xref: /freebsd/sys/contrib/device-tree/Bindings/mfd/nxp,lpc3220-scb.yaml (revision 0cd4430a9320c916a84617b6bbf400f5c64a09c7) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mfd/nxp,lpc3220-scb.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP LPC32xx System Control Block
8
9maintainers:
10  - Vladimir Zapolskiy <vz@mleia.com>
11
12description:
13  NXP LPC32xx SoC series have a System Control Block, which serves for
14  a multitude of purposes including clock management, DMA muxes, storing
15  SoC unique ID etc.
16
17properties:
18  compatible:
19    items:
20      - enum:
21          - nxp,lpc3220-scb
22      - const: syscon
23      - const: simple-mfd
24
25  reg:
26    maxItems: 1
27
28  ranges: true
29
30  "#address-cells":
31    const: 1
32
33  "#size-cells":
34    const: 1
35
36patternProperties:
37  "^clock-controller@[0-9a-f]+$":
38    $ref: /schemas/clock/nxp,lpc3220-clk.yaml#
39
40  "^dma-router@[0-9a-f]+$":
41    $ref: /schemas/dma/nxp,lpc3220-dmamux.yaml#
42
43required:
44  - compatible
45  - reg
46  - "#address-cells"
47  - "#size-cells"
48
49additionalProperties: false
50
51examples:
52  - |
53    syscon@400040000 {
54        compatible = "nxp,lpc3220-scb", "syscon", "simple-mfd";
55        reg = <0x40004000 0x1000>;
56        #address-cells = <1>;
57        #size-cells = <1>;
58        ranges = <0 0x40004000 0x1000>;
59
60        clock-controller@0 {
61            compatible = "nxp,lpc3220-clk";
62            reg = <0x0 0x114>;
63            clocks = <&xtal_32k>, <&xtal>;
64            clock-names = "xtal_32k", "xtal";
65            #clock-cells = <1>;
66        };
67
68        dma-router@78 {
69            compatible = "nxp,lpc3220-dmamux";
70            reg = <0x78 0x8>;
71            dma-masters = <&dma>;
72            #dma-cells = <3>;
73        };
74    };
75