1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/qcom,x1e80100-camss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm X1E80100 Camera Subsystem (CAMSS) 8 9maintainers: 10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org> 11 12description: 13 The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. 14 15properties: 16 compatible: 17 const: qcom,x1e80100-camss 18 19 reg: 20 maxItems: 17 21 22 reg-names: 23 items: 24 - const: csid0 25 - const: csid1 26 - const: csid2 27 - const: csid_lite0 28 - const: csid_lite1 29 - const: csid_wrapper 30 - const: csiphy0 31 - const: csiphy1 32 - const: csiphy2 33 - const: csiphy4 34 - const: csitpg0 35 - const: csitpg1 36 - const: csitpg2 37 - const: vfe0 38 - const: vfe1 39 - const: vfe_lite0 40 - const: vfe_lite1 41 42 clocks: 43 maxItems: 29 44 45 clock-names: 46 items: 47 - const: camnoc_nrt_axi 48 - const: camnoc_rt_axi 49 - const: core_ahb 50 - const: cpas_ahb 51 - const: cpas_fast_ahb 52 - const: cpas_vfe0 53 - const: cpas_vfe1 54 - const: cpas_vfe_lite 55 - const: cphy_rx_clk_src 56 - const: csid 57 - const: csid_csiphy_rx 58 - const: csiphy0 59 - const: csiphy0_timer 60 - const: csiphy1 61 - const: csiphy1_timer 62 - const: csiphy2 63 - const: csiphy2_timer 64 - const: csiphy4 65 - const: csiphy4_timer 66 - const: gcc_axi_hf 67 - const: gcc_axi_sf 68 - const: vfe0 69 - const: vfe0_fast_ahb 70 - const: vfe1 71 - const: vfe1_fast_ahb 72 - const: vfe_lite 73 - const: vfe_lite_ahb 74 - const: vfe_lite_cphy_rx 75 - const: vfe_lite_csid 76 77 interrupts: 78 maxItems: 13 79 80 interrupt-names: 81 items: 82 - const: csid0 83 - const: csid1 84 - const: csid2 85 - const: csid_lite0 86 - const: csid_lite1 87 - const: csiphy0 88 - const: csiphy1 89 - const: csiphy2 90 - const: csiphy4 91 - const: vfe0 92 - const: vfe1 93 - const: vfe_lite0 94 - const: vfe_lite1 95 96 interconnects: 97 maxItems: 4 98 99 interconnect-names: 100 items: 101 - const: ahb 102 - const: hf_mnoc 103 - const: sf_mnoc 104 - const: sf_icp_mnoc 105 106 iommus: 107 maxItems: 8 108 109 power-domains: 110 items: 111 - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. 112 - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. 113 - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. 114 115 power-domain-names: 116 items: 117 - const: ife0 118 - const: ife1 119 - const: top 120 121 vdd-csiphy-0p8-supply: 122 description: 123 Phandle to a 0.8V regulator supply to a PHY. 124 125 vdd-csiphy-1p2-supply: 126 description: 127 Phandle to 1.8V regulator supply to a PHY. 128 129 ports: 130 $ref: /schemas/graph.yaml#/properties/ports 131 132 description: 133 CSI input ports. 134 135 patternProperties: 136 "^port@[0-3]$": 137 $ref: /schemas/graph.yaml#/$defs/port-base 138 unevaluatedProperties: false 139 140 description: 141 Input port for receiving CSI data from a CSIPHY. 142 143 properties: 144 endpoint: 145 $ref: video-interfaces.yaml# 146 unevaluatedProperties: false 147 148 properties: 149 data-lanes: 150 minItems: 1 151 maxItems: 4 152 153 bus-type: 154 enum: 155 - 1 # MEDIA_BUS_TYPE_CSI2_CPHY 156 - 4 # MEDIA_BUS_TYPE_CSI2_DPHY 157 158 required: 159 - data-lanes 160 161required: 162 - compatible 163 - reg 164 - reg-names 165 - clocks 166 - clock-names 167 - interrupts 168 - interrupt-names 169 - interconnects 170 - interconnect-names 171 - iommus 172 - power-domains 173 - power-domain-names 174 - vdd-csiphy-0p8-supply 175 - vdd-csiphy-1p2-supply 176 - ports 177 178additionalProperties: false 179 180examples: 181 - | 182 #include <dt-bindings/interrupt-controller/arm-gic.h> 183 #include <dt-bindings/clock/qcom,x1e80100-gcc.h> 184 #include <dt-bindings/clock/qcom,x1e80100-camcc.h> 185 #include <dt-bindings/interconnect/qcom,icc.h> 186 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> 187 #include <dt-bindings/power/qcom-rpmpd.h> 188 189 soc { 190 #address-cells = <2>; 191 #size-cells = <2>; 192 193 camss: isp@acb7000 { 194 compatible = "qcom,x1e80100-camss"; 195 196 reg = <0 0x0acb7000 0 0x2000>, 197 <0 0x0acb9000 0 0x2000>, 198 <0 0x0acbb000 0 0x2000>, 199 <0 0x0acc6000 0 0x1000>, 200 <0 0x0acca000 0 0x1000>, 201 <0 0x0acb6000 0 0x1000>, 202 <0 0x0ace4000 0 0x1000>, 203 <0 0x0ace6000 0 0x1000>, 204 <0 0x0ace8000 0 0x1000>, 205 <0 0x0acec000 0 0x4000>, 206 <0 0x0acf6000 0 0x1000>, 207 <0 0x0acf7000 0 0x1000>, 208 <0 0x0acf8000 0 0x1000>, 209 <0 0x0ac62000 0 0x4000>, 210 <0 0x0ac71000 0 0x4000>, 211 <0 0x0acc7000 0 0x2000>, 212 <0 0x0accb000 0 0x2000>; 213 214 reg-names = "csid0", 215 "csid1", 216 "csid2", 217 "csid_lite0", 218 "csid_lite1", 219 "csid_wrapper", 220 "csiphy0", 221 "csiphy1", 222 "csiphy2", 223 "csiphy4", 224 "csitpg0", 225 "csitpg1", 226 "csitpg2", 227 "vfe0", 228 "vfe1", 229 "vfe_lite0", 230 "vfe_lite1"; 231 232 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 233 <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, 234 <&camcc CAM_CC_CORE_AHB_CLK>, 235 <&camcc CAM_CC_CPAS_AHB_CLK>, 236 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, 237 <&camcc CAM_CC_CPAS_IFE_0_CLK>, 238 <&camcc CAM_CC_CPAS_IFE_1_CLK>, 239 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, 240 <&camcc CAM_CC_CPHY_RX_CLK_SRC>, 241 <&camcc CAM_CC_CSID_CLK>, 242 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, 243 <&camcc CAM_CC_CSIPHY0_CLK>, 244 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 245 <&camcc CAM_CC_CSIPHY1_CLK>, 246 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 247 <&camcc CAM_CC_CSIPHY2_CLK>, 248 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 249 <&camcc CAM_CC_CSIPHY4_CLK>, 250 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 251 <&gcc GCC_CAMERA_HF_AXI_CLK>, 252 <&gcc GCC_CAMERA_SF_AXI_CLK>, 253 <&camcc CAM_CC_IFE_0_CLK>, 254 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, 255 <&camcc CAM_CC_IFE_1_CLK>, 256 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, 257 <&camcc CAM_CC_IFE_LITE_CLK>, 258 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 259 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 260 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 261 262 clock-names = "camnoc_nrt_axi", 263 "camnoc_rt_axi", 264 "core_ahb", 265 "cpas_ahb", 266 "cpas_fast_ahb", 267 "cpas_vfe0", 268 "cpas_vfe1", 269 "cpas_vfe_lite", 270 "cphy_rx_clk_src", 271 "csid", 272 "csid_csiphy_rx", 273 "csiphy0", 274 "csiphy0_timer", 275 "csiphy1", 276 "csiphy1_timer", 277 "csiphy2", 278 "csiphy2_timer", 279 "csiphy4", 280 "csiphy4_timer", 281 "gcc_axi_hf", 282 "gcc_axi_sf", 283 "vfe0", 284 "vfe0_fast_ahb", 285 "vfe1", 286 "vfe1_fast_ahb", 287 "vfe_lite", 288 "vfe_lite_ahb", 289 "vfe_lite_cphy_rx", 290 "vfe_lite_csid"; 291 292 interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 293 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 294 <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>, 295 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 296 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 297 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 298 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 299 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 300 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 301 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 302 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 303 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 304 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; 305 306 interrupt-names = "csid0", 307 "csid1", 308 "csid2", 309 "csid_lite0", 310 "csid_lite1", 311 "csiphy0", 312 "csiphy1", 313 "csiphy2", 314 "csiphy4", 315 "vfe0", 316 "vfe1", 317 "vfe_lite0", 318 "vfe_lite1"; 319 320 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 321 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 322 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 323 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 324 <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS 325 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 326 <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS 327 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 328 329 interconnect-names = "ahb", 330 "hf_mnoc", 331 "sf_mnoc", 332 "sf_icp_mnoc"; 333 334 iommus = <&apps_smmu 0x800 0x60>, 335 <&apps_smmu 0x860 0x60>, 336 <&apps_smmu 0x1800 0x60>, 337 <&apps_smmu 0x1860 0x60>, 338 <&apps_smmu 0x18e0 0x00>, 339 <&apps_smmu 0x1980 0x20>, 340 <&apps_smmu 0x1900 0x00>, 341 <&apps_smmu 0x19a0 0x20>; 342 343 power-domains = <&camcc CAM_CC_IFE_0_GDSC>, 344 <&camcc CAM_CC_IFE_1_GDSC>, 345 <&camcc CAM_CC_TITAN_TOP_GDSC>; 346 347 power-domain-names = "ife0", 348 "ife1", 349 "top"; 350 351 vdd-csiphy-0p8-supply = <&csiphy_0p8_supply>; 352 vdd-csiphy-1p2-supply = <&csiphy_1p2_supply>; 353 354 ports { 355 #address-cells = <1>; 356 #size-cells = <0>; 357 358 port@0 { 359 reg = <0>; 360 csiphy_ep0: endpoint { 361 data-lanes = <0 1>; 362 remote-endpoint = <&sensor_ep>; 363 }; 364 }; 365 }; 366 }; 367 }; 368