1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/edac/aspeed,ast2400-sdram-edac.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Aspeed BMC SoC SDRAM EDAC controller 8 9maintainers: 10 - Stefan Schaeckeler <sschaeck@cisco.com> 11 12description: > 13 The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error 14 correction check). 15 16 The memory controller supports SECDED (single bit error correction, double bit 17 error detection) and single bit error auto scrubbing by reserving 8 bits for 18 every 64 bit word (effectively reducing available memory to 8/9). 19 20 Note, the bootloader must configure ECC mode in the memory controller. 21 22properties: 23 compatible: 24 enum: 25 - aspeed,ast2400-sdram-edac 26 - aspeed,ast2500-sdram-edac 27 - aspeed,ast2600-sdram-edac 28 29 reg: 30 maxItems: 1 31 32 interrupts: 33 maxItems: 1 34 35required: 36 - compatible 37 - reg 38 - interrupts 39 40additionalProperties: false 41 42examples: 43 - | 44 sdram@1e6e0000 { 45 compatible = "aspeed,ast2500-sdram-edac"; 46 reg = <0x1e6e0000 0x174>; 47 interrupts = <0>; 48 }; 49