xref: /freebsd/sys/contrib/device-tree/Bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml (revision 2846c90520eb4cc74e24d586a0ea0f4a0006bc73) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip specific extensions to the Synopsys Designware MIPI DSI2
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12properties:
13  compatible:
14    enum:
15      - rockchip,rk3588-mipi-dsi2
16
17  reg:
18    maxItems: 1
19
20  interrupts:
21    maxItems: 1
22
23  clocks:
24    maxItems: 2
25
26  clock-names:
27    items:
28      - const: pclk
29      - const: sys
30
31  rockchip,grf:
32    $ref: /schemas/types.yaml#/definitions/phandle
33    description:
34      This SoC uses GRF regs to switch between vopl/vopb.
35
36  phys:
37    maxItems: 1
38
39  phy-names:
40    const: dcphy
41
42  power-domains:
43    maxItems: 1
44
45  resets:
46    maxItems: 1
47
48  reset-names:
49    const: apb
50
51  ports:
52    $ref: /schemas/graph.yaml#/properties/ports
53
54    properties:
55      port@0:
56        $ref: /schemas/graph.yaml#/properties/port
57        description: Input node to receive pixel data.
58
59      port@1:
60        $ref: /schemas/graph.yaml#/properties/port
61        description: DSI output node to panel.
62
63    required:
64      - port@0
65      - port@1
66
67required:
68  - compatible
69  - clocks
70  - clock-names
71  - rockchip,grf
72  - phys
73  - phy-names
74  - ports
75  - reg
76
77allOf:
78  - $ref: /schemas/display/dsi-controller.yaml#
79
80unevaluatedProperties: false
81
82examples:
83  - |
84    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
85    #include <dt-bindings/interrupt-controller/arm-gic.h>
86    #include <dt-bindings/interrupt-controller/irq.h>
87    #include <dt-bindings/phy/phy.h>
88    #include <dt-bindings/power/rk3588-power.h>
89    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
90
91    soc {
92      #address-cells = <2>;
93      #size-cells = <2>;
94
95      dsi@fde20000 {
96        compatible = "rockchip,rk3588-mipi-dsi2";
97        reg = <0x0 0xfde20000 0x0 0x10000>;
98        interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>;
99        clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>;
100        clock-names = "pclk", "sys";
101        resets = <&cru SRST_P_DSIHOST0>;
102        reset-names = "apb";
103        power-domains = <&power RK3588_PD_VOP>;
104        phys = <&mipidcphy0 PHY_TYPE_DPHY>;
105        phy-names = "dcphy";
106        rockchip,grf = <&vop_grf>;
107
108        ports {
109          #address-cells = <1>;
110          #size-cells = <0>;
111          dsi0_in: port@0 {
112            reg = <0>;
113          };
114
115          dsi0_out: port@1 {
116            reg = <1>;
117          };
118        };
119      };
120    };
121