xref: /freebsd/sys/contrib/device-tree/Bindings/display/rockchip/rockchip,dw-dp.yaml (revision 69ed3df4f588860308677cda76cbcce1f19a54c9) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-dp.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip DW DisplayPort Transmitter
8
9maintainers:
10  - Andy Yan <andy.yan@rock-chips.com>
11
12description: |
13  The Rockchip RK3588 SoC integrates the Synopsys DesignWare DPTX controller
14  which is compliant with the DisplayPort Specification Version 1.4 with the
15  following features:
16
17  * DisplayPort 1.4a
18  * Main Link: 1/2/4 lanes
19  * Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps
20  * AUX channel 1Mbps
21  * Single Stream Transport(SST)
22  * Multistream Transport (MST)
23  * Type-C support (alternate mode)
24  * HDCP 2.2, HDCP 1.3
25  * Supports up to 8/10 bits per color component
26  * Supports RBG, YCbCr4:4:4, YCbCr4:2:2, YCbCr4:2:0
27  * Pixel clock up to 594MHz
28  * I2S, SPDIF audio interface
29
30properties:
31  compatible:
32    enum:
33      - rockchip,rk3576-dp
34      - rockchip,rk3588-dp
35
36  reg:
37    maxItems: 1
38
39  interrupts:
40    maxItems: 1
41
42  clocks:
43    minItems: 3
44    items:
45      - description: Peripheral/APB bus clock
46      - description: DisplayPort AUX clock
47      - description: HDCP clock
48      - description: I2S interface clock
49      - description: SPDIF interfce clock
50
51  clock-names:
52    minItems: 3
53    items:
54      - const: apb
55      - const: aux
56      - const: hdcp
57      - const: i2s
58      - const: spdif
59
60  phys:
61    maxItems: 1
62
63  ports:
64    $ref: /schemas/graph.yaml#/properties/ports
65
66    properties:
67      port@0:
68        $ref: /schemas/graph.yaml#/properties/port
69        description: Video port for RGB/YUV input.
70
71      port@1:
72        $ref: /schemas/graph.yaml#/properties/port
73        description: Video port for DP output.
74
75    required:
76      - port@0
77      - port@1
78
79  power-domains:
80    maxItems: 1
81
82  resets:
83    maxItems: 1
84
85  "#sound-dai-cells":
86    const: 0
87
88required:
89  - compatible
90  - reg
91  - clocks
92  - clock-names
93  - interrupts
94  - phys
95  - ports
96  - resets
97
98allOf:
99  - $ref: /schemas/sound/dai-common.yaml#
100  - if:
101      properties:
102        compatible:
103          contains:
104            enum:
105              - rockchip,rk3588-dp
106    then:
107      properties:
108        clocks:
109          minItems: 5
110        clock-names:
111          minItems: 5
112    else:
113      properties:
114        clocks:
115          maxItems: 3
116        clock-names:
117          maxItems: 3
118
119unevaluatedProperties: false
120
121examples:
122  - |
123    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
124    #include <dt-bindings/phy/phy.h>
125    #include <dt-bindings/interrupt-controller/arm-gic.h>
126    #include <dt-bindings/interrupt-controller/irq.h>
127    #include <dt-bindings/power/rk3588-power.h>
128    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
129
130    soc {
131      #address-cells = <2>;
132      #size-cells = <2>;
133
134      dp@fde50000 {
135        compatible = "rockchip,rk3588-dp";
136        reg = <0x0 0xfde50000 0x0 0x4000>;
137        interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
138        clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>,
139        <&cru CLK_DP0>, <&cru MCLK_I2S4_8CH_TX>,
140        <&cru MCLK_SPDIF2_DP0>;
141        clock-names = "apb", "aux", "hdcp", "i2s", "spdif";
142        assigned-clocks = <&cru CLK_AUX16M_0>;
143        assigned-clock-rates = <16000000>;
144        resets = <&cru SRST_DP0>;
145        phys = <&usbdp_phy0 PHY_TYPE_DP>;
146        power-domains = <&power RK3588_PD_VO0>;
147        #sound-dai-cells = <0>;
148
149        ports {
150          #address-cells = <1>;
151          #size-cells = <0>;
152
153          port@0 {
154            reg = <0>;
155
156            dp0_in_vp2: endpoint {
157              remote-endpoint = <&vp2_out_dp0>;
158            };
159          };
160
161          port@1 {
162            reg = <1>;
163
164            dp0_out_con0: endpoint {
165              remote-endpoint = <&dp_con0_in>;
166            };
167          };
168        };
169      };
170    };
171