1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dpu-msm8998.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DPU dt properties for MSM8998 target 8 9maintainers: 10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> 11 12description: | 13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates 14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree 15 bindings of MDSS and DPU are mentioned for MSM8998 target. 16 17properties: 18 compatible: 19 items: 20 - const: qcom,msm8998-mdss 21 22 reg: 23 maxItems: 1 24 25 reg-names: 26 const: mdss 27 28 power-domains: 29 maxItems: 1 30 31 clocks: 32 items: 33 - description: Display AHB clock 34 - description: Display AXI clock 35 - description: Display core clock 36 37 clock-names: 38 items: 39 - const: iface 40 - const: bus 41 - const: core 42 43 interrupts: 44 maxItems: 1 45 46 interrupt-controller: true 47 48 "#address-cells": true 49 50 "#size-cells": true 51 52 "#interrupt-cells": 53 const: 1 54 55 iommus: 56 items: 57 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 58 59 ranges: true 60 61patternProperties: 62 "^display-controller@[0-9a-f]+$": 63 type: object 64 description: Node containing the properties of DPU. 65 additionalProperties: false 66 67 properties: 68 compatible: 69 items: 70 - const: qcom,msm8998-dpu 71 72 reg: 73 items: 74 - description: Address offset and size for mdp register set 75 - description: Address offset and size for regdma register set 76 - description: Address offset and size for vbif register set 77 - description: Address offset and size for non-realtime vbif register set 78 79 reg-names: 80 items: 81 - const: mdp 82 - const: regdma 83 - const: vbif 84 - const: vbif_nrt 85 86 clocks: 87 items: 88 - description: Display ahb clock 89 - description: Display axi clock 90 - description: Display mem-noc clock 91 - description: Display core clock 92 - description: Display vsync clock 93 94 clock-names: 95 items: 96 - const: iface 97 - const: bus 98 - const: mnoc 99 - const: core 100 - const: vsync 101 102 interrupts: 103 maxItems: 1 104 105 power-domains: 106 maxItems: 1 107 108 operating-points-v2: true 109 opp-table: 110 type: object 111 112 ports: 113 $ref: /schemas/graph.yaml#/properties/ports 114 description: | 115 Contains the list of output ports from DPU device. These ports 116 connect to interfaces that are external to the DPU hardware, 117 such as DSI, DP etc. Each output port contains an endpoint that 118 describes how it is connected to an external interface. 119 120 properties: 121 port@0: 122 $ref: /schemas/graph.yaml#/properties/port 123 description: DPU_INTF1 (DSI1) 124 125 port@1: 126 $ref: /schemas/graph.yaml#/properties/port 127 description: DPU_INTF2 (DSI2) 128 129 required: 130 - port@0 131 - port@1 132 133 required: 134 - compatible 135 - reg 136 - reg-names 137 - clocks 138 - interrupts 139 - power-domains 140 - operating-points-v2 141 - ports 142 143required: 144 - compatible 145 - reg 146 - reg-names 147 - power-domains 148 - clocks 149 - interrupts 150 - interrupt-controller 151 - iommus 152 - ranges 153 154additionalProperties: false 155 156examples: 157 - | 158 #include <dt-bindings/clock/qcom,mmcc-msm8998.h> 159 #include <dt-bindings/interrupt-controller/arm-gic.h> 160 #include <dt-bindings/power/qcom-rpmpd.h> 161 162 mdss: display-subsystem@c900000 { 163 compatible = "qcom,msm8998-mdss"; 164 reg = <0x0c900000 0x1000>; 165 reg-names = "mdss"; 166 167 clocks = <&mmcc MDSS_AHB_CLK>, 168 <&mmcc MDSS_AXI_CLK>, 169 <&mmcc MDSS_MDP_CLK>; 170 clock-names = "iface", "bus", "core"; 171 172 #address-cells = <1>; 173 #interrupt-cells = <1>; 174 #size-cells = <1>; 175 176 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 177 interrupt-controller; 178 iommus = <&mmss_smmu 0>; 179 180 power-domains = <&mmcc MDSS_GDSC>; 181 ranges; 182 183 display-controller@c901000 { 184 compatible = "qcom,msm8998-dpu"; 185 reg = <0x0c901000 0x8f000>, 186 <0x0c9a8e00 0xf0>, 187 <0x0c9b0000 0x2008>, 188 <0x0c9b8000 0x1040>; 189 reg-names = "mdp", "regdma", "vbif", "vbif_nrt"; 190 191 clocks = <&mmcc MDSS_AHB_CLK>, 192 <&mmcc MDSS_AXI_CLK>, 193 <&mmcc MNOC_AHB_CLK>, 194 <&mmcc MDSS_MDP_CLK>, 195 <&mmcc MDSS_VSYNC_CLK>; 196 clock-names = "iface", "bus", "mnoc", "core", "vsync"; 197 198 interrupt-parent = <&mdss>; 199 interrupts = <0>; 200 operating-points-v2 = <&mdp_opp_table>; 201 power-domains = <&rpmpd MSM8998_VDDMX>; 202 203 ports { 204 #address-cells = <1>; 205 #size-cells = <0>; 206 207 port@0 { 208 reg = <0>; 209 dpu_intf1_out: endpoint { 210 remote-endpoint = <&dsi0_in>; 211 }; 212 }; 213 214 port@1 { 215 reg = <1>; 216 dpu_intf2_out: endpoint { 217 remote-endpoint = <&dsi1_in>; 218 }; 219 }; 220 }; 221 }; 222 }; 223... 224