1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek Read Direct Memory Access 8 9maintainers: 10 - Chun-Kuang Hu <chunkuang.hu@kernel.org> 11 - Philipp Zabel <p.zabel@pengutronix.de> 12 13description: | 14 Mediatek Read Direct Memory Access(RDMA) component used to read the 15 data into DMA. It provides real time data to the back-end panel 16 driver, such as DSI, DPI and DP_INTF. 17 It contains one line buffer to store the sufficient pixel data. 18 RDMA device node must be siblings to the central MMSYS_CONFIG node. 19 For a description of the MMSYS_CONFIG binding, see 20 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml 21 for details. 22 23properties: 24 compatible: 25 oneOf: 26 - items: 27 - const: mediatek,mt2701-disp-rdma 28 - items: 29 - const: mediatek,mt8173-disp-rdma 30 - items: 31 - const: mediatek,mt8183-disp-rdma 32 - items: 33 - const: mediatek,mt8195-disp-rdma 34 - items: 35 - enum: 36 - mediatek,mt8188-disp-rdma 37 - const: mediatek,mt8195-disp-rdma 38 - items: 39 - enum: 40 - mediatek,mt7623-disp-rdma 41 - mediatek,mt2712-disp-rdma 42 - const: mediatek,mt2701-disp-rdma 43 - items: 44 - enum: 45 - mediatek,mt8186-disp-rdma 46 - mediatek,mt8192-disp-rdma 47 - const: mediatek,mt8183-disp-rdma 48 49 reg: 50 maxItems: 1 51 52 interrupts: 53 maxItems: 1 54 55 power-domains: 56 description: A phandle and PM domain specifier as defined by bindings of 57 the power controller specified by phandle. See 58 Documentation/devicetree/bindings/power/power-domain.yaml for details. 59 60 clocks: 61 items: 62 - description: RDMA Clock 63 64 iommus: 65 description: 66 This property should point to the respective IOMMU block with master port as argument, 67 see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. 68 69 mediatek,rdma-fifo-size: 70 description: 71 rdma fifo size may be different even in same SOC, add this property to the 72 corresponding rdma. 73 The value below is the Max value which defined in hardware data sheet 74 mediatek,rdma-fifo-size of mt8173-rdma0 is 8K 75 mediatek,rdma-fifo-size of mt8183-rdma0 is 5K 76 mediatek,rdma-fifo-size of mt8183-rdma1 is 2K 77 $ref: /schemas/types.yaml#/definitions/uint32 78 enum: [8192, 5120, 2048] 79 80 mediatek,gce-client-reg: 81 description: The register of client driver can be configured by gce with 82 4 arguments defined in this property, such as phandle of gce, subsys id, 83 register offset and size. Each GCE subsys id is mapping to a client 84 defined in the header include/dt-bindings/gce/<chip>-gce.h. 85 $ref: /schemas/types.yaml#/definitions/phandle-array 86 maxItems: 1 87 88required: 89 - compatible 90 - reg 91 - interrupts 92 - power-domains 93 - clocks 94 - iommus 95 96additionalProperties: false 97 98examples: 99 - | 100 #include <dt-bindings/interrupt-controller/arm-gic.h> 101 #include <dt-bindings/clock/mt8173-clk.h> 102 #include <dt-bindings/power/mt8173-power.h> 103 #include <dt-bindings/gce/mt8173-gce.h> 104 #include <dt-bindings/memory/mt8173-larb-port.h> 105 106 soc { 107 #address-cells = <2>; 108 #size-cells = <2>; 109 110 rdma0: rdma@1400e000 { 111 compatible = "mediatek,mt8173-disp-rdma"; 112 reg = <0 0x1400e000 0 0x1000>; 113 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 114 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 115 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 116 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 117 mediatek,rdma-fifo-size = <8192>; 118 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 119 }; 120 }; 121