1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek Read Direct Memory Access 8 9maintainers: 10 - Chun-Kuang Hu <chunkuang.hu@kernel.org> 11 - Philipp Zabel <p.zabel@pengutronix.de> 12 13description: | 14 Mediatek Read Direct Memory Access(RDMA) component used to read the 15 data into DMA. It provides real time data to the back-end panel 16 driver, such as DSI, DPI and DP_INTF. 17 It contains one line buffer to store the sufficient pixel data. 18 RDMA device node must be siblings to the central MMSYS_CONFIG node. 19 For a description of the MMSYS_CONFIG binding, see 20 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml 21 for details. 22 23properties: 24 compatible: 25 oneOf: 26 - enum: 27 - mediatek,mt2701-disp-rdma 28 - mediatek,mt8173-disp-rdma 29 - mediatek,mt8183-disp-rdma 30 - mediatek,mt8195-disp-rdma 31 - items: 32 - enum: 33 - mediatek,mt8188-disp-rdma 34 - const: mediatek,mt8195-disp-rdma 35 - items: 36 - enum: 37 - mediatek,mt7623-disp-rdma 38 - mediatek,mt2712-disp-rdma 39 - const: mediatek,mt2701-disp-rdma 40 - items: 41 - enum: 42 - mediatek,mt6795-disp-rdma 43 - const: mediatek,mt8173-disp-rdma 44 - items: 45 - enum: 46 - mediatek,mt8186-disp-rdma 47 - mediatek,mt8192-disp-rdma 48 - const: mediatek,mt8183-disp-rdma 49 50 reg: 51 maxItems: 1 52 53 interrupts: 54 maxItems: 1 55 56 power-domains: 57 description: A phandle and PM domain specifier as defined by bindings of 58 the power controller specified by phandle. See 59 Documentation/devicetree/bindings/power/power-domain.yaml for details. 60 61 clocks: 62 items: 63 - description: RDMA Clock 64 65 iommus: 66 description: 67 This property should point to the respective IOMMU block with master port as argument, 68 see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. 69 70 mediatek,rdma-fifo-size: 71 description: 72 rdma fifo size may be different even in same SOC, add this property to the 73 corresponding rdma. 74 The value below is the Max value which defined in hardware data sheet 75 mediatek,rdma-fifo-size of mt8173-rdma0 is 8K 76 mediatek,rdma-fifo-size of mt8183-rdma0 is 5K 77 mediatek,rdma-fifo-size of mt8183-rdma1 is 2K 78 $ref: /schemas/types.yaml#/definitions/uint32 79 enum: [8192, 5120, 2048] 80 81 mediatek,gce-client-reg: 82 description: The register of client driver can be configured by gce with 83 4 arguments defined in this property, such as phandle of gce, subsys id, 84 register offset and size. Each GCE subsys id is mapping to a client 85 defined in the header include/dt-bindings/gce/<chip>-gce.h. 86 $ref: /schemas/types.yaml#/definitions/phandle-array 87 maxItems: 1 88 89required: 90 - compatible 91 - reg 92 - interrupts 93 - power-domains 94 - clocks 95 - iommus 96 97additionalProperties: false 98 99examples: 100 - | 101 #include <dt-bindings/interrupt-controller/arm-gic.h> 102 #include <dt-bindings/clock/mt8173-clk.h> 103 #include <dt-bindings/power/mt8173-power.h> 104 #include <dt-bindings/gce/mt8173-gce.h> 105 #include <dt-bindings/memory/mt8173-larb-port.h> 106 107 soc { 108 #address-cells = <2>; 109 #size-cells = <2>; 110 111 rdma0: rdma@1400e000 { 112 compatible = "mediatek,mt8173-disp-rdma"; 113 reg = <0 0x1400e000 0 0x1000>; 114 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 115 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 116 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 117 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 118 mediatek,rdma-fifo-size = <8192>; 119 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 120 }; 121 }; 122