1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek Read Direct Memory Access 8 9maintainers: 10 - Chun-Kuang Hu <chunkuang.hu@kernel.org> 11 - Philipp Zabel <p.zabel@pengutronix.de> 12 13description: | 14 Mediatek Read Direct Memory Access(RDMA) component used to read the 15 data into DMA. It provides real time data to the back-end panel 16 driver, such as DSI, DPI and DP_INTF. 17 It contains one line buffer to store the sufficient pixel data. 18 RDMA device node must be siblings to the central MMSYS_CONFIG node. 19 For a description of the MMSYS_CONFIG binding, see 20 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml 21 for details. 22 23properties: 24 compatible: 25 oneOf: 26 - items: 27 - const: mediatek,mt2701-disp-rdma 28 - items: 29 - const: mediatek,mt8173-disp-rdma 30 - items: 31 - const: mediatek,mt8183-disp-rdma 32 - items: 33 - const: mediatek,mt8195-disp-rdma 34 - items: 35 - enum: 36 - mediatek,mt7623-disp-rdma 37 - mediatek,mt2712-disp-rdma 38 - enum: 39 - mediatek,mt2701-disp-rdma 40 - items: 41 - enum: 42 - mediatek,mt8192-disp-rdma 43 - enum: 44 - mediatek,mt8183-disp-rdma 45 46 reg: 47 maxItems: 1 48 49 interrupts: 50 maxItems: 1 51 52 power-domains: 53 description: A phandle and PM domain specifier as defined by bindings of 54 the power controller specified by phandle. See 55 Documentation/devicetree/bindings/power/power-domain.yaml for details. 56 57 clocks: 58 items: 59 - description: RDMA Clock 60 61 iommus: 62 description: 63 This property should point to the respective IOMMU block with master port as argument, 64 see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. 65 66 mediatek,rdma-fifo-size: 67 description: 68 rdma fifo size may be different even in same SOC, add this property to the 69 corresponding rdma. 70 The value below is the Max value which defined in hardware data sheet 71 mediatek,rdma-fifo-size of mt8173-rdma0 is 8K 72 mediatek,rdma-fifo-size of mt8183-rdma0 is 5K 73 mediatek,rdma-fifo-size of mt8183-rdma1 is 2K 74 $ref: /schemas/types.yaml#/definitions/uint32 75 enum: [8192, 5120, 2048] 76 77 mediatek,gce-client-reg: 78 description: The register of client driver can be configured by gce with 79 4 arguments defined in this property, such as phandle of gce, subsys id, 80 register offset and size. Each GCE subsys id is mapping to a client 81 defined in the header include/dt-bindings/gce/<chip>-gce.h. 82 $ref: /schemas/types.yaml#/definitions/phandle-array 83 maxItems: 1 84 85required: 86 - compatible 87 - reg 88 - interrupts 89 - power-domains 90 - clocks 91 - iommus 92 93additionalProperties: false 94 95examples: 96 - | 97 #include <dt-bindings/interrupt-controller/arm-gic.h> 98 #include <dt-bindings/clock/mt8173-clk.h> 99 #include <dt-bindings/power/mt8173-power.h> 100 #include <dt-bindings/gce/mt8173-gce.h> 101 #include <dt-bindings/memory/mt8173-larb-port.h> 102 103 soc { 104 #address-cells = <2>; 105 #size-cells = <2>; 106 107 rdma0: rdma@1400e000 { 108 compatible = "mediatek,mt8173-disp-rdma"; 109 reg = <0 0x1400e000 0 0x1000>; 110 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 111 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 112 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 113 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 114 mediatek,rdma-fifo-size = <8192>; 115 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 116 }; 117 }; 118