xref: /freebsd/sys/contrib/device-tree/Bindings/display/bridge/nwl-dsi.yaml (revision dc318a4ffabcbfa23bb56a33403aad36e6de30af) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Northwest Logic MIPI-DSI controller on i.MX SoCs
8
9maintainers:
10  - Guido Gúnther <agx@sigxcpu.org>
11  - Robert Chiras <robert.chiras@nxp.com>
12
13description: |
14  NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15  the SOCs NWL MIPI-DSI host controller.
16
17allOf:
18  - $ref: ../dsi-controller.yaml#
19
20properties:
21  compatible:
22    const: fsl,imx8mq-nwl-dsi
23
24  reg:
25    maxItems: 1
26
27  interrupts:
28    maxItems: 1
29
30  '#address-cells':
31    const: 1
32
33  '#size-cells':
34    const: 0
35
36  assigned-clock-parents: true
37  assigned-clock-rates: true
38  assigned-clocks: true
39
40  clocks:
41    items:
42      - description: DSI core clock
43      - description: RX_ESC clock (used in escape mode)
44      - description: TX_ESC clock (used in escape mode)
45      - description: PHY_REF clock
46      - description: LCDIF clock
47
48  clock-names:
49    items:
50      - const: core
51      - const: rx_esc
52      - const: tx_esc
53      - const: phy_ref
54      - const: lcdif
55
56  mux-controls:
57    description:
58      mux controller node to use for operating the input mux
59
60  phys:
61    maxItems: 1
62    description:
63      A phandle to the phy module representing the DPHY
64
65  phy-names:
66    items:
67      - const: dphy
68
69  power-domains:
70    maxItems: 1
71
72  resets:
73    items:
74      - description: dsi byte reset line
75      - description: dsi dpi reset line
76      - description: dsi esc reset line
77      - description: dsi pclk reset line
78
79  reset-names:
80    items:
81      - const: byte
82      - const: dpi
83      - const: esc
84      - const: pclk
85
86  ports:
87    type: object
88    description:
89      A node containing DSI input & output port nodes with endpoint
90      definitions as documented in
91      Documentation/devicetree/bindings/graph.txt.
92    properties:
93      port@0:
94        type: object
95        description:
96          Input port node to receive pixel data from the
97          display controller. Exactly one endpoint must be
98          specified.
99        properties:
100          '#address-cells':
101            const: 1
102
103          '#size-cells':
104            const: 0
105
106          endpoint@0:
107            description: sub-node describing the input from LCDIF
108            type: object
109
110          endpoint@1:
111            description: sub-node describing the input from DCSS
112            type: object
113
114          reg:
115            const: 0
116
117        required:
118          - '#address-cells'
119          - '#size-cells'
120          - reg
121
122        oneOf:
123          - required:
124              - endpoint@0
125          - required:
126              - endpoint@1
127
128        additionalProperties: false
129
130      port@1:
131        type: object
132        description:
133          DSI output port node to the panel or the next bridge
134          in the chain
135
136      '#address-cells':
137        const: 1
138
139      '#size-cells':
140        const: 0
141
142    required:
143      - '#address-cells'
144      - '#size-cells'
145      - port@0
146      - port@1
147
148    additionalProperties: false
149
150required:
151  - '#address-cells'
152  - '#size-cells'
153  - clock-names
154  - clocks
155  - compatible
156  - interrupts
157  - mux-controls
158  - phy-names
159  - phys
160  - ports
161  - reg
162  - reset-names
163  - resets
164
165unevaluatedProperties: false
166
167examples:
168  - |
169    #include <dt-bindings/clock/imx8mq-clock.h>
170    #include <dt-bindings/gpio/gpio.h>
171    #include <dt-bindings/interrupt-controller/arm-gic.h>
172    #include <dt-bindings/reset/imx8mq-reset.h>
173
174    dsi@30a00000 {
175              #address-cells = <1>;
176              #size-cells = <0>;
177              compatible = "fsl,imx8mq-nwl-dsi";
178              reg = <0x30A00000 0x300>;
179              clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
180                       <&clk IMX8MQ_CLK_DSI_AHB>,
181                       <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
182                       <&clk IMX8MQ_CLK_DSI_PHY_REF>,
183                       <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
184              clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
185              interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
186              mux-controls = <&mux 0>;
187              power-domains = <&pgc_mipi>;
188              resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
189                       <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
190                       <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
191                       <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
192              reset-names = "byte", "dpi", "esc", "pclk";
193              phys = <&dphy>;
194              phy-names = "dphy";
195
196              panel@0 {
197                      compatible = "rocktech,jh057n00900";
198                      reg = <0>;
199                      vcc-supply = <&reg_2v8_p>;
200                      iovcc-supply = <&reg_1v8_p>;
201                      reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
202                      port {
203                           panel_in: endpoint {
204                                     remote-endpoint = <&mipi_dsi_out>;
205                           };
206                      };
207              };
208
209              ports {
210                    #address-cells = <1>;
211                    #size-cells = <0>;
212
213                    port@0 {
214                           #size-cells = <0>;
215                           #address-cells = <1>;
216                           reg = <0>;
217                           mipi_dsi_in: endpoint@0 {
218                                        reg = <0>;
219                                        remote-endpoint = <&lcdif_mipi_dsi>;
220                           };
221                    };
222                    port@1 {
223                           reg = <1>;
224                           mipi_dsi_out: endpoint {
225                                         remote-endpoint = <&panel_in>;
226                           };
227                    };
228              };
229    };
230