xref: /freebsd/sys/contrib/device-tree/Bindings/clock/qcom,ipq9574-cmn-pll.yaml (revision 833e5d42ab135b0238e61c5b3c19b8619677cbfa)

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm CMN PLL Clock Controller on IPQ SoC

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Luo Jie <quic_luoj@quicinc.com>

description:
  The CMN (or common) PLL clock controller expects a reference
  input clock. This reference clock is from the on-board Wi-Fi.
  The CMN PLL supplies a number of fixed rate output clocks to
  the devices providing networking functions and to GCC. These
  networking hardware include PPE (packet process engine), PCS
  and the externally connected switch or PHY devices. The CMN
  PLL block also outputs fixed rate clocks to GCC. The PLL's
  primary function is to enable fixed rate output clocks for
  networking hardware functions used with the IPQ SoC.

properties:
  compatible:
    enum:
      - qcom,ipq5018-cmn-pll
      - qcom,ipq5424-cmn-pll
      - qcom,ipq9574-cmn-pll

  reg:
    maxItems: 1

  clocks:
    items:
      - description: The reference clock. The supported clock rates include
          25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ.
      - description: The AHB clock
      - description: The SYS clock
    description:
      The reference clock is the source clock of CMN PLL, which is from the
      Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL
      clock registers.

  clock-names:
    items:
      - const: ref
      - const: ahb
      - const: sys

  "#clock-cells":
    const: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - "#clock-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>

    cmn_pll: clock-controller@9b000 {
        compatible = "qcom,ipq9574-cmn-pll";
        reg = <0x0009b000 0x800>;
        clocks = <&cmn_pll_ref_clk>,
                 <&gcc GCC_CMN_12GPLL_AHB_CLK>,
                 <&gcc GCC_CMN_12GPLL_SYS_CLK>;
        clock-names = "ref", "ahb", "sys";
        #clock-cells = <1>;
        assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
        assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
    };
...