xref: /freebsd/sys/contrib/device-tree/Bindings/clock/qcom,ipq9574-cmn-pll.yaml (revision 833e5d42ab135b0238e61c5b3c19b8619677cbfa) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm CMN PLL Clock Controller on IPQ SoC
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Luo Jie <quic_luoj@quicinc.com>
12
13description:
14  The CMN (or common) PLL clock controller expects a reference
15  input clock. This reference clock is from the on-board Wi-Fi.
16  The CMN PLL supplies a number of fixed rate output clocks to
17  the devices providing networking functions and to GCC. These
18  networking hardware include PPE (packet process engine), PCS
19  and the externally connected switch or PHY devices. The CMN
20  PLL block also outputs fixed rate clocks to GCC. The PLL's
21  primary function is to enable fixed rate output clocks for
22  networking hardware functions used with the IPQ SoC.
23
24properties:
25  compatible:
26    enum:
27      - qcom,ipq5018-cmn-pll
28      - qcom,ipq5424-cmn-pll
29      - qcom,ipq9574-cmn-pll
30
31  reg:
32    maxItems: 1
33
34  clocks:
35    items:
36      - description: The reference clock. The supported clock rates include
37          25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ.
38      - description: The AHB clock
39      - description: The SYS clock
40    description:
41      The reference clock is the source clock of CMN PLL, which is from the
42      Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL
43      clock registers.
44
45  clock-names:
46    items:
47      - const: ref
48      - const: ahb
49      - const: sys
50
51  "#clock-cells":
52    const: 1
53
54required:
55  - compatible
56  - reg
57  - clocks
58  - clock-names
59  - "#clock-cells"
60
61additionalProperties: false
62
63examples:
64  - |
65    #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
66    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
67
68    cmn_pll: clock-controller@9b000 {
69        compatible = "qcom,ipq9574-cmn-pll";
70        reg = <0x0009b000 0x800>;
71        clocks = <&cmn_pll_ref_clk>,
72                 <&gcc GCC_CMN_12GPLL_AHB_CLK>,
73                 <&gcc GCC_CMN_12GPLL_SYS_CLK>;
74        clock-names = "ref", "ahb", "sys";
75        #clock-cells = <1>;
76        assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
77        assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
78    };
79...
80