1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/clock/amlogic,t7-peripherals-clkc.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Amlogic T7 Peripherals Clock Controller 9 10maintainers: 11 - Neil Armstrong <neil.armstrong@linaro.org> 12 - Jerome Brunet <jbrunet@baylibre.com> 13 - Xianwei Zhao <xianwei.zhao@amlogic.com> 14 - Jian Hu <jian.hu@amlogic.com> 15 16properties: 17 compatible: 18 const: amlogic,t7-peripherals-clkc 19 20 reg: 21 maxItems: 1 22 23 '#clock-cells': 24 const: 1 25 26 clocks: 27 minItems: 14 28 items: 29 - description: input oscillator 30 - description: input sys clk 31 - description: input fixed pll 32 - description: input fclk div 2 33 - description: input fclk div 2p5 34 - description: input fclk div 3 35 - description: input fclk div 4 36 - description: input fclk div 5 37 - description: input fclk div 7 38 - description: input hifi pll 39 - description: input gp0 pll 40 - description: input gp1 pll 41 - description: input mpll1 42 - description: input mpll2 43 - description: external input rmii oscillator (optional) 44 - description: input video pll0 (optional) 45 - description: external pad input for rtc (optional) 46 47 clock-names: 48 minItems: 14 49 items: 50 - const: xtal 51 - const: sys 52 - const: fix 53 - const: fdiv2 54 - const: fdiv2p5 55 - const: fdiv3 56 - const: fdiv4 57 - const: fdiv5 58 - const: fdiv7 59 - const: hifi 60 - const: gp0 61 - const: gp1 62 - const: mpll1 63 - const: mpll2 64 - const: ext_rmii 65 - const: vid_pll0 66 - const: ext_rtc 67 68required: 69 - compatible 70 - '#clock-cells' 71 - reg 72 - clocks 73 - clock-names 74 75additionalProperties: false 76 77examples: 78 - | 79 apb { 80 #address-cells = <2>; 81 #size-cells = <2>; 82 83 clkc_periphs:clock-controller@0 { 84 compatible = "amlogic,t7-peripherals-clkc"; 85 reg = <0 0x0 0 0x1c8>; 86 #clock-cells = <1>; 87 clocks = <&xtal>, 88 <&scmi_clk 13>, 89 <&scmi_clk 16>, 90 <&scmi_clk 18>, 91 <&scmi_clk 20>, 92 <&scmi_clk 22>, 93 <&scmi_clk 24>, 94 <&scmi_clk 26>, 95 <&scmi_clk 28>, 96 <&hifi 1>, 97 <&gp0 1>, 98 <&gp1 1>, 99 <&mpll 4>, 100 <&mpll 6>; 101 clock-names = "xtal", 102 "sys", 103 "fix", 104 "fdiv2", 105 "fdiv2p5", 106 "fdiv3", 107 "fdiv4", 108 "fdiv5", 109 "fdiv7", 110 "hifi", 111 "gp0", 112 "gp1", 113 "mpll1", 114 "mpll2"; 115 }; 116 }; 117