1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc.
3 *
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * Roy Luo <royluo@google.com>
6 * Felix Fietkau <nbd@nbd.name>
7 * Lorenzo Bianconi <lorenzo@kernel.org>
8 */
9
10 #include <linux/etherdevice.h>
11 #include <linux/timekeeping.h>
12 #if defined(__FreeBSD__)
13 #include <linux/delay.h>
14 #endif
15
16 #include "mt7615.h"
17 #include "../dma.h"
18 #include "mac.h"
19
20 static void
mt7615_write_fw_txp(struct mt7615_dev * dev,struct mt76_tx_info * tx_info,void * txp_ptr,u32 id)21 mt7615_write_fw_txp(struct mt7615_dev *dev, struct mt76_tx_info *tx_info,
22 void *txp_ptr, u32 id)
23 {
24 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data;
25 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
26 struct ieee80211_key_conf *key = info->control.hw_key;
27 struct ieee80211_vif *vif = info->control.vif;
28 struct mt76_connac_fw_txp *txp = txp_ptr;
29 u8 *rept_wds_wcid = (u8 *)&txp->rept_wds_wcid;
30 int nbuf = tx_info->nbuf - 1;
31 int i;
32
33 for (i = 0; i < nbuf; i++) {
34 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr);
35 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len);
36 }
37 txp->nbuf = nbuf;
38
39 /* pass partial skb header to fw */
40 tx_info->buf[0].len = MT_TXD_SIZE + sizeof(*txp);
41 tx_info->buf[1].len = MT_CT_PARSE_LEN;
42 tx_info->buf[1].skip_unmap = true;
43 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
44
45 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD);
46
47 if (!key)
48 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME);
49
50 if (ieee80211_is_mgmt(hdr->frame_control))
51 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME);
52
53 if (vif) {
54 struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv;
55
56 txp->bss_idx = mvif->idx;
57 }
58
59 txp->token = cpu_to_le16(id);
60 *rept_wds_wcid = 0xff;
61 }
62
mt7615_tx_prepare_skb(struct mt76_dev * mdev,void * txwi_ptr,enum mt76_txq_id qid,struct mt76_wcid * wcid,struct ieee80211_sta * sta,struct mt76_tx_info * tx_info)63 int mt7615_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
64 enum mt76_txq_id qid, struct mt76_wcid *wcid,
65 struct ieee80211_sta *sta,
66 struct mt76_tx_info *tx_info)
67 {
68 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
69 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
70 struct ieee80211_key_conf *key = info->control.hw_key;
71 int pid, id;
72 u8 *txwi = (u8 *)txwi_ptr;
73 struct mt76_txwi_cache *t;
74 struct mt7615_sta *msta;
75 void *txp;
76
77 msta = wcid ? container_of(wcid, struct mt7615_sta, wcid) : NULL;
78 if (!wcid)
79 wcid = &dev->mt76.global_wcid;
80
81 if ((info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) && msta) {
82 struct mt7615_phy *phy = &dev->phy;
83 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2;
84
85 if (phy_idx && mdev->phys[MT_BAND1])
86 phy = mdev->phys[MT_BAND1]->priv;
87
88 spin_lock_bh(&dev->mt76.lock);
89 mt7615_mac_set_rates(phy, msta, &info->control.rates[0],
90 msta->rates);
91 spin_unlock_bh(&dev->mt76.lock);
92 }
93
94 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size);
95 t->skb = tx_info->skb;
96
97 id = mt76_token_get(mdev, &t);
98 if (id < 0)
99 return id;
100
101 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb);
102 mt7615_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, sta,
103 pid, key, qid, false);
104
105 txp = txwi + MT_TXD_SIZE;
106 memset(txp, 0, sizeof(struct mt76_connac_txp_common));
107 if (is_mt7615(&dev->mt76))
108 mt7615_write_fw_txp(dev, tx_info, txp, id);
109 else
110 mt76_connac_write_hw_txp(mdev, tx_info, txp, id);
111
112 tx_info->skb = DMA_DUMMY_DATA;
113
114 return 0;
115 }
116
mt7615_dma_reset(struct mt7615_dev * dev)117 void mt7615_dma_reset(struct mt7615_dev *dev)
118 {
119 int i;
120
121 mt76_clear(dev, MT_WPDMA_GLO_CFG,
122 MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN |
123 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
124
125 usleep_range(1000, 2000);
126
127 for (i = 0; i < __MT_TXQ_MAX; i++)
128 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);
129
130 for (i = 0; i < __MT_MCUQ_MAX; i++)
131 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true);
132
133 mt76_for_each_q_rx(&dev->mt76, i)
134 mt76_queue_rx_reset(dev, i);
135
136 mt76_tx_status_check(&dev->mt76, true);
137
138 mt7615_dma_start(dev);
139 }
140 EXPORT_SYMBOL_GPL(mt7615_dma_reset);
141
142 static void
mt7615_hif_int_event_trigger(struct mt7615_dev * dev,u8 event)143 mt7615_hif_int_event_trigger(struct mt7615_dev *dev, u8 event)
144 {
145 u32 reg = MT_MCU_INT_EVENT;
146
147 if (is_mt7663(&dev->mt76))
148 reg = MT7663_MCU_INT_EVENT;
149
150 mt76_wr(dev, reg, event);
151
152 mt7622_trigger_hif_int(dev, true);
153 mt7622_trigger_hif_int(dev, false);
154 }
155
156 static bool
mt7615_wait_reset_state(struct mt7615_dev * dev,u32 state)157 mt7615_wait_reset_state(struct mt7615_dev *dev, u32 state)
158 {
159 bool ret;
160
161 ret = wait_event_timeout(dev->reset_wait,
162 (READ_ONCE(dev->reset_state) & state),
163 MT7615_RESET_TIMEOUT);
164 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state);
165 return ret;
166 }
167
168 static void
mt7615_update_vif_beacon(void * priv,u8 * mac,struct ieee80211_vif * vif)169 mt7615_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif)
170 {
171 struct ieee80211_hw *hw = priv;
172 struct mt7615_dev *dev = mt7615_hw_dev(hw);
173
174 switch (vif->type) {
175 case NL80211_IFTYPE_MESH_POINT:
176 case NL80211_IFTYPE_ADHOC:
177 case NL80211_IFTYPE_AP:
178 mt7615_mcu_add_beacon(dev, hw, vif,
179 vif->bss_conf.enable_beacon);
180 break;
181 default:
182 break;
183 }
184 }
185
186 static void
mt7615_update_beacons(struct mt7615_dev * dev)187 mt7615_update_beacons(struct mt7615_dev *dev)
188 {
189 struct mt76_phy *mphy_ext = dev->mt76.phys[MT_BAND1];
190
191 ieee80211_iterate_active_interfaces(dev->mt76.hw,
192 IEEE80211_IFACE_ITER_RESUME_ALL,
193 mt7615_update_vif_beacon, dev->mt76.hw);
194
195 if (!mphy_ext)
196 return;
197
198 ieee80211_iterate_active_interfaces(mphy_ext->hw,
199 IEEE80211_IFACE_ITER_RESUME_ALL,
200 mt7615_update_vif_beacon, mphy_ext->hw);
201 }
202
mt7615_mac_reset_work(struct work_struct * work)203 void mt7615_mac_reset_work(struct work_struct *work)
204 {
205 struct mt7615_phy *phy2;
206 struct mt76_phy *ext_phy;
207 struct mt7615_dev *dev;
208 unsigned long timeout;
209 int i;
210
211 dev = container_of(work, struct mt7615_dev, reset_work);
212 ext_phy = dev->mt76.phys[MT_BAND1];
213 phy2 = ext_phy ? ext_phy->priv : NULL;
214
215 if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_PDMA))
216 return;
217
218 ieee80211_stop_queues(mt76_hw(dev));
219 if (ext_phy)
220 ieee80211_stop_queues(ext_phy->hw);
221
222 set_bit(MT76_RESET, &dev->mphy.state);
223 set_bit(MT76_MCU_RESET, &dev->mphy.state);
224 wake_up(&dev->mt76.mcu.wait);
225 cancel_delayed_work_sync(&dev->mphy.mac_work);
226 del_timer_sync(&dev->phy.roc_timer);
227 cancel_work_sync(&dev->phy.roc_work);
228 if (phy2) {
229 set_bit(MT76_RESET, &phy2->mt76->state);
230 cancel_delayed_work_sync(&phy2->mt76->mac_work);
231 del_timer_sync(&phy2->roc_timer);
232 cancel_work_sync(&phy2->roc_work);
233 }
234
235 /* lock/unlock all queues to ensure that no tx is pending */
236 mt76_txq_schedule_all(&dev->mphy);
237 if (ext_phy)
238 mt76_txq_schedule_all(ext_phy);
239
240 mt76_worker_disable(&dev->mt76.tx_worker);
241 mt76_for_each_q_rx(&dev->mt76, i)
242 napi_disable(&dev->mt76.napi[i]);
243 napi_disable(&dev->mt76.tx_napi);
244
245 mt7615_mutex_acquire(dev);
246
247 mt7615_hif_int_event_trigger(dev, MT_MCU_INT_EVENT_PDMA_STOPPED);
248
249 if (mt7615_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) {
250 mt7615_dma_reset(dev);
251
252 mt7615_tx_token_put(dev);
253 idr_init(&dev->mt76.token);
254
255 mt76_wr(dev, MT_WPDMA_MEM_RNG_ERR, 0);
256
257 mt7615_hif_int_event_trigger(dev, MT_MCU_INT_EVENT_PDMA_INIT);
258 mt7615_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE);
259 }
260
261 clear_bit(MT76_MCU_RESET, &dev->mphy.state);
262 clear_bit(MT76_RESET, &dev->mphy.state);
263 if (phy2)
264 clear_bit(MT76_RESET, &phy2->mt76->state);
265
266 mt76_worker_enable(&dev->mt76.tx_worker);
267
268 local_bh_disable();
269 napi_enable(&dev->mt76.tx_napi);
270 napi_schedule(&dev->mt76.tx_napi);
271
272 mt76_for_each_q_rx(&dev->mt76, i) {
273 napi_enable(&dev->mt76.napi[i]);
274 napi_schedule(&dev->mt76.napi[i]);
275 }
276 local_bh_enable();
277
278 ieee80211_wake_queues(mt76_hw(dev));
279 if (ext_phy)
280 ieee80211_wake_queues(ext_phy->hw);
281
282 mt7615_hif_int_event_trigger(dev, MT_MCU_INT_EVENT_RESET_DONE);
283 mt7615_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE);
284
285 mt7615_update_beacons(dev);
286
287 mt7615_mutex_release(dev);
288
289 timeout = mt7615_get_macwork_timeout(dev);
290 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work,
291 timeout);
292 if (phy2)
293 ieee80211_queue_delayed_work(ext_phy->hw,
294 &phy2->mt76->mac_work, timeout);
295
296 }
297