1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2017 Intel Deutschland GmbH
4 * Copyright (C) 2018-2025 Intel Corporation
5 */
6 #if defined(__FreeBSD__)
7 #include <linux/delay.h>
8 #endif
9 #include "iwl-trans.h"
10 #include "iwl-prph.h"
11 #include "pcie/iwl-context-info.h"
12 #include "pcie/iwl-context-info-v2.h"
13 #include "internal.h"
14 #include "fw/dbg.h"
15
16 #define FW_RESET_TIMEOUT (HZ / 5)
17
18 /*
19 * Start up NIC's basic functionality after it has been reset
20 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
21 * NOTE: This does not load uCode nor start the embedded processor
22 */
iwl_pcie_gen2_apm_init(struct iwl_trans * trans)23 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
24 {
25 int ret = 0;
26
27 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
28
29 /*
30 * Use "set_bit" below rather than "write", to preserve any hardware
31 * bits already set by default after reset.
32 */
33
34 /*
35 * Disable L0s without affecting L1;
36 * don't wait for ICH L0s (ICH bug W/A)
37 */
38 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
39 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
40
41 /* Set FH wait threshold to maximum (HW error during stress W/A) */
42 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
43
44 /*
45 * Enable HAP INTA (interrupt from management bus) to
46 * wake device's PCI Express link L1a -> L0s
47 */
48 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
49 CSR_HW_IF_CONFIG_REG_HAP_WAKE);
50
51 iwl_pcie_apm_config(trans);
52
53 ret = iwl_finish_nic_init(trans);
54 if (ret)
55 return ret;
56
57 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
58
59 return 0;
60 }
61
iwl_pcie_gen2_apm_stop(struct iwl_trans * trans,bool op_mode_leave)62 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
63 {
64 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
65
66 if (op_mode_leave) {
67 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
68 iwl_pcie_gen2_apm_init(trans);
69
70 /* inform ME that we are leaving */
71 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
72 CSR_RESET_LINK_PWR_MGMT_DISABLED);
73 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
74 CSR_HW_IF_CONFIG_REG_WAKE_ME |
75 CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN);
76 mdelay(1);
77 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
78 CSR_RESET_LINK_PWR_MGMT_DISABLED);
79 mdelay(5);
80 }
81
82 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
83
84 /* Stop device's DMA activity */
85 iwl_pcie_apm_stop_master(trans);
86
87 iwl_trans_pcie_sw_reset(trans, false);
88
89 /*
90 * Clear "initialization complete" bit to move adapter from
91 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
92 */
93 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
94 iwl_clear_bit(trans, CSR_GP_CNTRL,
95 CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
96 else
97 iwl_clear_bit(trans, CSR_GP_CNTRL,
98 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
99 }
100
iwl_trans_pcie_fw_reset_handshake(struct iwl_trans * trans)101 void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans)
102 {
103 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
104 int ret;
105
106 trans_pcie->fw_reset_state = FW_RESET_REQUESTED;
107
108 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
109 iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,
110 UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE);
111 else if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_AX210)
112 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
113 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
114 else
115 iwl_write32(trans, CSR_DOORBELL_VECTOR,
116 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
117
118 /* wait 200ms */
119 ret = wait_event_timeout(trans_pcie->fw_reset_waitq,
120 trans_pcie->fw_reset_state != FW_RESET_REQUESTED,
121 FW_RESET_TIMEOUT);
122 if (!ret || trans_pcie->fw_reset_state == FW_RESET_ERROR) {
123 bool reset_done;
124 u32 inta_hw;
125
126 if (trans_pcie->msix_enabled) {
127 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
128 reset_done =
129 inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE;
130 } else {
131 inta_hw = iwl_read32(trans, CSR_INT);
132 reset_done = inta_hw & CSR_INT_BIT_RESET_DONE;
133 }
134
135 IWL_ERR(trans,
136 "timeout waiting for FW reset ACK (inta_hw=0x%x, reset_done %d)\n",
137 inta_hw, reset_done);
138
139 if (!reset_done) {
140 struct iwl_fw_error_dump_mode mode = {
141 .type = IWL_ERR_TYPE_RESET_HS_TIMEOUT,
142 .context = IWL_ERR_CONTEXT_FROM_OPMODE,
143 };
144 iwl_op_mode_nic_error(trans->op_mode,
145 IWL_ERR_TYPE_RESET_HS_TIMEOUT);
146 iwl_op_mode_dump_error(trans->op_mode, &mode);
147 }
148 }
149
150 trans_pcie->fw_reset_state = FW_RESET_IDLE;
151 }
152
_iwl_trans_pcie_gen2_stop_device(struct iwl_trans * trans)153 static void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
154 {
155 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
156
157 lockdep_assert_held(&trans_pcie->mutex);
158
159 if (trans_pcie->is_down)
160 return;
161
162 if (trans->state >= IWL_TRANS_FW_STARTED &&
163 trans->conf.fw_reset_handshake) {
164 /*
165 * Reset handshake can dump firmware on timeout, but that
166 * should assume that the firmware is already dead.
167 */
168 trans->state = IWL_TRANS_NO_FW;
169 iwl_trans_pcie_fw_reset_handshake(trans);
170 }
171
172 trans_pcie->is_down = true;
173
174 /* tell the device to stop sending interrupts */
175 iwl_disable_interrupts(trans);
176
177 /* device going down, Stop using ICT table */
178 iwl_pcie_disable_ict(trans);
179
180 /*
181 * If a HW restart happens during firmware loading,
182 * then the firmware loading might call this function
183 * and later it might be called again due to the
184 * restart. So don't process again if the device is
185 * already dead.
186 */
187 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
188 IWL_DEBUG_INFO(trans,
189 "DEVICE_ENABLED bit was set and is now cleared\n");
190 iwl_pcie_synchronize_irqs(trans);
191 iwl_pcie_rx_napi_sync(trans);
192 iwl_txq_gen2_tx_free(trans);
193 iwl_pcie_rx_stop(trans);
194 }
195
196 iwl_pcie_ctxt_info_free_paging(trans);
197 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
198 iwl_pcie_ctxt_info_v2_free(trans, false);
199 else
200 iwl_pcie_ctxt_info_free(trans);
201
202 /* Stop the device, and put it in low power state */
203 iwl_pcie_gen2_apm_stop(trans, false);
204
205 /* re-take ownership to prevent other users from stealing the device */
206 iwl_trans_pcie_sw_reset(trans, true);
207
208 /*
209 * Upon stop, the IVAR table gets erased, so msi-x won't
210 * work. This causes a bug in RF-KILL flows, since the interrupt
211 * that enables radio won't fire on the correct irq, and the
212 * driver won't be able to handle the interrupt.
213 * Configure the IVAR table again after reset.
214 */
215 iwl_pcie_conf_msix_hw(trans_pcie);
216
217 /*
218 * Upon stop, the APM issues an interrupt if HW RF kill is set.
219 * This is a bug in certain verions of the hardware.
220 * Certain devices also keep sending HW RF kill interrupt all
221 * the time, unless the interrupt is ACKed even if the interrupt
222 * should be masked. Re-ACK all the interrupts here.
223 */
224 iwl_disable_interrupts(trans);
225
226 /* clear all status bits */
227 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
228 clear_bit(STATUS_INT_ENABLED, &trans->status);
229 clear_bit(STATUS_TPOWER_PMI, &trans->status);
230
231 /*
232 * Even if we stop the HW, we still want the RF kill
233 * interrupt
234 */
235 iwl_enable_rfkill_int(trans);
236 }
237
iwl_trans_pcie_gen2_stop_device(struct iwl_trans * trans)238 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
239 {
240 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
241 bool was_in_rfkill;
242
243 iwl_op_mode_time_point(trans->op_mode,
244 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
245 NULL);
246
247 mutex_lock(&trans_pcie->mutex);
248 trans_pcie->opmode_down = true;
249 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
250 _iwl_trans_pcie_gen2_stop_device(trans);
251 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
252 mutex_unlock(&trans_pcie->mutex);
253 }
254
iwl_pcie_gen2_nic_init(struct iwl_trans * trans)255 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
256 {
257 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
258 int queue_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
259 trans->mac_cfg->base->min_txq_size);
260 int ret;
261
262 /* TODO: most of the logic can be removed in A0 - but not in Z0 */
263 spin_lock_bh(&trans_pcie->irq_lock);
264 ret = iwl_pcie_gen2_apm_init(trans);
265 spin_unlock_bh(&trans_pcie->irq_lock);
266 if (ret)
267 return ret;
268
269 iwl_op_mode_nic_config(trans->op_mode);
270
271 /* Allocate the RX queue, or reset if it is already allocated */
272 if (iwl_pcie_gen2_rx_init(trans))
273 return -ENOMEM;
274
275 /* Allocate or reset and init all Tx and Command queues */
276 if (iwl_txq_gen2_init(trans, trans->conf.cmd_queue, queue_size))
277 return -ENOMEM;
278
279 /* enable shadow regs in HW */
280 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
281 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
282
283 return 0;
284 }
285
iwl_pcie_get_rf_name(struct iwl_trans * trans)286 static void iwl_pcie_get_rf_name(struct iwl_trans *trans)
287 {
288 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
289 char *buf = trans_pcie->rf_name;
290 size_t buflen = sizeof(trans_pcie->rf_name);
291 size_t pos;
292 u32 version;
293
294 if (buf[0])
295 return;
296
297 switch (CSR_HW_RFID_TYPE(trans->info.hw_rf_id)) {
298 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_JF):
299 pos = scnprintf(buf, buflen, "JF");
300 break;
301 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF):
302 pos = scnprintf(buf, buflen, "GF");
303 break;
304 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF4):
305 pos = scnprintf(buf, buflen, "GF4");
306 break;
307 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
308 pos = scnprintf(buf, buflen, "HR");
309 break;
310 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
311 pos = scnprintf(buf, buflen, "HR1");
312 break;
313 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
314 pos = scnprintf(buf, buflen, "HRCDB");
315 break;
316 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_FM):
317 pos = scnprintf(buf, buflen, "FM");
318 break;
319 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_WP):
320 if (SILICON_Z_STEP ==
321 CSR_HW_RFID_STEP(trans->info.hw_rf_id))
322 pos = scnprintf(buf, buflen, "WHTC");
323 else
324 pos = scnprintf(buf, buflen, "WH");
325 break;
326 default:
327 return;
328 }
329
330 switch (CSR_HW_RFID_TYPE(trans->info.hw_rf_id)) {
331 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
332 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
333 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
334 version = iwl_read_prph(trans, CNVI_MBOX_C);
335 switch (version) {
336 case 0x20000:
337 pos += scnprintf(buf + pos, buflen - pos, " B3");
338 break;
339 case 0x120000:
340 pos += scnprintf(buf + pos, buflen - pos, " B5");
341 break;
342 default:
343 pos += scnprintf(buf + pos, buflen - pos,
344 " (0x%x)", version);
345 break;
346 }
347 break;
348 default:
349 break;
350 }
351
352 pos += scnprintf(buf + pos, buflen - pos, ", rfid=0x%x",
353 trans->info.hw_rf_id);
354
355 IWL_INFO(trans, "Detected RF %s\n", buf);
356
357 /*
358 * also add a \n for debugfs - need to do it after printing
359 * since our IWL_INFO machinery wants to see a static \n at
360 * the end of the string
361 */
362 pos += scnprintf(buf + pos, buflen - pos, "\n");
363 }
364
iwl_trans_pcie_gen2_fw_alive(struct iwl_trans * trans)365 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans)
366 {
367 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
368
369 iwl_pcie_reset_ict(trans);
370
371 /* make sure all queue are not stopped/used */
372 memset(trans_pcie->txqs.queue_stopped, 0,
373 sizeof(trans_pcie->txqs.queue_stopped));
374 memset(trans_pcie->txqs.queue_used, 0,
375 sizeof(trans_pcie->txqs.queue_used));
376
377 /* now that we got alive we can free the fw image & the context info.
378 * paging memory cannot be freed included since FW will still use it
379 */
380 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
381 iwl_pcie_ctxt_info_v2_free(trans, true);
382 else
383 iwl_pcie_ctxt_info_free(trans);
384
385 /*
386 * Re-enable all the interrupts, including the RF-Kill one, now that
387 * the firmware is alive.
388 */
389 iwl_enable_interrupts(trans);
390 mutex_lock(&trans_pcie->mutex);
391 iwl_pcie_check_hw_rf_kill(trans);
392
393 iwl_pcie_get_rf_name(trans);
394 mutex_unlock(&trans_pcie->mutex);
395
396 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
397 trans->step_urm = !!(iwl_read_umac_prph(trans,
398 CNVI_PMU_STEP_FLOW) &
399 CNVI_PMU_STEP_FLOW_FORCE_URM);
400 }
401
iwl_pcie_set_ltr(struct iwl_trans * trans)402 static bool iwl_pcie_set_ltr(struct iwl_trans *trans)
403 {
404 u32 ltr_val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ |
405 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
406 CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) |
407 u32_encode_bits(250,
408 CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) |
409 CSR_LTR_LONG_VAL_AD_SNOOP_REQ |
410 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
411 CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) |
412 u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL);
413
414 /*
415 * To workaround hardware latency issues during the boot process,
416 * initialize the LTR to ~250 usec (see ltr_val above).
417 * The firmware initializes this again later (to a smaller value).
418 */
419 if ((trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_AX210 ||
420 trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_22000) &&
421 !trans->mac_cfg->integrated) {
422 iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);
423 return true;
424 }
425
426 if (trans->mac_cfg->integrated &&
427 trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_22000) {
428 iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);
429 iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val);
430 return true;
431 }
432
433 if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_AX210) {
434 /* First clear the interrupt, just in case */
435 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD,
436 MSIX_HW_INT_CAUSES_REG_IML);
437 /* In this case, unfortunately the same ROM bug exists in the
438 * device (not setting LTR correctly), but we don't have control
439 * over the settings from the host due to some hardware security
440 * features. The only workaround we've been able to come up with
441 * so far is to try to keep the CPU and device busy by polling
442 * it and the IML (image loader) completed interrupt.
443 */
444 return false;
445 }
446
447 /* nothing needs to be done on other devices */
448 return true;
449 }
450
iwl_pcie_spin_for_iml(struct iwl_trans * trans)451 static void iwl_pcie_spin_for_iml(struct iwl_trans *trans)
452 {
453 /* in practice, this seems to complete in around 20-30ms at most, wait 100 */
454 #define IML_WAIT_TIMEOUT (HZ / 10)
455 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
456 unsigned long end_time = jiffies + IML_WAIT_TIMEOUT;
457 u32 value, loops = 0;
458 bool irq = false;
459
460 if (WARN_ON(!trans_pcie->iml))
461 return;
462
463 value = iwl_read32(trans, CSR_LTR_LAST_MSG);
464 IWL_DEBUG_INFO(trans, "Polling for IML load - CSR_LTR_LAST_MSG=0x%x\n",
465 value);
466
467 while (time_before(jiffies, end_time)) {
468 if (iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD) &
469 MSIX_HW_INT_CAUSES_REG_IML) {
470 irq = true;
471 break;
472 }
473 /* Keep the CPU and device busy. */
474 value = iwl_read32(trans, CSR_LTR_LAST_MSG);
475 loops++;
476 }
477
478 IWL_DEBUG_INFO(trans,
479 "Polled for IML load: irq=%d, loops=%d, CSR_LTR_LAST_MSG=0x%x\n",
480 irq, loops, value);
481
482 /* We don't fail here even if we timed out - maybe we get lucky and the
483 * interrupt comes in later (and we get alive from firmware) and then
484 * we're all happy - but if not we'll fail on alive timeout or get some
485 * other error out.
486 */
487 }
488
iwl_trans_pcie_gen2_start_fw(struct iwl_trans * trans,const struct iwl_fw * fw,const struct fw_img * img,bool run_in_rfkill)489 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
490 const struct iwl_fw *fw,
491 const struct fw_img *img,
492 bool run_in_rfkill)
493 {
494 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
495 bool hw_rfkill, keep_ram_busy;
496 bool top_reset_done = false;
497 int ret;
498
499 mutex_lock(&trans_pcie->mutex);
500 again:
501 /* This may fail if AMT took ownership of the device */
502 if (iwl_pcie_prepare_card_hw(trans)) {
503 IWL_WARN(trans, "Exit HW not ready\n");
504 ret = -EIO;
505 goto out;
506 }
507
508 iwl_enable_rfkill_int(trans);
509
510 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
511
512 /*
513 * We enabled the RF-Kill interrupt and the handler may very
514 * well be running. Disable the interrupts to make sure no other
515 * interrupt can be fired.
516 */
517 iwl_disable_interrupts(trans);
518
519 /* Make sure it finished running */
520 iwl_pcie_synchronize_irqs(trans);
521
522 /* If platform's RF_KILL switch is NOT set to KILL */
523 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
524 if (hw_rfkill && !run_in_rfkill) {
525 ret = -ERFKILL;
526 goto out;
527 }
528
529 /* Someone called stop_device, don't try to start_fw */
530 if (trans_pcie->is_down) {
531 IWL_WARN(trans,
532 "Can't start_fw since the HW hasn't been started\n");
533 ret = -EIO;
534 goto out;
535 }
536
537 /* make sure rfkill handshake bits are cleared */
538 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
539 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
540 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
541
542 /* clear (again), then enable host interrupts */
543 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
544
545 ret = iwl_pcie_gen2_nic_init(trans);
546 if (ret) {
547 IWL_ERR(trans, "Unable to init nic\n");
548 goto out;
549 }
550
551 if (WARN_ON(trans->do_top_reset &&
552 trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_SC)) {
553 ret = -EINVAL;
554 goto out;
555 }
556
557 /* we need to wait later - set state */
558 if (trans->do_top_reset)
559 trans_pcie->fw_reset_state = FW_RESET_TOP_REQUESTED;
560
561 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
562 if (!top_reset_done) {
563 ret = iwl_pcie_ctxt_info_v2_alloc(trans, fw, img);
564 if (ret)
565 goto out;
566 }
567
568 iwl_pcie_ctxt_info_v2_kick(trans);
569 } else {
570 ret = iwl_pcie_ctxt_info_init(trans, img);
571 if (ret)
572 goto out;
573 }
574
575 keep_ram_busy = !iwl_pcie_set_ltr(trans);
576
577 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
578 IWL_DEBUG_POWER(trans, "function scratch register value is 0x%08x\n",
579 iwl_read32(trans, CSR_FUNC_SCRATCH));
580 iwl_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE);
581 iwl_set_bit(trans, CSR_GP_CNTRL,
582 CSR_GP_CNTRL_REG_FLAG_ROM_START);
583 } else if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
584 iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);
585 } else {
586 iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);
587 }
588
589 if (keep_ram_busy)
590 iwl_pcie_spin_for_iml(trans);
591
592 if (trans->do_top_reset) {
593 trans->do_top_reset = 0;
594
595 #define FW_TOP_RESET_TIMEOUT (HZ / 4)
596 ret = wait_event_timeout(trans_pcie->fw_reset_waitq,
597 trans_pcie->fw_reset_state != FW_RESET_TOP_REQUESTED,
598 FW_TOP_RESET_TIMEOUT);
599
600 if (trans_pcie->fw_reset_state != FW_RESET_OK) {
601 if (trans_pcie->fw_reset_state != FW_RESET_TOP_REQUESTED)
602 IWL_ERR(trans,
603 "TOP reset interrupted by error (state %d)!\n",
604 trans_pcie->fw_reset_state);
605 else
606 IWL_ERR(trans, "TOP reset timed out!\n");
607 iwl_op_mode_nic_error(trans->op_mode,
608 IWL_ERR_TYPE_TOP_RESET_FAILED);
609 iwl_trans_schedule_reset(trans,
610 IWL_ERR_TYPE_TOP_RESET_FAILED);
611 ret = -EIO;
612 goto out;
613 }
614
615 msleep(10);
616 IWL_INFO(trans, "TOP reset successful, reinit now\n");
617 /* now load the firmware again properly */
618 ret = _iwl_trans_pcie_start_hw(trans);
619 if (ret) {
620 IWL_ERR(trans, "failed to start HW after TOP reset\n");
621 goto out;
622 }
623 trans_pcie->prph_scratch->ctrl_cfg.control.control_flags &=
624 ~cpu_to_le32(IWL_PRPH_SCRATCH_TOP_RESET);
625 top_reset_done = true;
626 goto again;
627 }
628
629 /* re-check RF-Kill state since we may have missed the interrupt */
630 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
631 if (hw_rfkill && !run_in_rfkill)
632 ret = -ERFKILL;
633
634 out:
635 mutex_unlock(&trans_pcie->mutex);
636 return ret;
637 }
638
iwl_trans_pcie_gen2_op_mode_leave(struct iwl_trans * trans)639 void iwl_trans_pcie_gen2_op_mode_leave(struct iwl_trans *trans)
640 {
641 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
642
643 mutex_lock(&trans_pcie->mutex);
644
645 /* disable interrupts - don't enable HW RF kill interrupt */
646 iwl_disable_interrupts(trans);
647
648 iwl_pcie_gen2_apm_stop(trans, true);
649
650 iwl_disable_interrupts(trans);
651
652 iwl_pcie_disable_ict(trans);
653
654 mutex_unlock(&trans_pcie->mutex);
655
656 iwl_pcie_synchronize_irqs(trans);
657 }
658