1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2024 Arm Ltd 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef _ARM64_ARM_SPE_H_ 29 #define _ARM64_ARM_SPE_H_ 30 31 /* kqueue events */ 32 #define ARM_SPE_KQ_BUF 138 33 #define ARM_SPE_KQ_SHUTDOWN 139 34 #define ARM_SPE_KQ_SIGNAL 140 35 36 /* spe_backend_read() u64 data encoding */ 37 #define KQ_BUF_POS_SHIFT 0 38 #define KQ_BUF_POS (1 << KQ_BUF_POS_SHIFT) 39 #define KQ_PARTREC_SHIFT 1 40 #define KQ_PARTREC (1 << KQ_PARTREC_SHIFT) 41 #define KQ_FINAL_BUF_SHIFT 2 42 #define KQ_FINAL_BUF (1 << KQ_FINAL_BUF_SHIFT) 43 44 enum arm_spe_ctx_field { 45 ARM_SPE_CTX_NONE, 46 ARM_SPE_CTX_PID, 47 ARM_SPE_CTX_CPU_ID 48 }; 49 50 enum arm_spe_profiling_level { 51 ARM_SPE_KERNEL_AND_USER, 52 ARM_SPE_KERNEL_ONLY, 53 ARM_SPE_USER_ONLY 54 }; 55 struct arm_spe_config { 56 /* Minimum interval is IMP DEF up to maximum 24 bit value */ 57 uint32_t interval; 58 59 /* Profile kernel (EL1), userspace (EL0) or both */ 60 enum arm_spe_profiling_level level; 61 62 /* 63 * Configure context field in SPE records to store either the 64 * current PID, the CPU ID or neither 65 * 66 * In PID mode, kernel threads without a process context are 67 * logged as PID 0 68 */ 69 enum arm_spe_ctx_field ctx_field; 70 }; 71 72 struct arm_spe_svc_buf { 73 uint32_t ident; 74 uint8_t buf_idx : 1; 75 }; 76 77 #endif /* _ARM64_ARM_SPE_H_ */ 78