1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com> 5 * 6 * This software was developed by SRI International and the University of 7 * Cambridge Computer Laboratory (Department of Computer Science and 8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the 9 * DARPA SSITH research programme. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 /* 34 * Intel Stratix 10 FPGA Manager. 35 */ 36 37 #include <sys/cdefs.h> 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/kernel.h> 42 #include <sys/module.h> 43 #include <sys/malloc.h> 44 #include <sys/rman.h> 45 #include <sys/timeet.h> 46 #include <sys/timetc.h> 47 #include <sys/conf.h> 48 #include <sys/uio.h> 49 #include <sys/sx.h> 50 51 #include <dev/ofw/openfirm.h> 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #include <arm64/intel/stratix10-svc.h> 56 57 #include <machine/bus.h> 58 #include <machine/cpu.h> 59 #include <machine/intr.h> 60 61 #define SVC_BUF_SIZE (2 * 1024 * 1024) 62 63 struct fpgamgr_s10_softc { 64 struct cdev *mgr_cdev; 65 struct cdev *mgr_cdev_partial; 66 device_t dev; 67 device_t s10_svc_dev; 68 struct s10_svc_mem mem; 69 struct sx sx; 70 int opened; 71 }; 72 73 static int 74 fpga_open(struct cdev *dev, int flags __unused, 75 int fmt __unused, struct thread *td __unused) 76 { 77 struct fpgamgr_s10_softc *sc; 78 struct s10_svc_msg msg; 79 int ret; 80 int err; 81 82 sc = dev->si_drv1; 83 84 sx_xlock(&sc->sx); 85 if (sc->opened) { 86 sx_xunlock(&sc->sx); 87 return (EBUSY); 88 } 89 90 err = s10_svc_allocate_memory(sc->s10_svc_dev, 91 &sc->mem, SVC_BUF_SIZE); 92 if (err != 0) { 93 sx_xunlock(&sc->sx); 94 return (ENXIO); 95 } 96 97 bzero(&msg, sizeof(struct s10_svc_msg)); 98 msg.command = COMMAND_RECONFIG; 99 if (dev == sc->mgr_cdev_partial) 100 msg.flags |= COMMAND_RECONFIG_FLAG_PARTIAL; 101 ret = s10_svc_send(sc->s10_svc_dev, &msg); 102 if (ret != 0) { 103 sx_xunlock(&sc->sx); 104 return (ENXIO); 105 } 106 107 sc->opened = 1; 108 sx_xunlock(&sc->sx); 109 110 return (0); 111 } 112 113 static int 114 fpga_write(struct cdev *dev, struct uio *uio, int ioflag) 115 { 116 struct fpgamgr_s10_softc *sc; 117 vm_offset_t addr; 118 int amnt; 119 120 sc = dev->si_drv1; 121 122 sx_xlock(&sc->sx); 123 if (sc->opened == 0) { 124 /* Device closed. */ 125 sx_xunlock(&sc->sx); 126 return (ENXIO); 127 } 128 129 while (uio->uio_resid > 0) { 130 addr = sc->mem.vaddr + sc->mem.fill; 131 if (sc->mem.fill >= SVC_BUF_SIZE) 132 return (ENOMEM); 133 amnt = MIN(uio->uio_resid, (SVC_BUF_SIZE - sc->mem.fill)); 134 uiomove((void *)addr, amnt, uio); 135 sc->mem.fill += amnt; 136 } 137 138 sx_xunlock(&sc->sx); 139 140 return (0); 141 } 142 143 static int 144 fpga_close(struct cdev *dev, int flags __unused, 145 int fmt __unused, struct thread *td __unused) 146 { 147 struct fpgamgr_s10_softc *sc; 148 struct s10_svc_msg msg; 149 int ret; 150 151 sc = dev->si_drv1; 152 153 sx_xlock(&sc->sx); 154 if (sc->opened == 0) { 155 /* Device closed. */ 156 sx_xunlock(&sc->sx); 157 return (ENXIO); 158 } 159 160 /* Submit bitstream */ 161 bzero(&msg, sizeof(struct s10_svc_msg)); 162 msg.command = COMMAND_RECONFIG_DATA_SUBMIT; 163 msg.payload = (void *)sc->mem.paddr; 164 msg.payload_length = sc->mem.fill; 165 ret = s10_svc_send(sc->s10_svc_dev, &msg); 166 if (ret != 0) { 167 device_printf(sc->dev, "Failed to submit data\n"); 168 s10_svc_free_memory(sc->s10_svc_dev, &sc->mem); 169 sc->opened = 0; 170 sx_xunlock(&sc->sx); 171 return (0); 172 } 173 174 /* Claim memory buffer back */ 175 bzero(&msg, sizeof(struct s10_svc_msg)); 176 msg.command = COMMAND_RECONFIG_DATA_CLAIM; 177 s10_svc_send(sc->s10_svc_dev, &msg); 178 179 s10_svc_free_memory(sc->s10_svc_dev, &sc->mem); 180 sc->opened = 0; 181 sx_xunlock(&sc->sx); 182 183 return (0); 184 } 185 186 static int 187 fpga_ioctl(struct cdev *dev, u_long cmd, caddr_t addr, int flags, 188 struct thread *td) 189 { 190 191 return (0); 192 } 193 194 static struct cdevsw fpga_cdevsw = { 195 .d_version = D_VERSION, 196 .d_open = fpga_open, 197 .d_close = fpga_close, 198 .d_write = fpga_write, 199 .d_ioctl = fpga_ioctl, 200 .d_name = "FPGA Manager", 201 }; 202 203 static int 204 fpgamgr_s10_probe(device_t dev) 205 { 206 207 if (!ofw_bus_status_okay(dev)) 208 return (ENXIO); 209 210 if (!ofw_bus_is_compatible(dev, "intel,stratix10-soc-fpga-mgr")) 211 return (ENXIO); 212 213 device_set_desc(dev, "Stratix 10 SOC FPGA Manager"); 214 215 return (BUS_PROBE_DEFAULT); 216 } 217 218 static int 219 fpgamgr_s10_attach(device_t dev) 220 { 221 struct fpgamgr_s10_softc *sc; 222 devclass_t dc; 223 224 sc = device_get_softc(dev); 225 sc->dev = dev; 226 227 dc = devclass_find("s10_svc"); 228 if (dc == NULL) 229 return (ENXIO); 230 231 sc->s10_svc_dev = devclass_get_device(dc, 0); 232 if (sc->s10_svc_dev == NULL) 233 return (ENXIO); 234 235 sc->mgr_cdev = make_dev(&fpga_cdevsw, 0, UID_ROOT, GID_WHEEL, 236 0600, "fpga%d", device_get_unit(sc->dev)); 237 if (sc->mgr_cdev == NULL) { 238 device_printf(dev, "Failed to create character device.\n"); 239 return (ENXIO); 240 } 241 242 sc->mgr_cdev_partial = make_dev(&fpga_cdevsw, 0, UID_ROOT, GID_WHEEL, 243 0600, "fpga_partial%d", device_get_unit(sc->dev)); 244 if (sc->mgr_cdev_partial == NULL) { 245 device_printf(dev, "Failed to create character device.\n"); 246 return (ENXIO); 247 } 248 249 sx_init(&sc->sx, "s10 fpga"); 250 251 sc->mgr_cdev->si_drv1 = sc; 252 sc->mgr_cdev_partial->si_drv1 = sc; 253 254 return (0); 255 } 256 257 static int 258 fpgamgr_s10_detach(device_t dev) 259 { 260 struct fpgamgr_s10_softc *sc; 261 262 sc = device_get_softc(dev); 263 264 destroy_dev(sc->mgr_cdev); 265 destroy_dev(sc->mgr_cdev_partial); 266 267 sx_destroy(&sc->sx); 268 269 return (0); 270 } 271 272 static device_method_t fpgamgr_s10_methods[] = { 273 DEVMETHOD(device_probe, fpgamgr_s10_probe), 274 DEVMETHOD(device_attach, fpgamgr_s10_attach), 275 DEVMETHOD(device_detach, fpgamgr_s10_detach), 276 { 0, 0 } 277 }; 278 279 static driver_t fpgamgr_s10_driver = { 280 "fpgamgr_s10", 281 fpgamgr_s10_methods, 282 sizeof(struct fpgamgr_s10_softc), 283 }; 284 285 DRIVER_MODULE(fpgamgr_s10, simplebus, fpgamgr_s10_driver, 0, 0); 286