1 /*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2021 The FreeBSD Foundation 4 * 5 * Portions of this software were developed by Andrew Turner 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _MACHINE_HYPERVISOR_H_ 33 #define _MACHINE_HYPERVISOR_H_ 34 35 /* 36 * These registers are only useful when in hypervisor context, 37 * e.g. specific to EL2, or controlling the hypervisor. 38 */ 39 40 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */ 41 #define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ 42 #define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ 43 #define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ 44 #define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */ 45 #define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/ 46 47 /* CPTR_EL2 - Architecture feature trap register */ 48 #define CPTR_RES0 0x7fefc800 49 #define CPTR_RES1 0x000033ff 50 #define CPTR_TFP 0x00000400 51 #define CPTR_TTA 0x00100000 52 #define CPTR_TCPAC 0x80000000 53 54 /* HCR_EL2 - Hypervisor Config Register */ 55 #define HCR_VM (UL(0x1) << 0) 56 #define HCR_SWIO (UL(0x1) << 1) 57 #define HCR_PTW (UL(0x1) << 2) 58 #define HCR_FMO (UL(0x1) << 3) 59 #define HCR_IMO (UL(0x1) << 4) 60 #define HCR_AMO (UL(0x1) << 5) 61 #define HCR_VF (UL(0x1) << 6) 62 #define HCR_VI (UL(0x1) << 7) 63 #define HCR_VSE (UL(0x1) << 8) 64 #define HCR_FB (UL(0x1) << 9) 65 #define HCR_BSU_MASK (UL(0x3) << 10) 66 #define HCR_BSU_IS (UL(0x1) << 10) 67 #define HCR_BSU_OS (UL(0x2) << 10) 68 #define HCR_BSU_FS (UL(0x3) << 10) 69 #define HCR_DC (UL(0x1) << 12) 70 #define HCR_TWI (UL(0x1) << 13) 71 #define HCR_TWE (UL(0x1) << 14) 72 #define HCR_TID0 (UL(0x1) << 15) 73 #define HCR_TID1 (UL(0x1) << 16) 74 #define HCR_TID2 (UL(0x1) << 17) 75 #define HCR_TID3 (UL(0x1) << 18) 76 #define HCR_TSC (UL(0x1) << 19) 77 #define HCR_TIDCP (UL(0x1) << 20) 78 #define HCR_TACR (UL(0x1) << 21) 79 #define HCR_TSW (UL(0x1) << 22) 80 #define HCR_TPCP (UL(0x1) << 23) 81 #define HCR_TPU (UL(0x1) << 24) 82 #define HCR_TTLB (UL(0x1) << 25) 83 #define HCR_TVM (UL(0x1) << 26) 84 #define HCR_TGE (UL(0x1) << 27) 85 #define HCR_TDZ (UL(0x1) << 28) 86 #define HCR_HCD (UL(0x1) << 29) 87 #define HCR_TRVM (UL(0x1) << 30) 88 #define HCR_RW (UL(0x1) << 31) 89 #define HCR_CD (UL(0x1) << 32) 90 #define HCR_ID (UL(0x1) << 33) 91 #define HCR_E2H (UL(0x1) << 34) 92 #define HCR_TLOR (UL(0x1) << 35) 93 #define HCR_TERR (UL(0x1) << 36) 94 #define HCR_TEA (UL(0x1) << 37) 95 #define HCR_MIOCNCE (UL(0x1) << 38) 96 /* Bit 39 is reserved */ 97 #define HCR_APK (UL(0x1) << 40) 98 #define HCR_API (UL(0x1) << 41) 99 #define HCR_NV (UL(0x1) << 42) 100 #define HCR_NV1 (UL(0x1) << 43) 101 #define HCR_AT (UL(0x1) << 44) 102 #define HCR_NV2 (UL(0x1) << 45) 103 #define HCR_FWB (UL(0x1) << 46) 104 #define HCR_FIEN (UL(0x1) << 47) 105 /* Bit 48 is reserved */ 106 #define HCR_TID4 (UL(0x1) << 49) 107 #define HCR_TICAB (UL(0x1) << 50) 108 #define HCR_AMVOFFEN (UL(0x1) << 51) 109 #define HCR_TOCU (UL(0x1) << 52) 110 #define HCR_EnSCXT (UL(0x1) << 53) 111 #define HCR_TTLBIS (UL(0x1) << 54) 112 #define HCR_TTLBOS (UL(0x1) << 55) 113 #define HCR_ATA (UL(0x1) << 56) 114 #define HCR_DCT (UL(0x1) << 57) 115 #define HCR_TID5 (UL(0x1) << 58) 116 #define HCR_TWEDEn (UL(0x1) << 59) 117 #define HCR_TWEDEL_MASK (UL(0xf) << 60) 118 119 /* HPFAR_EL2 - Hypervisor IPA Fault Address Register */ 120 #define HPFAR_EL2_FIPA_SHIFT 4 121 #define HPFAR_EL2_FIPA_MASK 0xfffffffff0 122 123 /* ICC_SRE_EL2 */ 124 #define ICC_SRE_EL2_SRE (1U << 0) 125 #define ICC_SRE_EL2_EN (1U << 3) 126 127 /* SCTLR_EL2 - System Control Register */ 128 #define SCTLR_EL2_RES1 0x30c50830 129 #define SCTLR_EL2_M_SHIFT 0 130 #define SCTLR_EL2_M (0x1 << SCTLR_EL2_M_SHIFT) 131 #define SCTLR_EL2_A_SHIFT 1 132 #define SCTLR_EL2_A (0x1 << SCTLR_EL2_A_SHIFT) 133 #define SCTLR_EL2_C_SHIFT 2 134 #define SCTLR_EL2_C (0x1 << SCTLR_EL2_C_SHIFT) 135 #define SCTLR_EL2_SA_SHIFT 3 136 #define SCTLR_EL2_SA (0x1 << SCTLR_EL2_SA_SHIFT) 137 #define SCTLR_EL2_I_SHIFT 12 138 #define SCTLR_EL2_I (0x1 << SCTLR_EL2_I_SHIFT) 139 #define SCTLR_EL2_WXN_SHIFT 19 140 #define SCTLR_EL2_WXN (0x1 << SCTLR_EL2_WXN_SHIFT) 141 #define SCTLR_EL2_EE_SHIFT 25 142 #define SCTLR_EL2_EE (0x1 << SCTLR_EL2_EE_SHIFT) 143 144 /* TCR_EL2 - Translation Control Register */ 145 #define TCR_EL2_RES1 ((0x1UL << 31) | (0x1UL << 23)) 146 #define TCR_EL2_T0SZ_SHIFT 0 147 #define TCR_EL2_T0SZ_MASK (0x3f << TCR_EL2_T0SZ_SHIFT) 148 #define TCR_EL2_T0SZ(x) ((x) << TCR_EL2_T0SZ_SHIFT) 149 /* Bits 7:6 are reserved */ 150 #define TCR_EL2_IRGN0_SHIFT 8 151 #define TCR_EL2_IRGN0_MASK (0x3 << TCR_EL2_IRGN0_SHIFT) 152 #define TCR_EL2_ORGN0_SHIFT 10 153 #define TCR_EL2_ORGN0_MASK (0x3 << TCR_EL2_ORGN0_SHIFT) 154 #define TCR_EL2_SH0_SHIFT 12 155 #define TCR_EL2_SH0_MASK (0x3 << TCR_EL2_SH0_SHIFT) 156 #define TCR_EL2_TG0_SHIFT 14 157 #define TCR_EL2_TG0_MASK (0x3 << TCR_EL2_TG0_SHIFT) 158 #define TCR_EL2_PS_SHIFT 16 159 #define TCR_EL2_PS_32BITS (0 << TCR_EL2_PS_SHIFT) 160 #define TCR_EL2_PS_36BITS (1 << TCR_EL2_PS_SHIFT) 161 #define TCR_EL2_PS_40BITS (2 << TCR_EL2_PS_SHIFT) 162 #define TCR_EL2_PS_42BITS (3 << TCR_EL2_PS_SHIFT) 163 #define TCR_EL2_PS_44BITS (4 << TCR_EL2_PS_SHIFT) 164 #define TCR_EL2_PS_48BITS (5 << TCR_EL2_PS_SHIFT) 165 #define TCR_EL2_PS_52BITS (6 << TCR_EL2_PS_SHIFT) /* ARMv8.2-LPA */ 166 167 /* VMPDIR_EL2 - Virtualization Multiprocessor ID Register */ 168 #define VMPIDR_EL2_U 0x0000000040000000 169 #define VMPIDR_EL2_MT 0x0000000001000000 170 #define VMPIDR_EL2_RES1 0x0000000080000000 171 172 /* VTCR_EL2 - Virtualization Translation Control Register */ 173 #define VTCR_EL2_RES1 (0x1 << 31) 174 #define VTCR_EL2_T0SZ_MASK 0x3f 175 #define VTCR_EL2_SL0_SHIFT 6 176 #define VTCR_EL2_SL0_4K_LVL2 (0x0 << VTCR_EL2_SL0_SHIFT) 177 #define VTCR_EL2_SL0_4K_LVL1 (0x1 << VTCR_EL2_SL0_SHIFT) 178 #define VTCR_EL2_SL0_4K_LVL0 (0x2 << VTCR_EL2_SL0_SHIFT) 179 #define VTCR_EL2_IRGN0_SHIFT 8 180 #define VTCR_EL2_IRGN0_WBWA (0x1 << VTCR_EL2_IRGN0_SHIFT) 181 #define VTCR_EL2_ORGN0_SHIFT 10 182 #define VTCR_EL2_ORGN0_WBWA (0x1 << VTCR_EL2_ORGN0_SHIFT) 183 #define VTCR_EL2_SH0_SHIFT 12 184 #define VTCR_EL2_SH0_NS (0x0 << VTCR_EL2_SH0_SHIFT) 185 #define VTCR_EL2_SH0_OS (0x2 << VTCR_EL2_SH0_SHIFT) 186 #define VTCR_EL2_SH0_IS (0x3 << VTCR_EL2_SH0_SHIFT) 187 #define VTCR_EL2_TG0_SHIFT 14 188 #define VTCR_EL2_TG0_4K (0x0 << VTCR_EL2_TG0_SHIFT) 189 #define VTCR_EL2_TG0_64K (0x1 << VTCR_EL2_TG0_SHIFT) 190 #define VTCR_EL2_TG0_16K (0x2 << VTCR_EL2_TG0_SHIFT) 191 #define VTCR_EL2_PS_SHIFT 16 192 #define VTCR_EL2_PS_32BIT (0x0 << VTCR_EL2_PS_SHIFT) 193 #define VTCR_EL2_PS_36BIT (0x1 << VTCR_EL2_PS_SHIFT) 194 #define VTCR_EL2_PS_40BIT (0x2 << VTCR_EL2_PS_SHIFT) 195 #define VTCR_EL2_PS_42BIT (0x3 << VTCR_EL2_PS_SHIFT) 196 #define VTCR_EL2_PS_44BIT (0x4 << VTCR_EL2_PS_SHIFT) 197 #define VTCR_EL2_PS_48BIT (0x5 << VTCR_EL2_PS_SHIFT) 198 199 /* VTTBR_EL2 - Virtualization Translation Table Base Register */ 200 #define VTTBR_VMID_MASK 0xffff000000000000 201 #define VTTBR_VMID_SHIFT 48 202 #define VTTBR_HOST 0x0000000000000000 203 204 #endif /* !_MACHINE_HYPERVISOR_H_ */ 205