arm64: Support mapping a 52-bit physical adddress

When FEAT_LPA2 is enabled the physical address space increases from
48-bits to 52-bits. The top two address bits are moved to the now
unused shareab

arm64: Support mapping a 52-bit physical adddress

When FEAT_LPA2 is enabled the physical address space increases from
48-bits to 52-bits. The top two address bits are moved to the now
unused shareability field.

Update the kernel to support this new larger address space.

Reviewed by: alc, kib
Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D46624

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arm64: add HCRX_EL2 register

HCRX_EL2 is the Extended Hypervisor Configuration Register introduced
with FEAT_HCX in ARMv8.7. All fields in this register are used for
features in ARMv8.7 and above. I

arm64: add HCRX_EL2 register

HCRX_EL2 is the Extended Hypervisor Configuration Register introduced
with FEAT_HCX in ARMv8.7. All fields in this register are used for
features in ARMv8.7 and above. Initially zero the register, incase
firmware has not properly configured it.

Reviewed by: andrew
Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D48583
Signed-off-by: Harry Moulton <harry.moulton@arm.com>

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arm64: Add a constant to document the TZ bit in CPTR_EL2 without VHE

Reviewed by: emaste
Sponsored by: AFRL, DARPA
Differential Revision: https://reviews.freebsd.org/D47882

arm64: Don't trap SVE to EL2

As with floating point instructions don't trap SVE instructions to the
hypervisor. This lets us handle then in the kernel.

Reviewed by: imp (earlier version)
Sponsored

arm64: Don't trap SVE to EL2

As with floating point instructions don't trap SVE instructions to the
hypervisor. This lets us handle then in the kernel.

Reviewed by: imp (earlier version)
Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D43303

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arm64: Add CPTR_TRAP_ALL and use it in vmm

Add a new macro that enables all CPTR_EL2 traps. This helps ensure we
trap all extensions we don't support.

Sponsored by: Arm Ltd
Differential Revision: h

arm64: Add CPTR_TRAP_ALL and use it in vmm

Add a new macro that enables all CPTR_EL2 traps. This helps ensure we
trap all extensions we don't support.

Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D46516

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arm64: Add CPTR_E2H_TTA

The TTA field moves depending on the HCR_EL2.E2H field. Add a macro to
hold the E2H == 1 case.

Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D46515

arm64: Add E2H to CPTR_EL2 register values

Rename register fields that are only valid when HCR_EL2.E2H == 1. Some
fields move around depending on the value of the E2H field.

Sponsored by: Arm Ltd
D

arm64: Add E2H to CPTR_EL2 register values

Rename register fields that are only valid when HCR_EL2.E2H == 1. Some
fields move around depending on the value of the E2H field.

Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D46514

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arm64: Adjust the indentation of CPTR_EL2 values

Reviewed by: emaste
Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D46513

arm64: add additional MDCR_EL2 fields

Monitor Debug Configuration Register provides EL2 configuration options
for self-hosted debug and the Performance Monitors Extension.

Reviewed by: andrew
Spons

arm64: add additional MDCR_EL2 fields

Monitor Debug Configuration Register provides EL2 configuration options
for self-hosted debug and the Performance Monitors Extension.

Reviewed by: andrew
Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D46191

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arm64: Make shareability attributes dynamic

When LPA2 is enabled the shareability attribute in the page table are
replaces with output address bits. To support a larger physical address
space make t

arm64: Make shareability attributes dynamic

When LPA2 is enabled the shareability attribute in the page table are
replaces with output address bits. To support a larger physical address
space make this attribute dynamic so we only set it when appropriate.

Reviewed by: alc, kib
Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D46394

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arm64/vmm: Teach the vtimer about VHE

Teach the virtual timer about the cnthctl_el2 field layout under VHE.
As with non-VHE we need to trap the physical timer and not trap the
virtual timer.

Sponso

arm64/vmm: Teach the vtimer about VHE

Teach the virtual timer about the cnthctl_el2 field layout under VHE.
As with non-VHE we need to trap the physical timer and not trap the
virtual timer.

Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D46074

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arm64: Ensure sctlr and pstate are in known states

Before entering the kernel exception level ensure sctlr_el2 and
sctlr_el1 are in a known state. The EOS flag needs to be set to ensure
an eret inst

arm64: Ensure sctlr and pstate are in known states

Before entering the kernel exception level ensure sctlr_el2 and
sctlr_el1 are in a known state. The EOS flag needs to be set to ensure
an eret instruction is a context synchronization event.

Set spcr_el1 when entering the kernel from EL1 and use an eret
instruction to return to the caller. This ensures the CPU pstate is
consistent with the value in spcr_el1 as it is the only way to set it
directly.

Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D45528

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arm64: Support counter access with E2H

When entering the kernel with the E2H field set the layout of the
cnthctl_el2 register changes. Use the correct field locations to enable
access to the counter

arm64: Support counter access with E2H

When entering the kernel with the E2H field set the layout of the
cnthctl_el2 register changes. Use the correct field locations to enable
access to the counter and timer registers from EL1.

Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D45529

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arm64: Add a macro to find a VM fault address

Add a macro to find which bits from far_el2 are needed to be copied
to get the full intermediate physical address (IPA).

The hpfar_el2 register only co

arm64: Add a macro to find a VM fault address

Add a macro to find which bits from far_el2 are needed to be copied
to get the full intermediate physical address (IPA).

The hpfar_el2 register only contains a 4k aligned fault address. We
need to include the lower bits from far_el2 if we need the full
faulting IPA.

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arm64: Add the TCR_EL2.PS mask

arm64: Add register definitions for MDCR_EL2

This is needed to support the bhyve gdb stub implementation on arm64.

Reviewed by: andrew
MFC after: 1 week
Sponsored by: Innovate UK
Differential Revis

arm64: Add register definitions for MDCR_EL2

This is needed to support the bhyve gdb stub implementation on arm64.

Reviewed by: andrew
MFC after: 1 week
Sponsored by: Innovate UK
Differential Revision: https://reviews.freebsd.org/D42867

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sys: Remove $FreeBSD$: two-line .h pattern

Remove /^\s*\*\n \*\s+\$FreeBSD\$$\n/

arm64: set FPEN if we're stuck with HCR_EL2.E2H

On Apple Silicon systems, E2H can't actually be cleared; we're stuck
with it. Check it again when we're setting up CPTR_EL2 and set FPEN
appropriatel

arm64: set FPEN if we're stuck with HCR_EL2.E2H

On Apple Silicon systems, E2H can't actually be cleared; we're stuck
with it. Check it again when we're setting up CPTR_EL2 and set FPEN
appropriately to avoid later trapping to EL2 on writes to SIMD
registers.

Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D38819

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Add more arm64 hypervisor registers

These will be used by bhyve.

Sponsored by: Innovate UK
Sponsored by: The FreeBSD Foundation

Put the arm64 vttbr_el2 register into a state

Zero the vttbr_el2 register on each CPU so we can tell if we are
running the host or guest kernel from a hypervisor.

Obtained from: https://github.com/

Put the arm64 vttbr_el2 register into a state

Zero the vttbr_el2 register on each CPU so we can tell if we are
running the host or guest kernel from a hypervisor.

Obtained from: https://github.com/FreeBSD-UPB/freebsd-src (earlier version)
Sponsored by: Innovate UK
Sponsored by: The FreeBSD Foundation

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Mark 64-bit arm64 hypervisor registers with UL

These are 64-bit. Mark them as unsigned long so we don't rely on
undefined behaviour or shift a 32-bit value more than 32 bits.

Sponsored by: Innovate

Mark 64-bit arm64 hypervisor registers with UL

These are 64-bit. Mark them as unsigned long so we don't rely on
undefined behaviour or shift a 32-bit value more than 32 bits.

Sponsored by: Innovate UK
Sponsored by: The FreeBSD Foundation

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Update the arm64 HCR_EL2 registers

They are valid as of the ARMv8.7 XML.

While here switch to use shifted values as they are easier to compare
with values in the Arm Reference Manual.

Sponsored by

Update the arm64 HCR_EL2 registers

They are valid as of the ARMv8.7 XML.

While here switch to use shifted values as they are easier to compare
with values in the Arm Reference Manual.

Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D31093

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Merge ^/head r358678 through r358711.

Update the hypervisor registers

- Add more registers needed by bhyve [1]
- Move EL2 registers from armreg.h to hypervisor.h
- Add the register name to hypervisor.h

Obtained from: https://github.

Update the hypervisor registers

- Add more registers needed by bhyve [1]
- Move EL2 registers from armreg.h to hypervisor.h
- Add the register name to hypervisor.h

Obtained from: https://github.com/FreeBSD-UPB/freebsd [1]

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Merge ^/head r339813 through r340125.