1 /*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2021 The FreeBSD Foundation 4 * 5 * Portions of this software were developed by Andrew Turner 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef _MACHINE_HYPERVISOR_H_ 31 #define _MACHINE_HYPERVISOR_H_ 32 33 #include <machine/_armreg.h> 34 35 /* 36 * These registers are only useful when in hypervisor context, 37 * e.g. specific to EL2, or controlling the hypervisor. 38 */ 39 40 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */ 41 /* Valid if HCR_EL2.E2H == 0 */ 42 #define CNTHCTL_EL1PCTEN_SHIFT 0 43 #define CNTHCTL_EL1PCTEN_MASK (0x1ul << CNTHCTL_E2H_EL1PCTEN_SHIFT) 44 #define CNTHCTL_EL1PCTEN_TRAP (0x0ul << CNTHCTL_E2H_EL1PCTEN_SHIFT) 45 #define CNTHCTL_EL1PCTEN_NOTRAP (0x1ul << CNTHCTL_EL1PCTEN_SHIFT) 46 #define CNTHCTL_EL1PCEN_SHIFT 1 47 #define CNTHCTL_EL1PCEN_MASK (0x1ul << CNTHCTL_EL1PCEN_SHIFT) 48 #define CNTHCTL_EL1PCEN_TRAP (0x0ul << CNTHCTL_EL1PCEN_SHIFT) 49 #define CNTHCTL_EL1PCEN_NOTRAP (0x1ul << CNTHCTL_EL1PCEN_SHIFT) 50 /* Valid if HCR_EL2.E2H == 1 */ 51 #define CNTHCTL_E2H_EL0PCTEN_SHIFT 0 52 #define CNTHCTL_E2H_EL0PCTEN_MASK (0x1ul << CNTHCTL_E2H_EL0PCTEN_SHIFT) 53 #define CNTHCTL_E2H_EL0PCTEN_TRAP (0x0ul << CNTHCTL_E2H_EL0PCTEN_SHIFT) 54 #define CNTHCTL_E2H_EL0PCTEN_NOTRAP (0x1ul << CNTHCTL_E2H_EL0PCTEN_SHIFT) 55 #define CNTHCTL_E2H_EL0VCTEN_SHIFT 1 56 #define CNTHCTL_E2H_EL0VCTEN_MASK (0x1ul << CNTHCTL_E2H_EL0VCTEN_SHIFT) 57 #define CNTHCTL_E2H_EL0VCTEN_TRAP (0x0ul << CNTHCTL_E2H_EL0VCTEN_SHIFT) 58 #define CNTHCTL_E2H_EL0VCTEN_NOTRAP (0x1ul << CNTHCTL_E2H_EL0VCTEN_SHIFT) 59 #define CNTHCTL_E2H_EL0VTEN_SHIFT 8 60 #define CNTHCTL_E2H_EL0VTEN_MASK (0x1ul << CNTHCTL_E2H_EL0VTEN_SHIFT) 61 #define CNTHCTL_E2H_EL0VTEN_TRAP (0x0ul << CNTHCTL_E2H_EL0VTEN_SHIFT) 62 #define CNTHCTL_E2H_EL0VTEN_NOTRAP (0x1ul << CNTHCTL_E2H_EL0VTEN_SHIFT) 63 #define CNTHCTL_E2H_EL0PTEN_SHIFT 9 64 #define CNTHCTL_E2H_EL0PTEN_MASK (0x1ul << CNTHCTL_E2H_EL0PTEN_SHIFT) 65 #define CNTHCTL_E2H_EL0PTEN_TRAP (0x0ul << CNTHCTL_E2H_EL0PTEN_SHIFT) 66 #define CNTHCTL_E2H_EL0PTEN_NOTRAP (0x1ul << CNTHCTL_E2H_EL0PTEN_SHIFT) 67 #define CNTHCTL_E2H_EL1PCTEN_SHIFT 10 68 #define CNTHCTL_E2H_EL1PCTEN_MASK (0x1ul << CNTHCTL_E2H_EL1PCTEN_SHIFT) 69 #define CNTHCTL_E2H_EL1PCTEN_TRAP (0x0ul << CNTHCTL_E2H_EL1PCTEN_SHIFT) 70 #define CNTHCTL_E2H_EL1PCTEN_NOTRAP (0x1ul << CNTHCTL_E2H_EL1PCTEN_SHIFT) 71 #define CNTHCTL_E2H_EL1PTEN_SHIFT 11 72 #define CNTHCTL_E2H_EL1PTEN_MASK (0x1ul << CNTHCTL_E2H_EL1PTEN_SHIFT) 73 #define CNTHCTL_E2H_EL1PTEN_TRAP (0x0ul << CNTHCTL_E2H_EL1PTEN_SHIFT) 74 #define CNTHCTL_E2H_EL1PTEN_NOTRAP (0x1ul << CNTHCTL_E2H_EL1PTEN_SHIFT) 75 /* Unconditionally valid */ 76 #define CNTHCTL_EVNTEN_SHIFT 2 77 #define CNTHCTL_EVNTEN_MASK (0x1ul << CNTHCTL_EVNTEN_SHIFT) 78 #define CNTHCTL_EVNTEN_DIS (0x0ul << CNTHCTL_EVNTEN_SHIFT) 79 #define CNTHCTL_EVNTEN_EN (0x1ul << CNTHCTL_EVNTEN_SHIFT) 80 #define CNTHCTL_EVNTDIR_SHIFT 3 81 #define CNTHCTL_EVNTDIR_MASK (0x1ul << CNTHCTL_EVNTDIR_SHIFT) 82 #define CNTHCTL_EVNTDIR_HIGH (0x0ul << CNTHCTL_EVNTDIR_SHIFT) 83 #define CNTHCTL_EVNTDIR_LOW (0x1ul << CNTHCTL_EVNTDIR_SHIFT) 84 #define CNTHCTL_EVNTI_SHIFT 4 85 #define CNTHCTL_EVNTI_MASK (0xful << CNTHCTL_EVNTI_SHIFT) 86 #define CNTHCTL_ECV_SHIFT 12 87 #define CNTHCTL_ECV_MASK (0x1ul << CNTHCTL_ECV_SHIFT) 88 #define CNTHCTL_ECV_DIS (0x0ul << CNTHCTL_ECV_SHIFT) 89 #define CNTHCTL_ECV_EN (0x1ul << CNTHCTL_ECV_SHIFT) 90 #define CNTHCTL_EL1TVT_SHIFT 13 91 #define CNTHCTL_EL1TVT_MASK (0x1ul << CNTHCTL_EL1TVT_SHIFT) 92 #define CNTHCTL_EL1TVT_NOTRAP (0x0ul << CNTHCTL_EL1TVT_SHIFT) 93 #define CNTHCTL_EL1TVT_TRAP (0x1ul << CNTHCTL_EL1TVT_SHIFT) 94 #define CNTHCTL_EL1TVCT_SHIFT 14 95 #define CNTHCTL_EL1TVCT_MASK (0x1ul << CNTHCTL_EL1TVCT_SHIFT) 96 #define CNTHCTL_EL1TVCT_NOTRAP (0x0ul << CNTHCTL_EL1TVCT_SHIFT) 97 #define CNTHCTL_EL1TVCT_TRAP (0x1ul << CNTHCTL_EL1TVCT_SHIFT) 98 #define CNTHCTL_EL1NVPCT_SHIFT 15 99 #define CNTHCTL_EL1NVPCT_MASK (0x1ul << CNTHCTL_EL1NVPCT_SHIFT) 100 #define CNTHCTL_EL1NVPCT_NOTRAP (0x0ul << CNTHCTL_EL1NVPCT_SHIFT) 101 #define CNTHCTL_EL1NVPCT_TRAP (0x1ul << CNTHCTL_EL1NVPCT_SHIFT) 102 #define CNTHCTL_EL1NVVCT_SHIFT 16 103 #define CNTHCTL_EL1NVVCT_MASK (0x1ul << CNTHCTL_EL1NVVCT_SHIFT) 104 #define CNTHCTL_EL1NVVCT_NOTRAP (0x0ul << CNTHCTL_EL1NVVCT_SHIFT) 105 #define CNTHCTL_EL1NVVCT_TRAP (0x1ul << CNTHCTL_EL1NVVCT_SHIFT) 106 #define CNTHCTL_EVNTIS_SHIFT 17 107 #define CNTHCTL_EVNTIS_MASK (0x1ul << CNTHCTL_EVNTIS_SHIFT) 108 #define CNTHCTL_CNTVMASK_SHIFT 18 109 #define CNTHCTL_CNTVMASK_MASK (0x1ul << CNTHCTL_CNTVMASK_SHIFT) 110 #define CNTHCTL_CNTPMASK_SHIFT 19 111 #define CNTHCTL_CNTPMASK_MASK (0x1ul << CNTHCTL_CNTPMASK_SHIFT) 112 113 /* CNTPOFF_EL2 - Counter-timer Physical Offset Register */ 114 #define CNTPOFF_EL2_REG MRS_REG_ALT_NAME(CNTPOFF_EL2) 115 #define CNTPOFF_EL2_op0 3 116 #define CNTPOFF_EL2_op1 4 117 #define CNTPOFF_EL2_CRn 14 118 #define CNTPOFF_EL2_CRm 0 119 #define CNTPOFF_EL2_op2 6 120 121 /* CPTR_EL2 - Architecture feature trap register */ 122 /* Valid if HCR_EL2.E2H == 0 */ 123 #define CPTR_TRAP_ALL 0xc01037ff /* Enable all traps */ 124 #define CPTR_RES0 0x7fefc800 125 #define CPTR_RES1 0x000032ff 126 #define CPTR_TZ 0x00000100 127 #define CPTR_TFP 0x00000400 128 #define CPTR_TTA 0x00100000 129 /* Valid if HCR_EL2.E2H == 1 */ 130 #define CPTR_E2H_TRAP_ALL 0xd0000000 131 #define CPTR_E2H_ZPEN 0x00030000 132 #define CPTR_E2H_FPEN 0x00300000 133 #define CPTR_E2H_TTA 0x10000000 134 /* Unconditionally valid */ 135 #define CPTR_TCPAC 0x80000000 136 137 /* HAFGRTR_EL2 */ 138 #define HAFGRTR_EL2_REG MRS_REG_ALT_NAME(HAFGRTR_EL2) 139 #define HAFGRTR_EL2_op0 3 140 #define HAFGRTR_EL2_op1 4 141 #define HAFGRTR_EL2_CRn 3 142 #define HAFGRTR_EL2_CRm 1 143 #define HAFGRTR_EL2_op2 6 144 #define HAFGRTR_EL2_TRAP_ALL UL(0x0003fffffffe001f) 145 146 /* HCR_EL2 - Hypervisor Config Register */ 147 #define HCR_VM (UL(0x1) << 0) 148 #define HCR_SWIO (UL(0x1) << 1) 149 #define HCR_PTW (UL(0x1) << 2) 150 #define HCR_FMO (UL(0x1) << 3) 151 #define HCR_IMO (UL(0x1) << 4) 152 #define HCR_AMO (UL(0x1) << 5) 153 #define HCR_VF (UL(0x1) << 6) 154 #define HCR_VI (UL(0x1) << 7) 155 #define HCR_VSE (UL(0x1) << 8) 156 #define HCR_FB (UL(0x1) << 9) 157 #define HCR_BSU_MASK (UL(0x3) << 10) 158 #define HCR_BSU_IS (UL(0x1) << 10) 159 #define HCR_BSU_OS (UL(0x2) << 10) 160 #define HCR_BSU_FS (UL(0x3) << 10) 161 #define HCR_DC (UL(0x1) << 12) 162 #define HCR_TWI (UL(0x1) << 13) 163 #define HCR_TWE (UL(0x1) << 14) 164 #define HCR_TID0 (UL(0x1) << 15) 165 #define HCR_TID1 (UL(0x1) << 16) 166 #define HCR_TID2 (UL(0x1) << 17) 167 #define HCR_TID3 (UL(0x1) << 18) 168 #define HCR_TSC (UL(0x1) << 19) 169 #define HCR_TIDCP (UL(0x1) << 20) 170 #define HCR_TACR (UL(0x1) << 21) 171 #define HCR_TSW (UL(0x1) << 22) 172 #define HCR_TPCP (UL(0x1) << 23) 173 #define HCR_TPU (UL(0x1) << 24) 174 #define HCR_TTLB (UL(0x1) << 25) 175 #define HCR_TVM (UL(0x1) << 26) 176 #define HCR_TGE (UL(0x1) << 27) 177 #define HCR_TDZ (UL(0x1) << 28) 178 #define HCR_HCD (UL(0x1) << 29) 179 #define HCR_TRVM (UL(0x1) << 30) 180 #define HCR_RW (UL(0x1) << 31) 181 #define HCR_CD (UL(0x1) << 32) 182 #define HCR_ID (UL(0x1) << 33) 183 #define HCR_E2H (UL(0x1) << 34) 184 #define HCR_TLOR (UL(0x1) << 35) 185 #define HCR_TERR (UL(0x1) << 36) 186 #define HCR_TEA (UL(0x1) << 37) 187 #define HCR_MIOCNCE (UL(0x1) << 38) 188 /* Bit 39 is reserved */ 189 #define HCR_APK (UL(0x1) << 40) 190 #define HCR_API (UL(0x1) << 41) 191 #define HCR_NV (UL(0x1) << 42) 192 #define HCR_NV1 (UL(0x1) << 43) 193 #define HCR_AT (UL(0x1) << 44) 194 #define HCR_NV2 (UL(0x1) << 45) 195 #define HCR_FWB (UL(0x1) << 46) 196 #define HCR_FIEN (UL(0x1) << 47) 197 /* Bit 48 is reserved */ 198 #define HCR_TID4 (UL(0x1) << 49) 199 #define HCR_TICAB (UL(0x1) << 50) 200 #define HCR_AMVOFFEN (UL(0x1) << 51) 201 #define HCR_TOCU (UL(0x1) << 52) 202 #define HCR_EnSCXT (UL(0x1) << 53) 203 #define HCR_TTLBIS (UL(0x1) << 54) 204 #define HCR_TTLBOS (UL(0x1) << 55) 205 #define HCR_ATA (UL(0x1) << 56) 206 #define HCR_DCT (UL(0x1) << 57) 207 #define HCR_TID5 (UL(0x1) << 58) 208 #define HCR_TWEDEn (UL(0x1) << 59) 209 #define HCR_TWEDEL_MASK (UL(0xf) << 60) 210 211 /* HCRX_EL2 - Extended Hypervisor Configuration Register */ 212 #define HCRX_EL2_REG MRS_REG_ALT_NAME(HCRX_EL2) 213 #define HCRX_EL2_op0 3 214 #define HCRX_EL2_op1 4 215 #define HCRX_EL2_CRn 1 216 #define HCRX_EL2_CRm 2 217 #define HCRX_EL2_op2 2 218 219 #define HCRX_EnAS0 (UL(0x1) << 0) 220 #define HCRX_EnALS (UL(0x1) << 1) 221 #define HCRX_EnASR (UL(0x1) << 2) 222 #define HCRX_FnXS (UL(0x1) << 3) 223 #define HCRX_FGTnXS (UL(0x1) << 4) 224 #define HCRX_SMPME (UL(0x1) << 5) 225 #define HCRX_TALLINT (UL(0x1) << 6) 226 #define HCRX_VINMI (UL(0x1) << 7) 227 #define HCRX_VFNMI (UL(0x1) << 8) 228 #define HCRX_CMOW (UL(0x1) << 9) 229 #define HCRX_MCE2 (UL(0x1) << 10) 230 #define HCRX_MSCEn (UL(0x1) << 11) 231 /* Bits 12 & 13 are reserved */ 232 #define HCRX_TCR2En (UL(0x1) << 14) 233 #define HCRX_SCTLR2En (UL(0x1) << 15) 234 #define HCRX_PTTWI (UL(0x1) << 16) 235 #define HCRX_D128En (UL(0x1) << 17) 236 #define HCRX_EnSNERR (UL(0x1) << 18) 237 #define HCRX_TMEA (UL(0x1) << 19) 238 #define HCRX_EnSDERR (UL(0x1) << 20) 239 #define HCRX_EnIDCP128 (UL(0x1) << 21) 240 #define HCRX_GCSEn (UL(0x1) << 22) 241 #define HCRX_EnFPM (UL(0x1) << 23) 242 #define HCRX_PACMEn (UL(0x1) << 24) 243 /* Bit 25 is reserved */ 244 #define HCRX_SRMASKEn (UL(0x1) << 26) 245 246 /* HDFGRTR2_EL2 */ 247 #define HDFGRTR2_EL2_REG MRS_REG_ALT_NAME(HDFGRTR2_EL2) 248 #define HDFGRTR2_EL2_op0 3 249 #define HDFGRTR2_EL2_op1 4 250 #define HDFGRTR2_EL2_CRn 3 251 #define HDFGRTR2_EL2_CRm 1 252 #define HDFGRTR2_EL2_op2 0 253 #define HDFGRTR2_EL2_nMDSTEPOP_EL1_SHIFT 23 254 #define HDFGRTR2_EL2_nMDSTEPOP_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nMDSTEPOP_EL1_SHIFT) 255 #define HDFGRTR2_EL2_nMDSTEPOP_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nMDSTEPOP_EL1_MASK) 256 #define HDFGRTR2_EL2_nMDSTEPOP_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nMDSTEPOP_EL1_SHIFT) 257 #define HDFGRTR2_EL2_nMDSTEPOP_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nMDSTEPOP_EL1_SHIFT) 258 #define HDFGRTR2_EL2_nTRBMPAM_EL1_SHIFT 22 259 #define HDFGRTR2_EL2_nTRBMPAM_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nTRBMPAM_EL1_SHIFT) 260 #define HDFGRTR2_EL2_nTRBMPAM_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nTRBMPAM_EL1_MASK) 261 #define HDFGRTR2_EL2_nTRBMPAM_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nTRBMPAM_EL1_SHIFT) 262 #define HDFGRTR2_EL2_nTRBMPAM_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nTRBMPAM_EL1_SHIFT) 263 #define HDFGRTR2_EL2_nTRCITECR_EL1_SHIFT 20 264 #define HDFGRTR2_EL2_nTRCITECR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nTRCITECR_EL1_SHIFT) 265 #define HDFGRTR2_EL2_nTRCITECR_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nTRCITECR_EL1_MASK) 266 #define HDFGRTR2_EL2_nTRCITECR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nTRCITECR_EL1_SHIFT) 267 #define HDFGRTR2_EL2_nTRCITECR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nTRCITECR_EL1_SHIFT) 268 #define HDFGRTR2_EL2_nPMSDSFR_EL1_SHIFT 19 269 #define HDFGRTR2_EL2_nPMSDSFR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nPMSDSFR_EL1_SHIFT) 270 #define HDFGRTR2_EL2_nPMSDSFR_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nPMSDSFR_EL1_MASK) 271 #define HDFGRTR2_EL2_nPMSDSFR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMSDSFR_EL1_SHIFT) 272 #define HDFGRTR2_EL2_nPMSDSFR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMSDSFR_EL1_SHIFT) 273 #define HDFGRTR2_EL2_nSPMDEVAFF_EL1_SHIFT 18 274 #define HDFGRTR2_EL2_nSPMDEVAFF_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMDEVAFF_EL1_SHIFT) 275 #define HDFGRTR2_EL2_nSPMDEVAFF_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nSPMDEVAFF_EL1_MASK) 276 #define HDFGRTR2_EL2_nSPMDEVAFF_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMDEVAFF_EL1_SHIFT) 277 #define HDFGRTR2_EL2_nSPMDEVAFF_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMDEVAFF_EL1_SHIFT) 278 #define HDFGRTR2_EL2_nSPMID_SHIFT 17 279 #define HDFGRTR2_EL2_nSPMID_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMID_SHIFT) 280 #define HDFGRTR2_EL2_nSPMID_VAL(x) ((x) & HDFGRTR2_EL2_nSPMID_MASK) 281 #define HDFGRTR2_EL2_nSPMID_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMID_SHIFT) 282 #define HDFGRTR2_EL2_nSPMID_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMID_SHIFT) 283 #define HDFGRTR2_EL2_nSPMSCR_EL1_SHIFT 16 284 #define HDFGRTR2_EL2_nSPMSCR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMSCR_EL1_SHIFT) 285 #define HDFGRTR2_EL2_nSPMSCR_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nSPMSCR_EL1_MASK) 286 #define HDFGRTR2_EL2_nSPMSCR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMSCR_EL1_SHIFT) 287 #define HDFGRTR2_EL2_nSPMSCR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMSCR_EL1_SHIFT) 288 #define HDFGRTR2_EL2_nSPMACCESSR_EL1_SHIFT 15 289 #define HDFGRTR2_EL2_nSPMACCESSR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMACCESSR_EL1_SHIFT) 290 #define HDFGRTR2_EL2_nSPMACCESSR_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nSPMACCESSR_EL1_MASK) 291 #define HDFGRTR2_EL2_nSPMACCESSR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMACCESSR_EL1_SHIFT) 292 #define HDFGRTR2_EL2_nSPMACCESSR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMACCESSR_EL1_SHIFT) 293 #define HDFGRTR2_EL2_nSPMCR_EL0_SHIFT 14 294 #define HDFGRTR2_EL2_nSPMCR_EL0_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMCR_EL0_SHIFT) 295 #define HDFGRTR2_EL2_nSPMCR_EL0_VAL(x) ((x) & HDFGRTR2_EL2_nSPMCR_EL0_MASK) 296 #define HDFGRTR2_EL2_nSPMCR_EL0_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMCR_EL0_SHIFT) 297 #define HDFGRTR2_EL2_nSPMCR_EL0_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMCR_EL0_SHIFT) 298 #define HDFGRTR2_EL2_nSPMOVS_SHIFT 13 299 #define HDFGRTR2_EL2_nSPMOVS_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMOVS_SHIFT) 300 #define HDFGRTR2_EL2_nSPMOVS_VAL(x) ((x) & HDFGRTR2_EL2_nSPMOVS_MASK) 301 #define HDFGRTR2_EL2_nSPMOVS_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMOVS_SHIFT) 302 #define HDFGRTR2_EL2_nSPMOVS_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMOVS_SHIFT) 303 #define HDFGRTR2_EL2_nSPMINTEN_SHIFT 12 304 #define HDFGRTR2_EL2_nSPMINTEN_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMINTEN_SHIFT) 305 #define HDFGRTR2_EL2_nSPMINTEN_VAL(x) ((x) & HDFGRTR2_EL2_nSPMINTEN_MASK) 306 #define HDFGRTR2_EL2_nSPMINTEN_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMINTEN_SHIFT) 307 #define HDFGRTR2_EL2_nSPMINTEN_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMINTEN_SHIFT) 308 #define HDFGRTR2_EL2_nSPMCNTEN_SHIFT 11 309 #define HDFGRTR2_EL2_nSPMCNTEN_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMCNTEN_SHIFT) 310 #define HDFGRTR2_EL2_nSPMCNTEN_VAL(x) ((x) & HDFGRTR2_EL2_nSPMCNTEN_MASK) 311 #define HDFGRTR2_EL2_nSPMCNTEN_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMCNTEN_SHIFT) 312 #define HDFGRTR2_EL2_nSPMCNTEN_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMCNTEN_SHIFT) 313 #define HDFGRTR2_EL2_nSPMSELR_EL0_SHIFT 10 314 #define HDFGRTR2_EL2_nSPMSELR_EL0_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMSELR_EL0_SHIFT) 315 #define HDFGRTR2_EL2_nSPMSELR_EL0_VAL(x) ((x) & HDFGRTR2_EL2_nSPMSELR_EL0_MASK) 316 #define HDFGRTR2_EL2_nSPMSELR_EL0_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMSELR_EL0_SHIFT) 317 #define HDFGRTR2_EL2_nSPMSELR_EL0_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMSELR_EL0_SHIFT) 318 #define HDFGRTR2_EL2_nSPMEVTYPERn_EL0_SHIFT 9 319 #define HDFGRTR2_EL2_nSPMEVTYPERn_EL0_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMEVTYPERn_EL0_SHIFT) 320 #define HDFGRTR2_EL2_nSPMEVTYPERn_EL0_VAL(x) ((x) & HDFGRTR2_EL2_nSPMEVTYPERn_EL0_MASK) 321 #define HDFGRTR2_EL2_nSPMEVTYPERn_EL0_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMEVTYPERn_EL0_SHIFT) 322 #define HDFGRTR2_EL2_nSPMEVTYPERn_EL0_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMEVTYPERn_EL0_SHIFT) 323 #define HDFGRTR2_EL2_nSPMEVCNTRn_EL0_SHIFT 8 324 #define HDFGRTR2_EL2_nSPMEVCNTRn_EL0_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMEVCNTRn_EL0_SHIFT) 325 #define HDFGRTR2_EL2_nSPMEVCNTRn_EL0_VAL(x) ((x) & HDFGRTR2_EL2_nSPMEVCNTRn_EL0_MASK) 326 #define HDFGRTR2_EL2_nSPMEVCNTRn_EL0_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMEVCNTRn_EL0_SHIFT) 327 #define HDFGRTR2_EL2_nSPMEVCNTRn_EL0_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMEVCNTRn_EL0_SHIFT) 328 #define HDFGRTR2_EL2_nPMSSCR_EL1_SHIFT 7 329 #define HDFGRTR2_EL2_nPMSSCR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nPMSSCR_EL1_SHIFT) 330 #define HDFGRTR2_EL2_nPMSSCR_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nPMSSCR_EL1_MASK) 331 #define HDFGRTR2_EL2_nPMSSCR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMSSCR_EL1_SHIFT) 332 #define HDFGRTR2_EL2_nPMSSCR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMSSCR_EL1_SHIFT) 333 #define HDFGRTR2_EL2_nPMSSDATA_SHIFT 6 334 #define HDFGRTR2_EL2_nPMSSDATA_MASK (UL(0x1) << HDFGRTR2_EL2_nPMSSDATA_SHIFT) 335 #define HDFGRTR2_EL2_nPMSSDATA_VAL(x) ((x) & HDFGRTR2_EL2_nPMSSDATA_MASK) 336 #define HDFGRTR2_EL2_nPMSSDATA_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMSSDATA_SHIFT) 337 #define HDFGRTR2_EL2_nPMSSDATA_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMSSDATA_SHIFT) 338 #define HDFGRTR2_EL2_nMDSELR_EL1_SHIFT 5 339 #define HDFGRTR2_EL2_nMDSELR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nMDSELR_EL1_SHIFT) 340 #define HDFGRTR2_EL2_nMDSELR_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nMDSELR_EL1_MASK) 341 #define HDFGRTR2_EL2_nMDSELR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nMDSELR_EL1_SHIFT) 342 #define HDFGRTR2_EL2_nMDSELR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nMDSELR_EL1_SHIFT) 343 #define HDFGRTR2_EL2_nPMUACR_EL1_SHIFT 4 344 #define HDFGRTR2_EL2_nPMUACR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nPMUACR_EL1_SHIFT) 345 #define HDFGRTR2_EL2_nPMUACR_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nPMUACR_EL1_MASK) 346 #define HDFGRTR2_EL2_nPMUACR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMUACR_EL1_SHIFT) 347 #define HDFGRTR2_EL2_nPMUACR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMUACR_EL1_SHIFT) 348 #define HDFGRTR2_EL2_nPMICFILTR_EL0_SHIFT 3 349 #define HDFGRTR2_EL2_nPMICFILTR_EL0_MASK (UL(0x1) << HDFGRTR2_EL2_nPMICFILTR_EL0_SHIFT) 350 #define HDFGRTR2_EL2_nPMICFILTR_EL0_VAL(x) ((x) & HDFGRTR2_EL2_nPMICFILTR_EL0_MASK) 351 #define HDFGRTR2_EL2_nPMICFILTR_EL0_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMICFILTR_EL0_SHIFT) 352 #define HDFGRTR2_EL2_nPMICFILTR_EL0_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMICFILTR_EL0_SHIFT) 353 #define HDFGRTR2_EL2_nPMICNTR_EL0_SHIFT 2 354 #define HDFGRTR2_EL2_nPMICNTR_EL0_MASK (UL(0x1) << HDFGRTR2_EL2_nPMICNTR_EL0_SHIFT) 355 #define HDFGRTR2_EL2_nPMICNTR_EL0_VAL(x) ((x) & HDFGRTR2_EL2_nPMICNTR_EL0_MASK) 356 #define HDFGRTR2_EL2_nPMICNTR_EL0_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMICNTR_EL0_SHIFT) 357 #define HDFGRTR2_EL2_nPMICNTR_EL0_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMICNTR_EL0_SHIFT) 358 #define HDFGRTR2_EL2_nPMIAR_EL1_SHIFT 1 359 #define HDFGRTR2_EL2_nPMIAR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nPMIAR_EL1_SHIFT) 360 #define HDFGRTR2_EL2_nPMIAR_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nPMIAR_EL1_MASK) 361 #define HDFGRTR2_EL2_nPMIAR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMIAR_EL1_SHIFT) 362 #define HDFGRTR2_EL2_nPMIAR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMIAR_EL1_SHIFT) 363 #define HDFGRTR2_EL2_nPMECR_EL1_SHIFT 0 364 #define HDFGRTR2_EL2_nPMECR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nPMECR_EL1_SHIFT) 365 #define HDFGRTR2_EL2_nPMECR_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nPMECR_EL1_MASK) 366 #define HDFGRTR2_EL2_nPMECR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMECR_EL1_SHIFT) 367 #define HDFGRTR2_EL2_nPMECR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMECR_EL1_SHIFT) 368 369 /* HDFGRTR_EL2 */ 370 #define HDFGRTR_EL2_REG MRS_REG_ALT_NAME(HDFGRTR_EL2) 371 #define HDFGRTR_EL2_op0 3 372 #define HDFGRTR_EL2_op1 4 373 #define HDFGRTR_EL2_CRn 3 374 #define HDFGRTR_EL2_CRm 1 375 #define HDFGRTR_EL2_op2 4 376 #define HDFGRTR_EL2_PMBIDR_EL1_SHIFT 63 377 #define HDFGRTR_EL2_PMBIDR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMBIDR_EL1_SHIFT) 378 #define HDFGRTR_EL2_PMBIDR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMBIDR_EL1_MASK) 379 #define HDFGRTR_EL2_PMBIDR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMBIDR_EL1_SHIFT) 380 #define HDFGRTR_EL2_PMBIDR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMBIDR_EL1_SHIFT) 381 #define HDFGRTR_EL2_nPMSNEVFR_EL1_SHIFT 62 382 #define HDFGRTR_EL2_nPMSNEVFR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_nPMSNEVFR_EL1_SHIFT) 383 #define HDFGRTR_EL2_nPMSNEVFR_EL1_VAL(x) ((x) & HDFGRTR_EL2_nPMSNEVFR_EL1_MASK) 384 #define HDFGRTR_EL2_nPMSNEVFR_EL1_TRAP (UL(0x0) << HDFGRTR_EL2_nPMSNEVFR_EL1_SHIFT) 385 #define HDFGRTR_EL2_nPMSNEVFR_EL1_NOTRAP (UL(0x1) << HDFGRTR_EL2_nPMSNEVFR_EL1_SHIFT) 386 #define HDFGRTR_EL2_nBRBDATA_SHIFT 61 387 #define HDFGRTR_EL2_nBRBDATA_MASK (UL(0x1) << HDFGRTR_EL2_nBRBDATA_SHIFT) 388 #define HDFGRTR_EL2_nBRBDATA_VAL(x) ((x) & HDFGRTR_EL2_nBRBDATA_MASK) 389 #define HDFGRTR_EL2_nBRBDATA_TRAP (UL(0x0) << HDFGRTR_EL2_nBRBDATA_SHIFT) 390 #define HDFGRTR_EL2_nBRBDATA_NOTRAP (UL(0x1) << HDFGRTR_EL2_nBRBDATA_SHIFT) 391 #define HDFGRTR_EL2_nBRBCTL_SHIFT 60 392 #define HDFGRTR_EL2_nBRBCTL_MASK (UL(0x1) << HDFGRTR_EL2_nBRBCTL_SHIFT) 393 #define HDFGRTR_EL2_nBRBCTL_VAL(x) ((x) & HDFGRTR_EL2_nBRBCTL_MASK) 394 #define HDFGRTR_EL2_nBRBCTL_TRAP (UL(0x0) << HDFGRTR_EL2_nBRBCTL_SHIFT) 395 #define HDFGRTR_EL2_nBRBCTL_NOTRAP (UL(0x1) << HDFGRTR_EL2_nBRBCTL_SHIFT) 396 #define HDFGRTR_EL2_nBRBIDR_SHIFT 59 397 #define HDFGRTR_EL2_nBRBIDR_MASK (UL(0x1) << HDFGRTR_EL2_nBRBIDR_SHIFT) 398 #define HDFGRTR_EL2_nBRBIDR_VAL(x) ((x) & HDFGRTR_EL2_nBRBIDR_MASK) 399 #define HDFGRTR_EL2_nBRBIDR_TRAP (UL(0x0) << HDFGRTR_EL2_nBRBIDR_SHIFT) 400 #define HDFGRTR_EL2_nBRBIDR_NOTRAP (UL(0x1) << HDFGRTR_EL2_nBRBIDR_SHIFT) 401 #define HDFGRTR_EL2_PMCEIDn_EL0_SHIFT 58 402 #define HDFGRTR_EL2_PMCEIDn_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMCEIDn_EL0_SHIFT) 403 #define HDFGRTR_EL2_PMCEIDn_EL0_VAL(x) ((x) & HDFGRTR_EL2_PMCEIDn_EL0_MASK) 404 #define HDFGRTR_EL2_PMCEIDn_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMCEIDn_EL0_SHIFT) 405 #define HDFGRTR_EL2_PMCEIDn_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMCEIDn_EL0_SHIFT) 406 #define HDFGRTR_EL2_PMUSERENR_EL0_SHIFT 57 407 #define HDFGRTR_EL2_PMUSERENR_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMUSERENR_EL0_SHIFT) 408 #define HDFGRTR_EL2_PMUSERENR_EL0_VAL(x) ((x) & HDFGRTR_EL2_PMUSERENR_EL0_MASK) 409 #define HDFGRTR_EL2_PMUSERENR_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMUSERENR_EL0_SHIFT) 410 #define HDFGRTR_EL2_PMUSERENR_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMUSERENR_EL0_SHIFT) 411 #define HDFGRTR_EL2_TRBTRG_EL1_SHIFT 56 412 #define HDFGRTR_EL2_TRBTRG_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBTRG_EL1_SHIFT) 413 #define HDFGRTR_EL2_TRBTRG_EL1_VAL(x) ((x) & HDFGRTR_EL2_TRBTRG_EL1_MASK) 414 #define HDFGRTR_EL2_TRBTRG_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBTRG_EL1_SHIFT) 415 #define HDFGRTR_EL2_TRBTRG_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBTRG_EL1_SHIFT) 416 #define HDFGRTR_EL2_TRBSR_EL1_SHIFT 55 417 #define HDFGRTR_EL2_TRBSR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBSR_EL1_SHIFT) 418 #define HDFGRTR_EL2_TRBSR_EL1_VAL(x) ((x) & HDFGRTR_EL2_TRBSR_EL1_MASK) 419 #define HDFGRTR_EL2_TRBSR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBSR_EL1_SHIFT) 420 #define HDFGRTR_EL2_TRBSR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBSR_EL1_SHIFT) 421 #define HDFGRTR_EL2_TRBPTR_EL1_SHIFT 54 422 #define HDFGRTR_EL2_TRBPTR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBPTR_EL1_SHIFT) 423 #define HDFGRTR_EL2_TRBPTR_EL1_VAL(x) ((x) & HDFGRTR_EL2_TRBPTR_EL1_MASK) 424 #define HDFGRTR_EL2_TRBPTR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBPTR_EL1_SHIFT) 425 #define HDFGRTR_EL2_TRBPTR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBPTR_EL1_SHIFT) 426 #define HDFGRTR_EL2_TRBMAR_EL1_SHIFT 53 427 #define HDFGRTR_EL2_TRBMAR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBMAR_EL1_SHIFT) 428 #define HDFGRTR_EL2_TRBMAR_EL1_VAL(x) ((x) & HDFGRTR_EL2_TRBMAR_EL1_MASK) 429 #define HDFGRTR_EL2_TRBMAR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBMAR_EL1_SHIFT) 430 #define HDFGRTR_EL2_TRBMAR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBMAR_EL1_SHIFT) 431 #define HDFGRTR_EL2_TRBLIMITR_EL1_SHIFT 52 432 #define HDFGRTR_EL2_TRBLIMITR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBLIMITR_EL1_SHIFT) 433 #define HDFGRTR_EL2_TRBLIMITR_EL1_VAL(x) ((x) & HDFGRTR_EL2_TRBLIMITR_EL1_MASK) 434 #define HDFGRTR_EL2_TRBLIMITR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBLIMITR_EL1_SHIFT) 435 #define HDFGRTR_EL2_TRBLIMITR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBLIMITR_EL1_SHIFT) 436 #define HDFGRTR_EL2_TRBIDR_EL1_SHIFT 51 437 #define HDFGRTR_EL2_TRBIDR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBIDR_EL1_SHIFT) 438 #define HDFGRTR_EL2_TRBIDR_EL1_VAL(x) ((x) & HDFGRTR_EL2_TRBIDR_EL1_MASK) 439 #define HDFGRTR_EL2_TRBIDR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBIDR_EL1_SHIFT) 440 #define HDFGRTR_EL2_TRBIDR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBIDR_EL1_SHIFT) 441 #define HDFGRTR_EL2_TRBBASER_EL1_SHIFT 50 442 #define HDFGRTR_EL2_TRBBASER_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBBASER_EL1_SHIFT) 443 #define HDFGRTR_EL2_TRBBASER_EL1_VAL(x) ((x) & HDFGRTR_EL2_TRBBASER_EL1_MASK) 444 #define HDFGRTR_EL2_TRBBASER_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBBASER_EL1_SHIFT) 445 #define HDFGRTR_EL2_TRBBASER_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBBASER_EL1_SHIFT) 446 #define HDFGRTR_EL2_TRCVICTLR_SHIFT 48 447 #define HDFGRTR_EL2_TRCVICTLR_MASK (UL(0x1) << HDFGRTR_EL2_TRCVICTLR_SHIFT) 448 #define HDFGRTR_EL2_TRCVICTLR_VAL(x) ((x) & HDFGRTR_EL2_TRCVICTLR_MASK) 449 #define HDFGRTR_EL2_TRCVICTLR_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCVICTLR_SHIFT) 450 #define HDFGRTR_EL2_TRCVICTLR_TRAP (UL(0x1) << HDFGRTR_EL2_TRCVICTLR_SHIFT) 451 #define HDFGRTR_EL2_TRCSTATR_SHIFT 47 452 #define HDFGRTR_EL2_TRCSTATR_MASK (UL(0x1) << HDFGRTR_EL2_TRCSTATR_SHIFT) 453 #define HDFGRTR_EL2_TRCSTATR_VAL(x) ((x) & HDFGRTR_EL2_TRCSTATR_MASK) 454 #define HDFGRTR_EL2_TRCSTATR_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCSTATR_SHIFT) 455 #define HDFGRTR_EL2_TRCSTATR_TRAP (UL(0x1) << HDFGRTR_EL2_TRCSTATR_SHIFT) 456 #define HDFGRTR_EL2_TRCSSCSRn_SHIFT 46 457 #define HDFGRTR_EL2_TRCSSCSRn_MASK (UL(0x1) << HDFGRTR_EL2_TRCSSCSRn_SHIFT) 458 #define HDFGRTR_EL2_TRCSSCSRn_VAL(x) ((x) & HDFGRTR_EL2_TRCSSCSRn_MASK) 459 #define HDFGRTR_EL2_TRCSSCSRn_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCSSCSRn_SHIFT) 460 #define HDFGRTR_EL2_TRCSSCSRn_TRAP (UL(0x1) << HDFGRTR_EL2_TRCSSCSRn_SHIFT) 461 #define HDFGRTR_EL2_TRCSEQSTR_SHIFT 45 462 #define HDFGRTR_EL2_TRCSEQSTR_MASK (UL(0x1) << HDFGRTR_EL2_TRCSEQSTR_SHIFT) 463 #define HDFGRTR_EL2_TRCSEQSTR_VAL(x) ((x) & HDFGRTR_EL2_TRCSEQSTR_MASK) 464 #define HDFGRTR_EL2_TRCSEQSTR_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCSEQSTR_SHIFT) 465 #define HDFGRTR_EL2_TRCSEQSTR_TRAP (UL(0x1) << HDFGRTR_EL2_TRCSEQSTR_SHIFT) 466 #define HDFGRTR_EL2_TRCPRGCTLR_SHIFT 44 467 #define HDFGRTR_EL2_TRCPRGCTLR_MASK (UL(0x1) << HDFGRTR_EL2_TRCPRGCTLR_SHIFT) 468 #define HDFGRTR_EL2_TRCPRGCTLR_VAL(x) ((x) & HDFGRTR_EL2_TRCPRGCTLR_MASK) 469 #define HDFGRTR_EL2_TRCPRGCTLR_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCPRGCTLR_SHIFT) 470 #define HDFGRTR_EL2_TRCPRGCTLR_TRAP (UL(0x1) << HDFGRTR_EL2_TRCPRGCTLR_SHIFT) 471 #define HDFGRTR_EL2_TRCOSLSR_SHIFT 43 472 #define HDFGRTR_EL2_TRCOSLSR_MASK (UL(0x1) << HDFGRTR_EL2_TRCOSLSR_SHIFT) 473 #define HDFGRTR_EL2_TRCOSLSR_VAL(x) ((x) & HDFGRTR_EL2_TRCOSLSR_MASK) 474 #define HDFGRTR_EL2_TRCOSLSR_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCOSLSR_SHIFT) 475 #define HDFGRTR_EL2_TRCOSLSR_TRAP (UL(0x1) << HDFGRTR_EL2_TRCOSLSR_SHIFT) 476 #define HDFGRTR_EL2_TRCIMSPECn_SHIFT 41 477 #define HDFGRTR_EL2_TRCIMSPECn_MASK (UL(0x1) << HDFGRTR_EL2_TRCIMSPECn_SHIFT) 478 #define HDFGRTR_EL2_TRCIMSPECn_VAL(x) ((x) & HDFGRTR_EL2_TRCIMSPECn_MASK) 479 #define HDFGRTR_EL2_TRCIMSPECn_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCIMSPECn_SHIFT) 480 #define HDFGRTR_EL2_TRCIMSPECn_TRAP (UL(0x1) << HDFGRTR_EL2_TRCIMSPECn_SHIFT) 481 #define HDFGRTR_EL2_TRCID_SHIFT 40 482 #define HDFGRTR_EL2_TRCID_MASK (UL(0x1) << HDFGRTR_EL2_TRCID_SHIFT) 483 #define HDFGRTR_EL2_TRCID_VAL(x) ((x) & HDFGRTR_EL2_TRCID_MASK) 484 #define HDFGRTR_EL2_TRCID_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCID_SHIFT) 485 #define HDFGRTR_EL2_TRCID_TRAP (UL(0x1) << HDFGRTR_EL2_TRCID_SHIFT) 486 #define HDFGRTR_EL2_TRCCNTVRn_SHIFT 37 487 #define HDFGRTR_EL2_TRCCNTVRn_MASK (UL(0x1) << HDFGRTR_EL2_TRCCNTVRn_SHIFT) 488 #define HDFGRTR_EL2_TRCCNTVRn_VAL(x) ((x) & HDFGRTR_EL2_TRCCNTVRn_MASK) 489 #define HDFGRTR_EL2_TRCCNTVRn_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCCNTVRn_SHIFT) 490 #define HDFGRTR_EL2_TRCCNTVRn_TRAP (UL(0x1) << HDFGRTR_EL2_TRCCNTVRn_SHIFT) 491 #define HDFGRTR_EL2_TRCCLAIM_SHIFT 36 492 #define HDFGRTR_EL2_TRCCLAIM_MASK (UL(0x1) << HDFGRTR_EL2_TRCCLAIM_SHIFT) 493 #define HDFGRTR_EL2_TRCCLAIM_VAL(x) ((x) & HDFGRTR_EL2_TRCCLAIM_MASK) 494 #define HDFGRTR_EL2_TRCCLAIM_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCCLAIM_SHIFT) 495 #define HDFGRTR_EL2_TRCCLAIM_TRAP (UL(0x1) << HDFGRTR_EL2_TRCCLAIM_SHIFT) 496 #define HDFGRTR_EL2_TRCAUXCTLR_SHIFT 35 497 #define HDFGRTR_EL2_TRCAUXCTLR_MASK (UL(0x1) << HDFGRTR_EL2_TRCAUXCTLR_SHIFT) 498 #define HDFGRTR_EL2_TRCAUXCTLR_VAL(x) ((x) & HDFGRTR_EL2_TRCAUXCTLR_MASK) 499 #define HDFGRTR_EL2_TRCAUXCTLR_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCAUXCTLR_SHIFT) 500 #define HDFGRTR_EL2_TRCAUXCTLR_TRAP (UL(0x1) << HDFGRTR_EL2_TRCAUXCTLR_SHIFT) 501 #define HDFGRTR_EL2_TRCAUTHSTATUS_SHIFT 34 502 #define HDFGRTR_EL2_TRCAUTHSTATUS_MASK (UL(0x1) << HDFGRTR_EL2_TRCAUTHSTATUS_SHIFT) 503 #define HDFGRTR_EL2_TRCAUTHSTATUS_VAL(x) ((x) & HDFGRTR_EL2_TRCAUTHSTATUS_MASK) 504 #define HDFGRTR_EL2_TRCAUTHSTATUS_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCAUTHSTATUS_SHIFT) 505 #define HDFGRTR_EL2_TRCAUTHSTATUS_TRAP (UL(0x1) << HDFGRTR_EL2_TRCAUTHSTATUS_SHIFT) 506 #define HDFGRTR_EL2_TRC_SHIFT 33 507 #define HDFGRTR_EL2_TRC_MASK (UL(0x1) << HDFGRTR_EL2_TRC_SHIFT) 508 #define HDFGRTR_EL2_TRC_VAL(x) ((x) & HDFGRTR_EL2_TRC_MASK) 509 #define HDFGRTR_EL2_TRC_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRC_SHIFT) 510 #define HDFGRTR_EL2_TRC_TRAP (UL(0x1) << HDFGRTR_EL2_TRC_SHIFT) 511 #define HDFGRTR_EL2_PMSLATFR_EL1_SHIFT 32 512 #define HDFGRTR_EL2_PMSLATFR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSLATFR_EL1_SHIFT) 513 #define HDFGRTR_EL2_PMSLATFR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMSLATFR_EL1_MASK) 514 #define HDFGRTR_EL2_PMSLATFR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSLATFR_EL1_SHIFT) 515 #define HDFGRTR_EL2_PMSLATFR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSLATFR_EL1_SHIFT) 516 #define HDFGRTR_EL2_PMSIRR_EL1_SHIFT 31 517 #define HDFGRTR_EL2_PMSIRR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSIRR_EL1_SHIFT) 518 #define HDFGRTR_EL2_PMSIRR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMSIRR_EL1_MASK) 519 #define HDFGRTR_EL2_PMSIRR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSIRR_EL1_SHIFT) 520 #define HDFGRTR_EL2_PMSIRR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSIRR_EL1_SHIFT) 521 #define HDFGRTR_EL2_PMSIDR_EL1_SHIFT 30 522 #define HDFGRTR_EL2_PMSIDR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSIDR_EL1_SHIFT) 523 #define HDFGRTR_EL2_PMSIDR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMSIDR_EL1_MASK) 524 #define HDFGRTR_EL2_PMSIDR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSIDR_EL1_SHIFT) 525 #define HDFGRTR_EL2_PMSIDR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSIDR_EL1_SHIFT) 526 #define HDFGRTR_EL2_PMSICR_EL1_SHIFT 29 527 #define HDFGRTR_EL2_PMSICR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSICR_EL1_SHIFT) 528 #define HDFGRTR_EL2_PMSICR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMSICR_EL1_MASK) 529 #define HDFGRTR_EL2_PMSICR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSICR_EL1_SHIFT) 530 #define HDFGRTR_EL2_PMSICR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSICR_EL1_SHIFT) 531 #define HDFGRTR_EL2_PMSFCR_EL1_SHIFT 28 532 #define HDFGRTR_EL2_PMSFCR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSFCR_EL1_SHIFT) 533 #define HDFGRTR_EL2_PMSFCR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMSFCR_EL1_MASK) 534 #define HDFGRTR_EL2_PMSFCR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSFCR_EL1_SHIFT) 535 #define HDFGRTR_EL2_PMSFCR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSFCR_EL1_SHIFT) 536 #define HDFGRTR_EL2_PMSEVFR_EL1_SHIFT 27 537 #define HDFGRTR_EL2_PMSEVFR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSEVFR_EL1_SHIFT) 538 #define HDFGRTR_EL2_PMSEVFR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMSEVFR_EL1_MASK) 539 #define HDFGRTR_EL2_PMSEVFR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSEVFR_EL1_SHIFT) 540 #define HDFGRTR_EL2_PMSEVFR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSEVFR_EL1_SHIFT) 541 #define HDFGRTR_EL2_PMSCR_EL1_SHIFT 26 542 #define HDFGRTR_EL2_PMSCR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSCR_EL1_SHIFT) 543 #define HDFGRTR_EL2_PMSCR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMSCR_EL1_MASK) 544 #define HDFGRTR_EL2_PMSCR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSCR_EL1_SHIFT) 545 #define HDFGRTR_EL2_PMSCR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSCR_EL1_SHIFT) 546 #define HDFGRTR_EL2_PMBSR_EL1_SHIFT 25 547 #define HDFGRTR_EL2_PMBSR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMBSR_EL1_SHIFT) 548 #define HDFGRTR_EL2_PMBSR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMBSR_EL1_MASK) 549 #define HDFGRTR_EL2_PMBSR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMBSR_EL1_SHIFT) 550 #define HDFGRTR_EL2_PMBSR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMBSR_EL1_SHIFT) 551 #define HDFGRTR_EL2_PMBPTR_EL1_SHIFT 24 552 #define HDFGRTR_EL2_PMBPTR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMBPTR_EL1_SHIFT) 553 #define HDFGRTR_EL2_PMBPTR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMBPTR_EL1_MASK) 554 #define HDFGRTR_EL2_PMBPTR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMBPTR_EL1_SHIFT) 555 #define HDFGRTR_EL2_PMBPTR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMBPTR_EL1_SHIFT) 556 #define HDFGRTR_EL2_PMBLIMITR_EL1_SHIFT 23 557 #define HDFGRTR_EL2_PMBLIMITR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMBLIMITR_EL1_SHIFT) 558 #define HDFGRTR_EL2_PMBLIMITR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMBLIMITR_EL1_MASK) 559 #define HDFGRTR_EL2_PMBLIMITR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMBLIMITR_EL1_SHIFT) 560 #define HDFGRTR_EL2_PMBLIMITR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMBLIMITR_EL1_SHIFT) 561 #define HDFGRTR_EL2_PMMIR_EL1_SHIFT 22 562 #define HDFGRTR_EL2_PMMIR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMMIR_EL1_SHIFT) 563 #define HDFGRTR_EL2_PMMIR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMMIR_EL1_MASK) 564 #define HDFGRTR_EL2_PMMIR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMMIR_EL1_SHIFT) 565 #define HDFGRTR_EL2_PMMIR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMMIR_EL1_SHIFT) 566 #define HDFGRTR_EL2_PMSELR_EL0_SHIFT 19 567 #define HDFGRTR_EL2_PMSELR_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMSELR_EL0_SHIFT) 568 #define HDFGRTR_EL2_PMSELR_EL0_VAL(x) ((x) & HDFGRTR_EL2_PMSELR_EL0_MASK) 569 #define HDFGRTR_EL2_PMSELR_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSELR_EL0_SHIFT) 570 #define HDFGRTR_EL2_PMSELR_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMSELR_EL0_SHIFT) 571 #define HDFGRTR_EL2_PMOVS_SHIFT 18 572 #define HDFGRTR_EL2_PMOVS_MASK (UL(0x1) << HDFGRTR_EL2_PMOVS_SHIFT) 573 #define HDFGRTR_EL2_PMOVS_VAL(x) ((x) & HDFGRTR_EL2_PMOVS_MASK) 574 #define HDFGRTR_EL2_PMOVS_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMOVS_SHIFT) 575 #define HDFGRTR_EL2_PMOVS_TRAP (UL(0x1) << HDFGRTR_EL2_PMOVS_SHIFT) 576 #define HDFGRTR_EL2_PMINTEN_SHIFT 17 577 #define HDFGRTR_EL2_PMINTEN_MASK (UL(0x1) << HDFGRTR_EL2_PMINTEN_SHIFT) 578 #define HDFGRTR_EL2_PMINTEN_VAL(x) ((x) & HDFGRTR_EL2_PMINTEN_MASK) 579 #define HDFGRTR_EL2_PMINTEN_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMINTEN_SHIFT) 580 #define HDFGRTR_EL2_PMINTEN_TRAP (UL(0x1) << HDFGRTR_EL2_PMINTEN_SHIFT) 581 #define HDFGRTR_EL2_PMCNTEN_SHIFT 16 582 #define HDFGRTR_EL2_PMCNTEN_MASK (UL(0x1) << HDFGRTR_EL2_PMCNTEN_SHIFT) 583 #define HDFGRTR_EL2_PMCNTEN_VAL(x) ((x) & HDFGRTR_EL2_PMCNTEN_MASK) 584 #define HDFGRTR_EL2_PMCNTEN_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMCNTEN_SHIFT) 585 #define HDFGRTR_EL2_PMCNTEN_TRAP (UL(0x1) << HDFGRTR_EL2_PMCNTEN_SHIFT) 586 #define HDFGRTR_EL2_PMCCNTR_EL0_SHIFT 15 587 #define HDFGRTR_EL2_PMCCNTR_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMCCNTR_EL0_SHIFT) 588 #define HDFGRTR_EL2_PMCCNTR_EL0_VAL(x) ((x) & HDFGRTR_EL2_PMCCNTR_EL0_MASK) 589 #define HDFGRTR_EL2_PMCCNTR_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMCCNTR_EL0_SHIFT) 590 #define HDFGRTR_EL2_PMCCNTR_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMCCNTR_EL0_SHIFT) 591 #define HDFGRTR_EL2_PMCCFILTR_EL0_SHIFT 14 592 #define HDFGRTR_EL2_PMCCFILTR_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMCCFILTR_EL0_SHIFT) 593 #define HDFGRTR_EL2_PMCCFILTR_EL0_VAL(x) ((x) & HDFGRTR_EL2_PMCCFILTR_EL0_MASK) 594 #define HDFGRTR_EL2_PMCCFILTR_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMCCFILTR_EL0_SHIFT) 595 #define HDFGRTR_EL2_PMCCFILTR_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMCCFILTR_EL0_SHIFT) 596 #define HDFGRTR_EL2_PMEVTYPERn_EL0_SHIFT 13 597 #define HDFGRTR_EL2_PMEVTYPERn_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMEVTYPERn_EL0_SHIFT) 598 #define HDFGRTR_EL2_PMEVTYPERn_EL0_VAL(x) ((x) & HDFGRTR_EL2_PMEVTYPERn_EL0_MASK) 599 #define HDFGRTR_EL2_PMEVTYPERn_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMEVTYPERn_EL0_SHIFT) 600 #define HDFGRTR_EL2_PMEVTYPERn_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMEVTYPERn_EL0_SHIFT) 601 #define HDFGRTR_EL2_PMEVCNTRn_EL0_SHIFT 12 602 #define HDFGRTR_EL2_PMEVCNTRn_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMEVCNTRn_EL0_SHIFT) 603 #define HDFGRTR_EL2_PMEVCNTRn_EL0_VAL(x) ((x) & HDFGRTR_EL2_PMEVCNTRn_EL0_MASK) 604 #define HDFGRTR_EL2_PMEVCNTRn_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMEVCNTRn_EL0_SHIFT) 605 #define HDFGRTR_EL2_PMEVCNTRn_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMEVCNTRn_EL0_SHIFT) 606 #define HDFGRTR_EL2_OSDLR_EL1_SHIFT 11 607 #define HDFGRTR_EL2_OSDLR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_OSDLR_EL1_SHIFT) 608 #define HDFGRTR_EL2_OSDLR_EL1_VAL(x) ((x) & HDFGRTR_EL2_OSDLR_EL1_MASK) 609 #define HDFGRTR_EL2_OSDLR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_OSDLR_EL1_SHIFT) 610 #define HDFGRTR_EL2_OSDLR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_OSDLR_EL1_SHIFT) 611 #define HDFGRTR_EL2_OSECCR_EL1_SHIFT 10 612 #define HDFGRTR_EL2_OSECCR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_OSECCR_EL1_SHIFT) 613 #define HDFGRTR_EL2_OSECCR_EL1_VAL(x) ((x) & HDFGRTR_EL2_OSECCR_EL1_MASK) 614 #define HDFGRTR_EL2_OSECCR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_OSECCR_EL1_SHIFT) 615 #define HDFGRTR_EL2_OSECCR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_OSECCR_EL1_SHIFT) 616 #define HDFGRTR_EL2_OSLSR_EL1_SHIFT 9 617 #define HDFGRTR_EL2_OSLSR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_OSLSR_EL1_SHIFT) 618 #define HDFGRTR_EL2_OSLSR_EL1_VAL(x) ((x) & HDFGRTR_EL2_OSLSR_EL1_MASK) 619 #define HDFGRTR_EL2_OSLSR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_OSLSR_EL1_SHIFT) 620 #define HDFGRTR_EL2_OSLSR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_OSLSR_EL1_SHIFT) 621 #define HDFGRTR_EL2_DBGPRCR_EL1_SHIFT 7 622 #define HDFGRTR_EL2_DBGPRCR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_DBGPRCR_EL1_SHIFT) 623 #define HDFGRTR_EL2_DBGPRCR_EL1_VAL(x) ((x) & HDFGRTR_EL2_DBGPRCR_EL1_MASK) 624 #define HDFGRTR_EL2_DBGPRCR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGPRCR_EL1_SHIFT) 625 #define HDFGRTR_EL2_DBGPRCR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_DBGPRCR_EL1_SHIFT) 626 #define HDFGRTR_EL2_DBGAUTHSTATUS_EL1_SHIFT 6 627 #define HDFGRTR_EL2_DBGAUTHSTATUS_EL1_MASK (UL(0x1) << HDFGRTR_EL2_DBGAUTHSTATUS_EL1_SHIFT) 628 #define HDFGRTR_EL2_DBGAUTHSTATUS_EL1_VAL(x) ((x) & HDFGRTR_EL2_DBGAUTHSTATUS_EL1_MASK) 629 #define HDFGRTR_EL2_DBGAUTHSTATUS_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGAUTHSTATUS_EL1_SHIFT) 630 #define HDFGRTR_EL2_DBGAUTHSTATUS_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_DBGAUTHSTATUS_EL1_SHIFT) 631 #define HDFGRTR_EL2_DBGCLAIM_SHIFT 5 632 #define HDFGRTR_EL2_DBGCLAIM_MASK (UL(0x1) << HDFGRTR_EL2_DBGCLAIM_SHIFT) 633 #define HDFGRTR_EL2_DBGCLAIM_VAL(x) ((x) & HDFGRTR_EL2_DBGCLAIM_MASK) 634 #define HDFGRTR_EL2_DBGCLAIM_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGCLAIM_SHIFT) 635 #define HDFGRTR_EL2_DBGCLAIM_TRAP (UL(0x1) << HDFGRTR_EL2_DBGCLAIM_SHIFT) 636 #define HDFGRTR_EL2_MDSCR_EL1_SHIFT 4 637 #define HDFGRTR_EL2_MDSCR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_MDSCR_EL1_SHIFT) 638 #define HDFGRTR_EL2_MDSCR_EL1_VAL(x) ((x) & HDFGRTR_EL2_MDSCR_EL1_MASK) 639 #define HDFGRTR_EL2_MDSCR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_MDSCR_EL1_SHIFT) 640 #define HDFGRTR_EL2_MDSCR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_MDSCR_EL1_SHIFT) 641 #define HDFGRTR_EL2_DBGWVRn_EL1_SHIFT 3 642 #define HDFGRTR_EL2_DBGWVRn_EL1_MASK (UL(0x1) << HDFGRTR_EL2_DBGWVRn_EL1_SHIFT) 643 #define HDFGRTR_EL2_DBGWVRn_EL1_VAL(x) ((x) & HDFGRTR_EL2_DBGWVRn_EL1_MASK) 644 #define HDFGRTR_EL2_DBGWVRn_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGWVRn_EL1_SHIFT) 645 #define HDFGRTR_EL2_DBGWVRn_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_DBGWVRn_EL1_SHIFT) 646 #define HDFGRTR_EL2_DBGWCRn_EL1_SHIFT 2 647 #define HDFGRTR_EL2_DBGWCRn_EL1_MASK (UL(0x1) << HDFGRTR_EL2_DBGWCRn_EL1_SHIFT) 648 #define HDFGRTR_EL2_DBGWCRn_EL1_VAL(x) ((x) & HDFGRTR_EL2_DBGWCRn_EL1_MASK) 649 #define HDFGRTR_EL2_DBGWCRn_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGWCRn_EL1_SHIFT) 650 #define HDFGRTR_EL2_DBGWCRn_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_DBGWCRn_EL1_SHIFT) 651 #define HDFGRTR_EL2_DBGBVRn_EL1_SHIFT 1 652 #define HDFGRTR_EL2_DBGBVRn_EL1_MASK (UL(0x1) << HDFGRTR_EL2_DBGBVRn_EL1_SHIFT) 653 #define HDFGRTR_EL2_DBGBVRn_EL1_VAL(x) ((x) & HDFGRTR_EL2_DBGBVRn_EL1_MASK) 654 #define HDFGRTR_EL2_DBGBVRn_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGBVRn_EL1_SHIFT) 655 #define HDFGRTR_EL2_DBGBVRn_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_DBGBVRn_EL1_SHIFT) 656 #define HDFGRTR_EL2_DBGBCRn_EL1_SHIFT 0 657 #define HDFGRTR_EL2_DBGBCRn_EL1_MASK (UL(0x1) << HDFGRTR_EL2_DBGBCRn_EL1_SHIFT) 658 #define HDFGRTR_EL2_DBGBCRn_EL1_VAL(x) ((x) & HDFGRTR_EL2_DBGBCRn_EL1_MASK) 659 #define HDFGRTR_EL2_DBGBCRn_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGBCRn_EL1_SHIFT) 660 #define HDFGRTR_EL2_DBGBCRn_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_DBGBCRn_EL1_SHIFT) 661 662 /* HDFGWTR2_EL2 */ 663 #define HDFGWTR2_EL2_REG MRS_REG_ALT_NAME(HDFGWTR2_EL2) 664 #define HDFGWTR2_EL2_op0 3 665 #define HDFGWTR2_EL2_op1 4 666 #define HDFGWTR2_EL2_CRn 3 667 #define HDFGWTR2_EL2_CRm 1 668 #define HDFGWTR2_EL2_op2 1 669 #define HDFGWTR2_EL2_nMDSTEPOP_EL1_SHIFT 23 670 #define HDFGWTR2_EL2_nMDSTEPOP_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nMDSTEPOP_EL1_SHIFT) 671 #define HDFGWTR2_EL2_nMDSTEPOP_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nMDSTEPOP_EL1_MASK) 672 #define HDFGWTR2_EL2_nMDSTEPOP_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nMDSTEPOP_EL1_SHIFT) 673 #define HDFGWTR2_EL2_nMDSTEPOP_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nMDSTEPOP_EL1_SHIFT) 674 #define HDFGWTR2_EL2_nTRBMPAM_EL1_SHIFT 22 675 #define HDFGWTR2_EL2_nTRBMPAM_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nTRBMPAM_EL1_SHIFT) 676 #define HDFGWTR2_EL2_nTRBMPAM_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nTRBMPAM_EL1_MASK) 677 #define HDFGWTR2_EL2_nTRBMPAM_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nTRBMPAM_EL1_SHIFT) 678 #define HDFGWTR2_EL2_nTRBMPAM_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nTRBMPAM_EL1_SHIFT) 679 #define HDFGWTR2_EL2_nPMZR_EL0_SHIFT 21 680 #define HDFGWTR2_EL2_nPMZR_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nPMZR_EL0_SHIFT) 681 #define HDFGWTR2_EL2_nPMZR_EL0_VAL(x) ((x) & HDFGWTR2_EL2_nPMZR_EL0_MASK) 682 #define HDFGWTR2_EL2_nPMZR_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMZR_EL0_SHIFT) 683 #define HDFGWTR2_EL2_nPMZR_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMZR_EL0_SHIFT) 684 #define HDFGWTR2_EL2_nTRCITECR_EL1_SHIFT 20 685 #define HDFGWTR2_EL2_nTRCITECR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nTRCITECR_EL1_SHIFT) 686 #define HDFGWTR2_EL2_nTRCITECR_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nTRCITECR_EL1_MASK) 687 #define HDFGWTR2_EL2_nTRCITECR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nTRCITECR_EL1_SHIFT) 688 #define HDFGWTR2_EL2_nTRCITECR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nTRCITECR_EL1_SHIFT) 689 #define HDFGWTR2_EL2_nPMSDSFR_EL1_SHIFT 19 690 #define HDFGWTR2_EL2_nPMSDSFR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nPMSDSFR_EL1_SHIFT) 691 #define HDFGWTR2_EL2_nPMSDSFR_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nPMSDSFR_EL1_MASK) 692 #define HDFGWTR2_EL2_nPMSDSFR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMSDSFR_EL1_SHIFT) 693 #define HDFGWTR2_EL2_nPMSDSFR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMSDSFR_EL1_SHIFT) 694 #define HDFGWTR2_EL2_nSPMSCR_EL1_SHIFT 16 695 #define HDFGWTR2_EL2_nSPMSCR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMSCR_EL1_SHIFT) 696 #define HDFGWTR2_EL2_nSPMSCR_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nSPMSCR_EL1_MASK) 697 #define HDFGWTR2_EL2_nSPMSCR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMSCR_EL1_SHIFT) 698 #define HDFGWTR2_EL2_nSPMSCR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMSCR_EL1_SHIFT) 699 #define HDFGWTR2_EL2_nSPMACCESSR_EL1_SHIFT 15 700 #define HDFGWTR2_EL2_nSPMACCESSR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMACCESSR_EL1_SHIFT) 701 #define HDFGWTR2_EL2_nSPMACCESSR_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nSPMACCESSR_EL1_MASK) 702 #define HDFGWTR2_EL2_nSPMACCESSR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMACCESSR_EL1_SHIFT) 703 #define HDFGWTR2_EL2_nSPMACCESSR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMACCESSR_EL1_SHIFT) 704 #define HDFGWTR2_EL2_nSPMCR_EL0_SHIFT 14 705 #define HDFGWTR2_EL2_nSPMCR_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMCR_EL0_SHIFT) 706 #define HDFGWTR2_EL2_nSPMCR_EL0_VAL(x) ((x) & HDFGWTR2_EL2_nSPMCR_EL0_MASK) 707 #define HDFGWTR2_EL2_nSPMCR_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMCR_EL0_SHIFT) 708 #define HDFGWTR2_EL2_nSPMCR_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMCR_EL0_SHIFT) 709 #define HDFGWTR2_EL2_nSPMOVS_SHIFT 13 710 #define HDFGWTR2_EL2_nSPMOVS_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMOVS_SHIFT) 711 #define HDFGWTR2_EL2_nSPMOVS_VAL(x) ((x) & HDFGWTR2_EL2_nSPMOVS_MASK) 712 #define HDFGWTR2_EL2_nSPMOVS_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMOVS_SHIFT) 713 #define HDFGWTR2_EL2_nSPMOVS_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMOVS_SHIFT) 714 #define HDFGWTR2_EL2_nSPMINTEN_SHIFT 12 715 #define HDFGWTR2_EL2_nSPMINTEN_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMINTEN_SHIFT) 716 #define HDFGWTR2_EL2_nSPMINTEN_VAL(x) ((x) & HDFGWTR2_EL2_nSPMINTEN_MASK) 717 #define HDFGWTR2_EL2_nSPMINTEN_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMINTEN_SHIFT) 718 #define HDFGWTR2_EL2_nSPMINTEN_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMINTEN_SHIFT) 719 #define HDFGWTR2_EL2_nSPMCNTEN_SHIFT 11 720 #define HDFGWTR2_EL2_nSPMCNTEN_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMCNTEN_SHIFT) 721 #define HDFGWTR2_EL2_nSPMCNTEN_VAL(x) ((x) & HDFGWTR2_EL2_nSPMCNTEN_MASK) 722 #define HDFGWTR2_EL2_nSPMCNTEN_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMCNTEN_SHIFT) 723 #define HDFGWTR2_EL2_nSPMCNTEN_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMCNTEN_SHIFT) 724 #define HDFGWTR2_EL2_nSPMSELR_EL0_SHIFT 10 725 #define HDFGWTR2_EL2_nSPMSELR_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMSELR_EL0_SHIFT) 726 #define HDFGWTR2_EL2_nSPMSELR_EL0_VAL(x) ((x) & HDFGWTR2_EL2_nSPMSELR_EL0_MASK) 727 #define HDFGWTR2_EL2_nSPMSELR_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMSELR_EL0_SHIFT) 728 #define HDFGWTR2_EL2_nSPMSELR_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMSELR_EL0_SHIFT) 729 #define HDFGWTR2_EL2_nSPMEVTYPERn_EL0_SHIFT 9 730 #define HDFGWTR2_EL2_nSPMEVTYPERn_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMEVTYPERn_EL0_SHIFT) 731 #define HDFGWTR2_EL2_nSPMEVTYPERn_EL0_VAL(x) ((x) & HDFGWTR2_EL2_nSPMEVTYPERn_EL0_MASK) 732 #define HDFGWTR2_EL2_nSPMEVTYPERn_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMEVTYPERn_EL0_SHIFT) 733 #define HDFGWTR2_EL2_nSPMEVTYPERn_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMEVTYPERn_EL0_SHIFT) 734 #define HDFGWTR2_EL2_nSPMEVCNTRn_EL0_SHIFT 8 735 #define HDFGWTR2_EL2_nSPMEVCNTRn_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMEVCNTRn_EL0_SHIFT) 736 #define HDFGWTR2_EL2_nSPMEVCNTRn_EL0_VAL(x) ((x) & HDFGWTR2_EL2_nSPMEVCNTRn_EL0_MASK) 737 #define HDFGWTR2_EL2_nSPMEVCNTRn_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMEVCNTRn_EL0_SHIFT) 738 #define HDFGWTR2_EL2_nSPMEVCNTRn_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMEVCNTRn_EL0_SHIFT) 739 #define HDFGWTR2_EL2_nPMSSCR_EL1_SHIFT 7 740 #define HDFGWTR2_EL2_nPMSSCR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nPMSSCR_EL1_SHIFT) 741 #define HDFGWTR2_EL2_nPMSSCR_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nPMSSCR_EL1_MASK) 742 #define HDFGWTR2_EL2_nPMSSCR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMSSCR_EL1_SHIFT) 743 #define HDFGWTR2_EL2_nPMSSCR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMSSCR_EL1_SHIFT) 744 #define HDFGWTR2_EL2_nMDSELR_EL1_SHIFT 5 745 #define HDFGWTR2_EL2_nMDSELR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nMDSELR_EL1_SHIFT) 746 #define HDFGWTR2_EL2_nMDSELR_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nMDSELR_EL1_MASK) 747 #define HDFGWTR2_EL2_nMDSELR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nMDSELR_EL1_SHIFT) 748 #define HDFGWTR2_EL2_nMDSELR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nMDSELR_EL1_SHIFT) 749 #define HDFGWTR2_EL2_nPMUACR_EL1_SHIFT 4 750 #define HDFGWTR2_EL2_nPMUACR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nPMUACR_EL1_SHIFT) 751 #define HDFGWTR2_EL2_nPMUACR_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nPMUACR_EL1_MASK) 752 #define HDFGWTR2_EL2_nPMUACR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMUACR_EL1_SHIFT) 753 #define HDFGWTR2_EL2_nPMUACR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMUACR_EL1_SHIFT) 754 #define HDFGWTR2_EL2_nPMICFILTR_EL0_SHIFT 3 755 #define HDFGWTR2_EL2_nPMICFILTR_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nPMICFILTR_EL0_SHIFT) 756 #define HDFGWTR2_EL2_nPMICFILTR_EL0_VAL(x) ((x) & HDFGWTR2_EL2_nPMICFILTR_EL0_MASK) 757 #define HDFGWTR2_EL2_nPMICFILTR_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMICFILTR_EL0_SHIFT) 758 #define HDFGWTR2_EL2_nPMICFILTR_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMICFILTR_EL0_SHIFT) 759 #define HDFGWTR2_EL2_nPMICNTR_EL0_SHIFT 2 760 #define HDFGWTR2_EL2_nPMICNTR_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nPMICNTR_EL0_SHIFT) 761 #define HDFGWTR2_EL2_nPMICNTR_EL0_VAL(x) ((x) & HDFGWTR2_EL2_nPMICNTR_EL0_MASK) 762 #define HDFGWTR2_EL2_nPMICNTR_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMICNTR_EL0_SHIFT) 763 #define HDFGWTR2_EL2_nPMICNTR_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMICNTR_EL0_SHIFT) 764 #define HDFGWTR2_EL2_nPMIAR_EL1_SHIFT 1 765 #define HDFGWTR2_EL2_nPMIAR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nPMIAR_EL1_SHIFT) 766 #define HDFGWTR2_EL2_nPMIAR_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nPMIAR_EL1_MASK) 767 #define HDFGWTR2_EL2_nPMIAR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMIAR_EL1_SHIFT) 768 #define HDFGWTR2_EL2_nPMIAR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMIAR_EL1_SHIFT) 769 #define HDFGWTR2_EL2_nPMECR_EL1_SHIFT 0 770 #define HDFGWTR2_EL2_nPMECR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nPMECR_EL1_SHIFT) 771 #define HDFGWTR2_EL2_nPMECR_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nPMECR_EL1_MASK) 772 #define HDFGWTR2_EL2_nPMECR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMECR_EL1_SHIFT) 773 #define HDFGWTR2_EL2_nPMECR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMECR_EL1_SHIFT) 774 775 /* HDFGWTR_EL2 */ 776 #define HDFGWTR_EL2_REG MRS_REG_ALT_NAME(HDFGWTR_EL2) 777 #define HDFGWTR_EL2_op0 3 778 #define HDFGWTR_EL2_op1 4 779 #define HDFGWTR_EL2_CRn 3 780 #define HDFGWTR_EL2_CRm 1 781 #define HDFGWTR_EL2_op2 5 782 #define HDFGWTR_EL2_nPMSNEVFR_EL1_SHIFT 62 783 #define HDFGWTR_EL2_nPMSNEVFR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_nPMSNEVFR_EL1_SHIFT) 784 #define HDFGWTR_EL2_nPMSNEVFR_EL1_VAL(x) ((x) & HDFGWTR_EL2_nPMSNEVFR_EL1_MASK) 785 #define HDFGWTR_EL2_nPMSNEVFR_EL1_TRAP (UL(0x0) << HDFGWTR_EL2_nPMSNEVFR_EL1_SHIFT) 786 #define HDFGWTR_EL2_nPMSNEVFR_EL1_NOTRAP (UL(0x1) << HDFGWTR_EL2_nPMSNEVFR_EL1_SHIFT) 787 #define HDFGWTR_EL2_nBRBDATA_SHIFT 61 788 #define HDFGWTR_EL2_nBRBDATA_MASK (UL(0x1) << HDFGWTR_EL2_nBRBDATA_SHIFT) 789 #define HDFGWTR_EL2_nBRBDATA_VAL(x) ((x) & HDFGWTR_EL2_nBRBDATA_MASK) 790 #define HDFGWTR_EL2_nBRBDATA_TRAP (UL(0x0) << HDFGWTR_EL2_nBRBDATA_SHIFT) 791 #define HDFGWTR_EL2_nBRBDATA_NOTRAP (UL(0x1) << HDFGWTR_EL2_nBRBDATA_SHIFT) 792 #define HDFGWTR_EL2_nBRBCTL_SHIFT 60 793 #define HDFGWTR_EL2_nBRBCTL_MASK (UL(0x1) << HDFGWTR_EL2_nBRBCTL_SHIFT) 794 #define HDFGWTR_EL2_nBRBCTL_VAL(x) ((x) & HDFGWTR_EL2_nBRBCTL_MASK) 795 #define HDFGWTR_EL2_nBRBCTL_TRAP (UL(0x0) << HDFGWTR_EL2_nBRBCTL_SHIFT) 796 #define HDFGWTR_EL2_nBRBCTL_NOTRAP (UL(0x1) << HDFGWTR_EL2_nBRBCTL_SHIFT) 797 #define HDFGWTR_EL2_PMUSERENR_EL0_SHIFT 57 798 #define HDFGWTR_EL2_PMUSERENR_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMUSERENR_EL0_SHIFT) 799 #define HDFGWTR_EL2_PMUSERENR_EL0_VAL(x) ((x) & HDFGWTR_EL2_PMUSERENR_EL0_MASK) 800 #define HDFGWTR_EL2_PMUSERENR_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMUSERENR_EL0_SHIFT) 801 #define HDFGWTR_EL2_PMUSERENR_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMUSERENR_EL0_SHIFT) 802 #define HDFGWTR_EL2_TRBTRG_EL1_SHIFT 56 803 #define HDFGWTR_EL2_TRBTRG_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRBTRG_EL1_SHIFT) 804 #define HDFGWTR_EL2_TRBTRG_EL1_VAL(x) ((x) & HDFGWTR_EL2_TRBTRG_EL1_MASK) 805 #define HDFGWTR_EL2_TRBTRG_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRBTRG_EL1_SHIFT) 806 #define HDFGWTR_EL2_TRBTRG_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRBTRG_EL1_SHIFT) 807 #define HDFGWTR_EL2_TRBSR_EL1_SHIFT 55 808 #define HDFGWTR_EL2_TRBSR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRBSR_EL1_SHIFT) 809 #define HDFGWTR_EL2_TRBSR_EL1_VAL(x) ((x) & HDFGWTR_EL2_TRBSR_EL1_MASK) 810 #define HDFGWTR_EL2_TRBSR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRBSR_EL1_SHIFT) 811 #define HDFGWTR_EL2_TRBSR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRBSR_EL1_SHIFT) 812 #define HDFGWTR_EL2_TRBPTR_EL1_SHIFT 54 813 #define HDFGWTR_EL2_TRBPTR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRBPTR_EL1_SHIFT) 814 #define HDFGWTR_EL2_TRBPTR_EL1_VAL(x) ((x) & HDFGWTR_EL2_TRBPTR_EL1_MASK) 815 #define HDFGWTR_EL2_TRBPTR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRBPTR_EL1_SHIFT) 816 #define HDFGWTR_EL2_TRBPTR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRBPTR_EL1_SHIFT) 817 #define HDFGWTR_EL2_TRBMAR_EL1_SHIFT 53 818 #define HDFGWTR_EL2_TRBMAR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRBMAR_EL1_SHIFT) 819 #define HDFGWTR_EL2_TRBMAR_EL1_VAL(x) ((x) & HDFGWTR_EL2_TRBMAR_EL1_MASK) 820 #define HDFGWTR_EL2_TRBMAR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRBMAR_EL1_SHIFT) 821 #define HDFGWTR_EL2_TRBMAR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRBMAR_EL1_SHIFT) 822 #define HDFGWTR_EL2_TRBLIMITR_EL1_SHIFT 52 823 #define HDFGWTR_EL2_TRBLIMITR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRBLIMITR_EL1_SHIFT) 824 #define HDFGWTR_EL2_TRBLIMITR_EL1_VAL(x) ((x) & HDFGWTR_EL2_TRBLIMITR_EL1_MASK) 825 #define HDFGWTR_EL2_TRBLIMITR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRBLIMITR_EL1_SHIFT) 826 #define HDFGWTR_EL2_TRBLIMITR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRBLIMITR_EL1_SHIFT) 827 #define HDFGWTR_EL2_TRBBASER_EL1_SHIFT 50 828 #define HDFGWTR_EL2_TRBBASER_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRBBASER_EL1_SHIFT) 829 #define HDFGWTR_EL2_TRBBASER_EL1_VAL(x) ((x) & HDFGWTR_EL2_TRBBASER_EL1_MASK) 830 #define HDFGWTR_EL2_TRBBASER_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRBBASER_EL1_SHIFT) 831 #define HDFGWTR_EL2_TRBBASER_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRBBASER_EL1_SHIFT) 832 #define HDFGWTR_EL2_TRFCR_EL1_SHIFT 49 833 #define HDFGWTR_EL2_TRFCR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRFCR_EL1_SHIFT) 834 #define HDFGWTR_EL2_TRFCR_EL1_VAL(x) ((x) & HDFGWTR_EL2_TRFCR_EL1_MASK) 835 #define HDFGWTR_EL2_TRFCR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRFCR_EL1_SHIFT) 836 #define HDFGWTR_EL2_TRFCR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRFCR_EL1_SHIFT) 837 #define HDFGWTR_EL2_TRCVICTLR_SHIFT 48 838 #define HDFGWTR_EL2_TRCVICTLR_MASK (UL(0x1) << HDFGWTR_EL2_TRCVICTLR_SHIFT) 839 #define HDFGWTR_EL2_TRCVICTLR_VAL(x) ((x) & HDFGWTR_EL2_TRCVICTLR_MASK) 840 #define HDFGWTR_EL2_TRCVICTLR_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCVICTLR_SHIFT) 841 #define HDFGWTR_EL2_TRCVICTLR_TRAP (UL(0x1) << HDFGWTR_EL2_TRCVICTLR_SHIFT) 842 #define HDFGWTR_EL2_TRCSSCSRn_SHIFT 46 843 #define HDFGWTR_EL2_TRCSSCSRn_MASK (UL(0x1) << HDFGWTR_EL2_TRCSSCSRn_SHIFT) 844 #define HDFGWTR_EL2_TRCSSCSRn_VAL(x) ((x) & HDFGWTR_EL2_TRCSSCSRn_MASK) 845 #define HDFGWTR_EL2_TRCSSCSRn_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCSSCSRn_SHIFT) 846 #define HDFGWTR_EL2_TRCSSCSRn_TRAP (UL(0x1) << HDFGWTR_EL2_TRCSSCSRn_SHIFT) 847 #define HDFGWTR_EL2_TRCSEQSTR_SHIFT 45 848 #define HDFGWTR_EL2_TRCSEQSTR_MASK (UL(0x1) << HDFGWTR_EL2_TRCSEQSTR_SHIFT) 849 #define HDFGWTR_EL2_TRCSEQSTR_VAL(x) ((x) & HDFGWTR_EL2_TRCSEQSTR_MASK) 850 #define HDFGWTR_EL2_TRCSEQSTR_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCSEQSTR_SHIFT) 851 #define HDFGWTR_EL2_TRCSEQSTR_TRAP (UL(0x1) << HDFGWTR_EL2_TRCSEQSTR_SHIFT) 852 #define HDFGWTR_EL2_TRCPRGCTLR_SHIFT 44 853 #define HDFGWTR_EL2_TRCPRGCTLR_MASK (UL(0x1) << HDFGWTR_EL2_TRCPRGCTLR_SHIFT) 854 #define HDFGWTR_EL2_TRCPRGCTLR_VAL(x) ((x) & HDFGWTR_EL2_TRCPRGCTLR_MASK) 855 #define HDFGWTR_EL2_TRCPRGCTLR_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCPRGCTLR_SHIFT) 856 #define HDFGWTR_EL2_TRCPRGCTLR_TRAP (UL(0x1) << HDFGWTR_EL2_TRCPRGCTLR_SHIFT) 857 #define HDFGWTR_EL2_TRCOSLAR_SHIFT 42 858 #define HDFGWTR_EL2_TRCOSLAR_MASK (UL(0x1) << HDFGWTR_EL2_TRCOSLAR_SHIFT) 859 #define HDFGWTR_EL2_TRCOSLAR_VAL(x) ((x) & HDFGWTR_EL2_TRCOSLAR_MASK) 860 #define HDFGWTR_EL2_TRCOSLAR_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCOSLAR_SHIFT) 861 #define HDFGWTR_EL2_TRCOSLAR_TRAP (UL(0x1) << HDFGWTR_EL2_TRCOSLAR_SHIFT) 862 #define HDFGWTR_EL2_TRCIMSPECn_SHIFT 41 863 #define HDFGWTR_EL2_TRCIMSPECn_MASK (UL(0x1) << HDFGWTR_EL2_TRCIMSPECn_SHIFT) 864 #define HDFGWTR_EL2_TRCIMSPECn_VAL(x) ((x) & HDFGWTR_EL2_TRCIMSPECn_MASK) 865 #define HDFGWTR_EL2_TRCIMSPECn_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCIMSPECn_SHIFT) 866 #define HDFGWTR_EL2_TRCIMSPECn_TRAP (UL(0x1) << HDFGWTR_EL2_TRCIMSPECn_SHIFT) 867 #define HDFGWTR_EL2_TRCCNTVRn_SHIFT 37 868 #define HDFGWTR_EL2_TRCCNTVRn_MASK (UL(0x1) << HDFGWTR_EL2_TRCCNTVRn_SHIFT) 869 #define HDFGWTR_EL2_TRCCNTVRn_VAL(x) ((x) & HDFGWTR_EL2_TRCCNTVRn_MASK) 870 #define HDFGWTR_EL2_TRCCNTVRn_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCCNTVRn_SHIFT) 871 #define HDFGWTR_EL2_TRCCNTVRn_TRAP (UL(0x1) << HDFGWTR_EL2_TRCCNTVRn_SHIFT) 872 #define HDFGWTR_EL2_TRCCLAIM_SHIFT 36 873 #define HDFGWTR_EL2_TRCCLAIM_MASK (UL(0x1) << HDFGWTR_EL2_TRCCLAIM_SHIFT) 874 #define HDFGWTR_EL2_TRCCLAIM_VAL(x) ((x) & HDFGWTR_EL2_TRCCLAIM_MASK) 875 #define HDFGWTR_EL2_TRCCLAIM_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCCLAIM_SHIFT) 876 #define HDFGWTR_EL2_TRCCLAIM_TRAP (UL(0x1) << HDFGWTR_EL2_TRCCLAIM_SHIFT) 877 #define HDFGWTR_EL2_TRCAUXCTLR_SHIFT 35 878 #define HDFGWTR_EL2_TRCAUXCTLR_MASK (UL(0x1) << HDFGWTR_EL2_TRCAUXCTLR_SHIFT) 879 #define HDFGWTR_EL2_TRCAUXCTLR_VAL(x) ((x) & HDFGWTR_EL2_TRCAUXCTLR_MASK) 880 #define HDFGWTR_EL2_TRCAUXCTLR_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCAUXCTLR_SHIFT) 881 #define HDFGWTR_EL2_TRCAUXCTLR_TRAP (UL(0x1) << HDFGWTR_EL2_TRCAUXCTLR_SHIFT) 882 #define HDFGWTR_EL2_TRC_SHIFT 33 883 #define HDFGWTR_EL2_TRC_MASK (UL(0x1) << HDFGWTR_EL2_TRC_SHIFT) 884 #define HDFGWTR_EL2_TRC_VAL(x) ((x) & HDFGWTR_EL2_TRC_MASK) 885 #define HDFGWTR_EL2_TRC_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRC_SHIFT) 886 #define HDFGWTR_EL2_TRC_TRAP (UL(0x1) << HDFGWTR_EL2_TRC_SHIFT) 887 #define HDFGWTR_EL2_PMSLATFR_EL1_SHIFT 32 888 #define HDFGWTR_EL2_PMSLATFR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMSLATFR_EL1_SHIFT) 889 #define HDFGWTR_EL2_PMSLATFR_EL1_VAL(x) ((x) & HDFGWTR_EL2_PMSLATFR_EL1_MASK) 890 #define HDFGWTR_EL2_PMSLATFR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSLATFR_EL1_SHIFT) 891 #define HDFGWTR_EL2_PMSLATFR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMSLATFR_EL1_SHIFT) 892 #define HDFGWTR_EL2_PMSIRR_EL1_SHIFT 31 893 #define HDFGWTR_EL2_PMSIRR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMSIRR_EL1_SHIFT) 894 #define HDFGWTR_EL2_PMSIRR_EL1_VAL(x) ((x) & HDFGWTR_EL2_PMSIRR_EL1_MASK) 895 #define HDFGWTR_EL2_PMSIRR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSIRR_EL1_SHIFT) 896 #define HDFGWTR_EL2_PMSIRR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMSIRR_EL1_SHIFT) 897 #define HDFGWTR_EL2_PMSICR_EL1_SHIFT 29 898 #define HDFGWTR_EL2_PMSICR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMSICR_EL1_SHIFT) 899 #define HDFGWTR_EL2_PMSICR_EL1_VAL(x) ((x) & HDFGWTR_EL2_PMSICR_EL1_MASK) 900 #define HDFGWTR_EL2_PMSICR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSICR_EL1_SHIFT) 901 #define HDFGWTR_EL2_PMSICR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMSICR_EL1_SHIFT) 902 #define HDFGWTR_EL2_PMSFCR_EL1_SHIFT 28 903 #define HDFGWTR_EL2_PMSFCR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMSFCR_EL1_SHIFT) 904 #define HDFGWTR_EL2_PMSFCR_EL1_VAL(x) ((x) & HDFGWTR_EL2_PMSFCR_EL1_MASK) 905 #define HDFGWTR_EL2_PMSFCR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSFCR_EL1_SHIFT) 906 #define HDFGWTR_EL2_PMSFCR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMSFCR_EL1_SHIFT) 907 #define HDFGWTR_EL2_PMSEVFR_EL1_SHIFT 27 908 #define HDFGWTR_EL2_PMSEVFR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMSEVFR_EL1_SHIFT) 909 #define HDFGWTR_EL2_PMSEVFR_EL1_VAL(x) ((x) & HDFGWTR_EL2_PMSEVFR_EL1_MASK) 910 #define HDFGWTR_EL2_PMSEVFR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSEVFR_EL1_SHIFT) 911 #define HDFGWTR_EL2_PMSEVFR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMSEVFR_EL1_SHIFT) 912 #define HDFGWTR_EL2_PMSCR_EL1_SHIFT 26 913 #define HDFGWTR_EL2_PMSCR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMSCR_EL1_SHIFT) 914 #define HDFGWTR_EL2_PMSCR_EL1_VAL(x) ((x) & HDFGWTR_EL2_PMSCR_EL1_MASK) 915 #define HDFGWTR_EL2_PMSCR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSCR_EL1_SHIFT) 916 #define HDFGWTR_EL2_PMSCR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMSCR_EL1_SHIFT) 917 #define HDFGWTR_EL2_PMBSR_EL1_SHIFT 25 918 #define HDFGWTR_EL2_PMBSR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMBSR_EL1_SHIFT) 919 #define HDFGWTR_EL2_PMBSR_EL1_VAL(x) ((x) & HDFGWTR_EL2_PMBSR_EL1_MASK) 920 #define HDFGWTR_EL2_PMBSR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMBSR_EL1_SHIFT) 921 #define HDFGWTR_EL2_PMBSR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMBSR_EL1_SHIFT) 922 #define HDFGWTR_EL2_PMBPTR_EL1_SHIFT 24 923 #define HDFGWTR_EL2_PMBPTR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMBPTR_EL1_SHIFT) 924 #define HDFGWTR_EL2_PMBPTR_EL1_VAL(x) ((x) & HDFGWTR_EL2_PMBPTR_EL1_MASK) 925 #define HDFGWTR_EL2_PMBPTR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMBPTR_EL1_SHIFT) 926 #define HDFGWTR_EL2_PMBPTR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMBPTR_EL1_SHIFT) 927 #define HDFGWTR_EL2_PMBLIMITR_EL1_SHIFT 23 928 #define HDFGWTR_EL2_PMBLIMITR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMBLIMITR_EL1_SHIFT) 929 #define HDFGWTR_EL2_PMBLIMITR_EL1_VAL(x) ((x) & HDFGWTR_EL2_PMBLIMITR_EL1_MASK) 930 #define HDFGWTR_EL2_PMBLIMITR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMBLIMITR_EL1_SHIFT) 931 #define HDFGWTR_EL2_PMBLIMITR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMBLIMITR_EL1_SHIFT) 932 #define HDFGWTR_EL2_PMCR_EL0_SHIFT 21 933 #define HDFGWTR_EL2_PMCR_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMCR_EL0_SHIFT) 934 #define HDFGWTR_EL2_PMCR_EL0_VAL(x) ((x) & HDFGWTR_EL2_PMCR_EL0_MASK) 935 #define HDFGWTR_EL2_PMCR_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMCR_EL0_SHIFT) 936 #define HDFGWTR_EL2_PMCR_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMCR_EL0_SHIFT) 937 #define HDFGWTR_EL2_PMSWINC_EL0_SHIFT 20 938 #define HDFGWTR_EL2_PMSWINC_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMSWINC_EL0_SHIFT) 939 #define HDFGWTR_EL2_PMSWINC_EL0_VAL(x) ((x) & HDFGWTR_EL2_PMSWINC_EL0_MASK) 940 #define HDFGWTR_EL2_PMSWINC_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSWINC_EL0_SHIFT) 941 #define HDFGWTR_EL2_PMSWINC_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMSWINC_EL0_SHIFT) 942 #define HDFGWTR_EL2_PMSELR_EL0_SHIFT 19 943 #define HDFGWTR_EL2_PMSELR_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMSELR_EL0_SHIFT) 944 #define HDFGWTR_EL2_PMSELR_EL0_VAL(x) ((x) & HDFGWTR_EL2_PMSELR_EL0_MASK) 945 #define HDFGWTR_EL2_PMSELR_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSELR_EL0_SHIFT) 946 #define HDFGWTR_EL2_PMSELR_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMSELR_EL0_SHIFT) 947 #define HDFGWTR_EL2_PMOVS_SHIFT 18 948 #define HDFGWTR_EL2_PMOVS_MASK (UL(0x1) << HDFGWTR_EL2_PMOVS_SHIFT) 949 #define HDFGWTR_EL2_PMOVS_VAL(x) ((x) & HDFGWTR_EL2_PMOVS_MASK) 950 #define HDFGWTR_EL2_PMOVS_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMOVS_SHIFT) 951 #define HDFGWTR_EL2_PMOVS_TRAP (UL(0x1) << HDFGWTR_EL2_PMOVS_SHIFT) 952 #define HDFGWTR_EL2_PMINTEN_SHIFT 17 953 #define HDFGWTR_EL2_PMINTEN_MASK (UL(0x1) << HDFGWTR_EL2_PMINTEN_SHIFT) 954 #define HDFGWTR_EL2_PMINTEN_VAL(x) ((x) & HDFGWTR_EL2_PMINTEN_MASK) 955 #define HDFGWTR_EL2_PMINTEN_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMINTEN_SHIFT) 956 #define HDFGWTR_EL2_PMINTEN_TRAP (UL(0x1) << HDFGWTR_EL2_PMINTEN_SHIFT) 957 #define HDFGWTR_EL2_PMCNTEN_SHIFT 16 958 #define HDFGWTR_EL2_PMCNTEN_MASK (UL(0x1) << HDFGWTR_EL2_PMCNTEN_SHIFT) 959 #define HDFGWTR_EL2_PMCNTEN_VAL(x) ((x) & HDFGWTR_EL2_PMCNTEN_MASK) 960 #define HDFGWTR_EL2_PMCNTEN_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMCNTEN_SHIFT) 961 #define HDFGWTR_EL2_PMCNTEN_TRAP (UL(0x1) << HDFGWTR_EL2_PMCNTEN_SHIFT) 962 #define HDFGWTR_EL2_PMCCNTR_EL0_SHIFT 15 963 #define HDFGWTR_EL2_PMCCNTR_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMCCNTR_EL0_SHIFT) 964 #define HDFGWTR_EL2_PMCCNTR_EL0_VAL(x) ((x) & HDFGWTR_EL2_PMCCNTR_EL0_MASK) 965 #define HDFGWTR_EL2_PMCCNTR_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMCCNTR_EL0_SHIFT) 966 #define HDFGWTR_EL2_PMCCNTR_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMCCNTR_EL0_SHIFT) 967 #define HDFGWTR_EL2_PMCCFILTR_EL0_SHIFT 14 968 #define HDFGWTR_EL2_PMCCFILTR_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMCCFILTR_EL0_SHIFT) 969 #define HDFGWTR_EL2_PMCCFILTR_EL0_VAL(x) ((x) & HDFGWTR_EL2_PMCCFILTR_EL0_MASK) 970 #define HDFGWTR_EL2_PMCCFILTR_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMCCFILTR_EL0_SHIFT) 971 #define HDFGWTR_EL2_PMCCFILTR_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMCCFILTR_EL0_SHIFT) 972 #define HDFGWTR_EL2_PMEVTYPERn_EL0_SHIFT 13 973 #define HDFGWTR_EL2_PMEVTYPERn_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMEVTYPERn_EL0_SHIFT) 974 #define HDFGWTR_EL2_PMEVTYPERn_EL0_VAL(x) ((x) & HDFGWTR_EL2_PMEVTYPERn_EL0_MASK) 975 #define HDFGWTR_EL2_PMEVTYPERn_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMEVTYPERn_EL0_SHIFT) 976 #define HDFGWTR_EL2_PMEVTYPERn_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMEVTYPERn_EL0_SHIFT) 977 #define HDFGWTR_EL2_PMEVCNTRn_EL0_SHIFT 12 978 #define HDFGWTR_EL2_PMEVCNTRn_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMEVCNTRn_EL0_SHIFT) 979 #define HDFGWTR_EL2_PMEVCNTRn_EL0_VAL(x) ((x) & HDFGWTR_EL2_PMEVCNTRn_EL0_MASK) 980 #define HDFGWTR_EL2_PMEVCNTRn_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMEVCNTRn_EL0_SHIFT) 981 #define HDFGWTR_EL2_PMEVCNTRn_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMEVCNTRn_EL0_SHIFT) 982 #define HDFGWTR_EL2_OSDLR_EL1_SHIFT 11 983 #define HDFGWTR_EL2_OSDLR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_OSDLR_EL1_SHIFT) 984 #define HDFGWTR_EL2_OSDLR_EL1_VAL(x) ((x) & HDFGWTR_EL2_OSDLR_EL1_MASK) 985 #define HDFGWTR_EL2_OSDLR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_OSDLR_EL1_SHIFT) 986 #define HDFGWTR_EL2_OSDLR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_OSDLR_EL1_SHIFT) 987 #define HDFGWTR_EL2_OSECCR_EL1_SHIFT 10 988 #define HDFGWTR_EL2_OSECCR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_OSECCR_EL1_SHIFT) 989 #define HDFGWTR_EL2_OSECCR_EL1_VAL(x) ((x) & HDFGWTR_EL2_OSECCR_EL1_MASK) 990 #define HDFGWTR_EL2_OSECCR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_OSECCR_EL1_SHIFT) 991 #define HDFGWTR_EL2_OSECCR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_OSECCR_EL1_SHIFT) 992 #define HDFGWTR_EL2_OSLAR_EL1_SHIFT 8 993 #define HDFGWTR_EL2_OSLAR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_OSLAR_EL1_SHIFT) 994 #define HDFGWTR_EL2_OSLAR_EL1_VAL(x) ((x) & HDFGWTR_EL2_OSLAR_EL1_MASK) 995 #define HDFGWTR_EL2_OSLAR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_OSLAR_EL1_SHIFT) 996 #define HDFGWTR_EL2_OSLAR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_OSLAR_EL1_SHIFT) 997 #define HDFGWTR_EL2_DBGPRCR_EL1_SHIFT 7 998 #define HDFGWTR_EL2_DBGPRCR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_DBGPRCR_EL1_SHIFT) 999 #define HDFGWTR_EL2_DBGPRCR_EL1_VAL(x) ((x) & HDFGWTR_EL2_DBGPRCR_EL1_MASK) 1000 #define HDFGWTR_EL2_DBGPRCR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_DBGPRCR_EL1_SHIFT) 1001 #define HDFGWTR_EL2_DBGPRCR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_DBGPRCR_EL1_SHIFT) 1002 #define HDFGWTR_EL2_DBGCLAIM_SHIFT 5 1003 #define HDFGWTR_EL2_DBGCLAIM_MASK (UL(0x1) << HDFGWTR_EL2_DBGCLAIM_SHIFT) 1004 #define HDFGWTR_EL2_DBGCLAIM_VAL(x) ((x) & HDFGWTR_EL2_DBGCLAIM_MASK) 1005 #define HDFGWTR_EL2_DBGCLAIM_NOTRAP (UL(0x0) << HDFGWTR_EL2_DBGCLAIM_SHIFT) 1006 #define HDFGWTR_EL2_DBGCLAIM_TRAP (UL(0x1) << HDFGWTR_EL2_DBGCLAIM_SHIFT) 1007 #define HDFGWTR_EL2_MDSCR_EL1_SHIFT 4 1008 #define HDFGWTR_EL2_MDSCR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_MDSCR_EL1_SHIFT) 1009 #define HDFGWTR_EL2_MDSCR_EL1_VAL(x) ((x) & HDFGWTR_EL2_MDSCR_EL1_MASK) 1010 #define HDFGWTR_EL2_MDSCR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_MDSCR_EL1_SHIFT) 1011 #define HDFGWTR_EL2_MDSCR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_MDSCR_EL1_SHIFT) 1012 #define HDFGWTR_EL2_DBGWVRn_EL1_SHIFT 3 1013 #define HDFGWTR_EL2_DBGWVRn_EL1_MASK (UL(0x1) << HDFGWTR_EL2_DBGWVRn_EL1_SHIFT) 1014 #define HDFGWTR_EL2_DBGWVRn_EL1_VAL(x) ((x) & HDFGWTR_EL2_DBGWVRn_EL1_MASK) 1015 #define HDFGWTR_EL2_DBGWVRn_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_DBGWVRn_EL1_SHIFT) 1016 #define HDFGWTR_EL2_DBGWVRn_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_DBGWVRn_EL1_SHIFT) 1017 #define HDFGWTR_EL2_DBGWCRn_EL1_SHIFT 2 1018 #define HDFGWTR_EL2_DBGWCRn_EL1_MASK (UL(0x1) << HDFGWTR_EL2_DBGWCRn_EL1_SHIFT) 1019 #define HDFGWTR_EL2_DBGWCRn_EL1_VAL(x) ((x) & HDFGWTR_EL2_DBGWCRn_EL1_MASK) 1020 #define HDFGWTR_EL2_DBGWCRn_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_DBGWCRn_EL1_SHIFT) 1021 #define HDFGWTR_EL2_DBGWCRn_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_DBGWCRn_EL1_SHIFT) 1022 #define HDFGWTR_EL2_DBGBVRn_EL1_SHIFT 1 1023 #define HDFGWTR_EL2_DBGBVRn_EL1_MASK (UL(0x1) << HDFGWTR_EL2_DBGBVRn_EL1_SHIFT) 1024 #define HDFGWTR_EL2_DBGBVRn_EL1_VAL(x) ((x) & HDFGWTR_EL2_DBGBVRn_EL1_MASK) 1025 #define HDFGWTR_EL2_DBGBVRn_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_DBGBVRn_EL1_SHIFT) 1026 #define HDFGWTR_EL2_DBGBVRn_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_DBGBVRn_EL1_SHIFT) 1027 #define HDFGWTR_EL2_DBGBCRn_EL1_SHIFT 0 1028 #define HDFGWTR_EL2_DBGBCRn_EL1_MASK (UL(0x1) << HDFGWTR_EL2_DBGBCRn_EL1_SHIFT) 1029 #define HDFGWTR_EL2_DBGBCRn_EL1_VAL(x) ((x) & HDFGWTR_EL2_DBGBCRn_EL1_MASK) 1030 #define HDFGWTR_EL2_DBGBCRn_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_DBGBCRn_EL1_SHIFT) 1031 #define HDFGWTR_EL2_DBGBCRn_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_DBGBCRn_EL1_SHIFT) 1032 1033 /* HFGITR2_EL2 */ 1034 #define HFGITR2_EL2_REG MRS_REG_ALT_NAME(HFGITR2_EL2) 1035 #define HFGITR2_EL2_op0 3 1036 #define HFGITR2_EL2_op1 4 1037 #define HFGITR2_EL2_CRn 3 1038 #define HFGITR2_EL2_CRm 1 1039 #define HFGITR2_EL2_op2 7 1040 1041 /* HFGITR_EL2 */ 1042 #define HFGITR_EL2_REG MRS_REG_ALT_NAME(HFGITR_EL2) 1043 #define HFGITR_EL2_op0 3 1044 #define HFGITR_EL2_op1 4 1045 #define HFGITR_EL2_CRn 1 1046 #define HFGITR_EL2_CRm 1 1047 #define HFGITR_EL2_op2 6 1048 #define HFGITR_EL2_ATS1E1A_SHIFT 62 1049 #define HFGITR_EL2_ATS1E1A_MASK (UL(0x1) << HFGITR_EL2_ATS1E1A_SHIFT) 1050 #define HFGITR_EL2_ATS1E1A_VAL(x) ((x) & HFGITR_EL2_ATS1E1A_MASK) 1051 #define HFGITR_EL2_ATS1E1A_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E1A_SHIFT) 1052 #define HFGITR_EL2_ATS1E1A_TRAP (UL(0x1) << HFGITR_EL2_ATS1E1A_SHIFT) 1053 #define HFGITR_EL2_COSPRCTX_SHIFT 60 1054 #define HFGITR_EL2_COSPRCTX_MASK (UL(0x1) << HFGITR_EL2_COSPRCTX_SHIFT) 1055 #define HFGITR_EL2_COSPRCTX_VAL(x) ((x) & HFGITR_EL2_COSPRCTX_MASK) 1056 #define HFGITR_EL2_COSPRCTX_NOTRAP (UL(0x0) << HFGITR_EL2_COSPRCTX_SHIFT) 1057 #define HFGITR_EL2_COSPRCTX_TRAP (UL(0x1) << HFGITR_EL2_COSPRCTX_SHIFT) 1058 #define HFGITR_EL2_nGCSEPP_SHIFT 59 1059 #define HFGITR_EL2_nGCSEPP_MASK (UL(0x1) << HFGITR_EL2_nGCSEPP_SHIFT) 1060 #define HFGITR_EL2_nGCSEPP_VAL(x) ((x) & HFGITR_EL2_nGCSEPP_MASK) 1061 #define HFGITR_EL2_nGCSEPP_TRAP (UL(0x0) << HFGITR_EL2_nGCSEPP_SHIFT) 1062 #define HFGITR_EL2_nGCSEPP_NOTRAP (UL(0x1) << HFGITR_EL2_nGCSEPP_SHIFT) 1063 #define HFGITR_EL2_nGCSSTR_EL1_SHIFT 58 1064 #define HFGITR_EL2_nGCSSTR_EL1_MASK (UL(0x1) << HFGITR_EL2_nGCSSTR_EL1_SHIFT) 1065 #define HFGITR_EL2_nGCSSTR_EL1_VAL(x) ((x) & HFGITR_EL2_nGCSSTR_EL1_MASK) 1066 #define HFGITR_EL2_nGCSSTR_EL1_TRAP (UL(0x0) << HFGITR_EL2_nGCSSTR_EL1_SHIFT) 1067 #define HFGITR_EL2_nGCSSTR_EL1_NOTRAP (UL(0x1) << HFGITR_EL2_nGCSSTR_EL1_SHIFT) 1068 #define HFGITR_EL2_nGCSPUSHM_EL1_SHIFT 57 1069 #define HFGITR_EL2_nGCSPUSHM_EL1_MASK (UL(0x1) << HFGITR_EL2_nGCSPUSHM_EL1_SHIFT) 1070 #define HFGITR_EL2_nGCSPUSHM_EL1_VAL(x) ((x) & HFGITR_EL2_nGCSPUSHM_EL1_MASK) 1071 #define HFGITR_EL2_nGCSPUSHM_EL1_TRAP (UL(0x0) << HFGITR_EL2_nGCSPUSHM_EL1_SHIFT) 1072 #define HFGITR_EL2_nGCSPUSHM_EL1_NOTRAP (UL(0x1) << HFGITR_EL2_nGCSPUSHM_EL1_SHIFT) 1073 #define HFGITR_EL2_nBRBIALL_SHIFT 56 1074 #define HFGITR_EL2_nBRBIALL_MASK (UL(0x1) << HFGITR_EL2_nBRBIALL_SHIFT) 1075 #define HFGITR_EL2_nBRBIALL_VAL(x) ((x) & HFGITR_EL2_nBRBIALL_MASK) 1076 #define HFGITR_EL2_nBRBIALL_TRAP (UL(0x0) << HFGITR_EL2_nBRBIALL_SHIFT) 1077 #define HFGITR_EL2_nBRBIALL_NOTRAP (UL(0x1) << HFGITR_EL2_nBRBIALL_SHIFT) 1078 #define HFGITR_EL2_nBRBINJ_SHIFT 55 1079 #define HFGITR_EL2_nBRBINJ_MASK (UL(0x1) << HFGITR_EL2_nBRBINJ_SHIFT) 1080 #define HFGITR_EL2_nBRBINJ_VAL(x) ((x) & HFGITR_EL2_nBRBINJ_MASK) 1081 #define HFGITR_EL2_nBRBINJ_TRAP (UL(0x0) << HFGITR_EL2_nBRBINJ_SHIFT) 1082 #define HFGITR_EL2_nBRBINJ_NOTRAP (UL(0x1) << HFGITR_EL2_nBRBINJ_SHIFT) 1083 #define HFGITR_EL2_DCCVAC_SHIFT 54 1084 #define HFGITR_EL2_DCCVAC_MASK (UL(0x1) << HFGITR_EL2_DCCVAC_SHIFT) 1085 #define HFGITR_EL2_DCCVAC_VAL(x) ((x) & HFGITR_EL2_DCCVAC_MASK) 1086 #define HFGITR_EL2_DCCVAC_NOTRAP (UL(0x0) << HFGITR_EL2_DCCVAC_SHIFT) 1087 #define HFGITR_EL2_DCCVAC_TRAP (UL(0x1) << HFGITR_EL2_DCCVAC_SHIFT) 1088 #define HFGITR_EL2_SVC_EL1_SHIFT 53 1089 #define HFGITR_EL2_SVC_EL1_MASK (UL(0x1) << HFGITR_EL2_SVC_EL1_SHIFT) 1090 #define HFGITR_EL2_SVC_EL1_VAL(x) ((x) & HFGITR_EL2_SVC_EL1_MASK) 1091 #define HFGITR_EL2_SVC_EL1_NOTRAP (UL(0x0) << HFGITR_EL2_SVC_EL1_SHIFT) 1092 #define HFGITR_EL2_SVC_EL1_TRAP (UL(0x1) << HFGITR_EL2_SVC_EL1_SHIFT) 1093 #define HFGITR_EL2_SVC_EL0_SHIFT 52 1094 #define HFGITR_EL2_SVC_EL0_MASK (UL(0x1) << HFGITR_EL2_SVC_EL0_SHIFT) 1095 #define HFGITR_EL2_SVC_EL0_VAL(x) ((x) & HFGITR_EL2_SVC_EL0_MASK) 1096 #define HFGITR_EL2_SVC_EL0_NOTRAP (UL(0x0) << HFGITR_EL2_SVC_EL0_SHIFT) 1097 #define HFGITR_EL2_SVC_EL0_TRAP (UL(0x1) << HFGITR_EL2_SVC_EL0_SHIFT) 1098 #define HFGITR_EL2_ERET_SHIFT 51 1099 #define HFGITR_EL2_ERET_MASK (UL(0x1) << HFGITR_EL2_ERET_SHIFT) 1100 #define HFGITR_EL2_ERET_VAL(x) ((x) & HFGITR_EL2_ERET_MASK) 1101 #define HFGITR_EL2_ERET_NOTRAP (UL(0x0) << HFGITR_EL2_ERET_SHIFT) 1102 #define HFGITR_EL2_ERET_TRAP (UL(0x1) << HFGITR_EL2_ERET_SHIFT) 1103 #define HFGITR_EL2_CPPRCTX_SHIFT 50 1104 #define HFGITR_EL2_CPPRCTX_MASK (UL(0x1) << HFGITR_EL2_CPPRCTX_SHIFT) 1105 #define HFGITR_EL2_CPPRCTX_VAL(x) ((x) & HFGITR_EL2_CPPRCTX_MASK) 1106 #define HFGITR_EL2_CPPRCTX_NOTRAP (UL(0x0) << HFGITR_EL2_CPPRCTX_SHIFT) 1107 #define HFGITR_EL2_CPPRCTX_TRAP (UL(0x1) << HFGITR_EL2_CPPRCTX_SHIFT) 1108 #define HFGITR_EL2_DVPRCTX_SHIFT 49 1109 #define HFGITR_EL2_DVPRCTX_MASK (UL(0x1) << HFGITR_EL2_DVPRCTX_SHIFT) 1110 #define HFGITR_EL2_DVPRCTX_VAL(x) ((x) & HFGITR_EL2_DVPRCTX_MASK) 1111 #define HFGITR_EL2_DVPRCTX_NOTRAP (UL(0x0) << HFGITR_EL2_DVPRCTX_SHIFT) 1112 #define HFGITR_EL2_DVPRCTX_TRAP (UL(0x1) << HFGITR_EL2_DVPRCTX_SHIFT) 1113 #define HFGITR_EL2_CFPRCTX_SHIFT 48 1114 #define HFGITR_EL2_CFPRCTX_MASK (UL(0x1) << HFGITR_EL2_CFPRCTX_SHIFT) 1115 #define HFGITR_EL2_CFPRCTX_VAL(x) ((x) & HFGITR_EL2_CFPRCTX_MASK) 1116 #define HFGITR_EL2_CFPRCTX_NOTRAP (UL(0x0) << HFGITR_EL2_CFPRCTX_SHIFT) 1117 #define HFGITR_EL2_CFPRCTX_TRAP (UL(0x1) << HFGITR_EL2_CFPRCTX_SHIFT) 1118 #define HFGITR_EL2_TLBIVAALE1_SHIFT 47 1119 #define HFGITR_EL2_TLBIVAALE1_MASK (UL(0x1) << HFGITR_EL2_TLBIVAALE1_SHIFT) 1120 #define HFGITR_EL2_TLBIVAALE1_VAL(x) ((x) & HFGITR_EL2_TLBIVAALE1_MASK) 1121 #define HFGITR_EL2_TLBIVAALE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAALE1_SHIFT) 1122 #define HFGITR_EL2_TLBIVAALE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAALE1_SHIFT) 1123 #define HFGITR_EL2_TLBIVALE1_SHIFT 46 1124 #define HFGITR_EL2_TLBIVALE1_MASK (UL(0x1) << HFGITR_EL2_TLBIVALE1_SHIFT) 1125 #define HFGITR_EL2_TLBIVALE1_VAL(x) ((x) & HFGITR_EL2_TLBIVALE1_MASK) 1126 #define HFGITR_EL2_TLBIVALE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVALE1_SHIFT) 1127 #define HFGITR_EL2_TLBIVALE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIVALE1_SHIFT) 1128 #define HFGITR_EL2_TLBIVAAE1_SHIFT 45 1129 #define HFGITR_EL2_TLBIVAAE1_MASK (UL(0x1) << HFGITR_EL2_TLBIVAAE1_SHIFT) 1130 #define HFGITR_EL2_TLBIVAAE1_VAL(x) ((x) & HFGITR_EL2_TLBIVAAE1_MASK) 1131 #define HFGITR_EL2_TLBIVAAE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAAE1_SHIFT) 1132 #define HFGITR_EL2_TLBIVAAE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAAE1_SHIFT) 1133 #define HFGITR_EL2_TLBIASIDE1_SHIFT 44 1134 #define HFGITR_EL2_TLBIASIDE1_MASK (UL(0x1) << HFGITR_EL2_TLBIASIDE1_SHIFT) 1135 #define HFGITR_EL2_TLBIASIDE1_VAL(x) ((x) & HFGITR_EL2_TLBIASIDE1_MASK) 1136 #define HFGITR_EL2_TLBIASIDE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIASIDE1_SHIFT) 1137 #define HFGITR_EL2_TLBIASIDE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIASIDE1_SHIFT) 1138 #define HFGITR_EL2_TLBIVAE1_SHIFT 43 1139 #define HFGITR_EL2_TLBIVAE1_MASK (UL(0x1) << HFGITR_EL2_TLBIVAE1_SHIFT) 1140 #define HFGITR_EL2_TLBIVAE1_VAL(x) ((x) & HFGITR_EL2_TLBIVAE1_MASK) 1141 #define HFGITR_EL2_TLBIVAE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAE1_SHIFT) 1142 #define HFGITR_EL2_TLBIVAE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAE1_SHIFT) 1143 #define HFGITR_EL2_TLBIVMALLE1_SHIFT 42 1144 #define HFGITR_EL2_TLBIVMALLE1_MASK (UL(0x1) << HFGITR_EL2_TLBIVMALLE1_SHIFT) 1145 #define HFGITR_EL2_TLBIVMALLE1_VAL(x) ((x) & HFGITR_EL2_TLBIVMALLE1_MASK) 1146 #define HFGITR_EL2_TLBIVMALLE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVMALLE1_SHIFT) 1147 #define HFGITR_EL2_TLBIVMALLE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIVMALLE1_SHIFT) 1148 #define HFGITR_EL2_TLBIRVAALE1_SHIFT 41 1149 #define HFGITR_EL2_TLBIRVAALE1_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAALE1_SHIFT) 1150 #define HFGITR_EL2_TLBIRVAALE1_VAL(x) ((x) & HFGITR_EL2_TLBIRVAALE1_MASK) 1151 #define HFGITR_EL2_TLBIRVAALE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAALE1_SHIFT) 1152 #define HFGITR_EL2_TLBIRVAALE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAALE1_SHIFT) 1153 #define HFGITR_EL2_TLBIRVALE1_SHIFT 40 1154 #define HFGITR_EL2_TLBIRVALE1_MASK (UL(0x1) << HFGITR_EL2_TLBIRVALE1_SHIFT) 1155 #define HFGITR_EL2_TLBIRVALE1_VAL(x) ((x) & HFGITR_EL2_TLBIRVALE1_MASK) 1156 #define HFGITR_EL2_TLBIRVALE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVALE1_SHIFT) 1157 #define HFGITR_EL2_TLBIRVALE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVALE1_SHIFT) 1158 #define HFGITR_EL2_TLBIRVAAE1_SHIFT 39 1159 #define HFGITR_EL2_TLBIRVAAE1_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAAE1_SHIFT) 1160 #define HFGITR_EL2_TLBIRVAAE1_VAL(x) ((x) & HFGITR_EL2_TLBIRVAAE1_MASK) 1161 #define HFGITR_EL2_TLBIRVAAE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAAE1_SHIFT) 1162 #define HFGITR_EL2_TLBIRVAAE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAAE1_SHIFT) 1163 #define HFGITR_EL2_TLBIRVAE1_SHIFT 38 1164 #define HFGITR_EL2_TLBIRVAE1_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAE1_SHIFT) 1165 #define HFGITR_EL2_TLBIRVAE1_VAL(x) ((x) & HFGITR_EL2_TLBIRVAE1_MASK) 1166 #define HFGITR_EL2_TLBIRVAE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAE1_SHIFT) 1167 #define HFGITR_EL2_TLBIRVAE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAE1_SHIFT) 1168 #define HFGITR_EL2_TLBIRVAALE1IS_SHIFT 37 1169 #define HFGITR_EL2_TLBIRVAALE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAALE1IS_SHIFT) 1170 #define HFGITR_EL2_TLBIRVAALE1IS_VAL(x) ((x) & HFGITR_EL2_TLBIRVAALE1IS_MASK) 1171 #define HFGITR_EL2_TLBIRVAALE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAALE1IS_SHIFT) 1172 #define HFGITR_EL2_TLBIRVAALE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAALE1IS_SHIFT) 1173 #define HFGITR_EL2_TLBIRVALE1IS_SHIFT 36 1174 #define HFGITR_EL2_TLBIRVALE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVALE1IS_SHIFT) 1175 #define HFGITR_EL2_TLBIRVALE1IS_VAL(x) ((x) & HFGITR_EL2_TLBIRVALE1IS_MASK) 1176 #define HFGITR_EL2_TLBIRVALE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVALE1IS_SHIFT) 1177 #define HFGITR_EL2_TLBIRVALE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVALE1IS_SHIFT) 1178 #define HFGITR_EL2_TLBIRVAAE1IS_SHIFT 35 1179 #define HFGITR_EL2_TLBIRVAAE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAAE1IS_SHIFT) 1180 #define HFGITR_EL2_TLBIRVAAE1IS_VAL(x) ((x) & HFGITR_EL2_TLBIRVAAE1IS_MASK) 1181 #define HFGITR_EL2_TLBIRVAAE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAAE1IS_SHIFT) 1182 #define HFGITR_EL2_TLBIRVAAE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAAE1IS_SHIFT) 1183 #define HFGITR_EL2_TLBIRVAE1IS_SHIFT 34 1184 #define HFGITR_EL2_TLBIRVAE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAE1IS_SHIFT) 1185 #define HFGITR_EL2_TLBIRVAE1IS_VAL(x) ((x) & HFGITR_EL2_TLBIRVAE1IS_MASK) 1186 #define HFGITR_EL2_TLBIRVAE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAE1IS_SHIFT) 1187 #define HFGITR_EL2_TLBIRVAE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAE1IS_SHIFT) 1188 #define HFGITR_EL2_TLBIVAALE1IS_SHIFT 33 1189 #define HFGITR_EL2_TLBIVAALE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIVAALE1IS_SHIFT) 1190 #define HFGITR_EL2_TLBIVAALE1IS_VAL(x) ((x) & HFGITR_EL2_TLBIVAALE1IS_MASK) 1191 #define HFGITR_EL2_TLBIVAALE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAALE1IS_SHIFT) 1192 #define HFGITR_EL2_TLBIVAALE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAALE1IS_SHIFT) 1193 #define HFGITR_EL2_TLBIVALE1IS_SHIFT 32 1194 #define HFGITR_EL2_TLBIVALE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIVALE1IS_SHIFT) 1195 #define HFGITR_EL2_TLBIVALE1IS_VAL(x) ((x) & HFGITR_EL2_TLBIVALE1IS_MASK) 1196 #define HFGITR_EL2_TLBIVALE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVALE1IS_SHIFT) 1197 #define HFGITR_EL2_TLBIVALE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVALE1IS_SHIFT) 1198 #define HFGITR_EL2_TLBIVAAE1IS_SHIFT 31 1199 #define HFGITR_EL2_TLBIVAAE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIVAAE1IS_SHIFT) 1200 #define HFGITR_EL2_TLBIVAAE1IS_VAL(x) ((x) & HFGITR_EL2_TLBIVAAE1IS_MASK) 1201 #define HFGITR_EL2_TLBIVAAE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAAE1IS_SHIFT) 1202 #define HFGITR_EL2_TLBIVAAE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAAE1IS_SHIFT) 1203 #define HFGITR_EL2_TLBIASIDE1IS_SHIFT 30 1204 #define HFGITR_EL2_TLBIASIDE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIASIDE1IS_SHIFT) 1205 #define HFGITR_EL2_TLBIASIDE1IS_VAL(x) ((x) & HFGITR_EL2_TLBIASIDE1IS_MASK) 1206 #define HFGITR_EL2_TLBIASIDE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIASIDE1IS_SHIFT) 1207 #define HFGITR_EL2_TLBIASIDE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIASIDE1IS_SHIFT) 1208 #define HFGITR_EL2_TLBIVAE1IS_SHIFT 29 1209 #define HFGITR_EL2_TLBIVAE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIVAE1IS_SHIFT) 1210 #define HFGITR_EL2_TLBIVAE1IS_VAL(x) ((x) & HFGITR_EL2_TLBIVAE1IS_MASK) 1211 #define HFGITR_EL2_TLBIVAE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAE1IS_SHIFT) 1212 #define HFGITR_EL2_TLBIVAE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAE1IS_SHIFT) 1213 #define HFGITR_EL2_TLBIVMALLE1IS_SHIFT 28 1214 #define HFGITR_EL2_TLBIVMALLE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIVMALLE1IS_SHIFT) 1215 #define HFGITR_EL2_TLBIVMALLE1IS_VAL(x) ((x) & HFGITR_EL2_TLBIVMALLE1IS_MASK) 1216 #define HFGITR_EL2_TLBIVMALLE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVMALLE1IS_SHIFT) 1217 #define HFGITR_EL2_TLBIVMALLE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVMALLE1IS_SHIFT) 1218 #define HFGITR_EL2_TLBIRVAALE1OS_SHIFT 27 1219 #define HFGITR_EL2_TLBIRVAALE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAALE1OS_SHIFT) 1220 #define HFGITR_EL2_TLBIRVAALE1OS_VAL(x) ((x) & HFGITR_EL2_TLBIRVAALE1OS_MASK) 1221 #define HFGITR_EL2_TLBIRVAALE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAALE1OS_SHIFT) 1222 #define HFGITR_EL2_TLBIRVAALE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAALE1OS_SHIFT) 1223 #define HFGITR_EL2_TLBIRVALE1OS_SHIFT 26 1224 #define HFGITR_EL2_TLBIRVALE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVALE1OS_SHIFT) 1225 #define HFGITR_EL2_TLBIRVALE1OS_VAL(x) ((x) & HFGITR_EL2_TLBIRVALE1OS_MASK) 1226 #define HFGITR_EL2_TLBIRVALE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVALE1OS_SHIFT) 1227 #define HFGITR_EL2_TLBIRVALE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVALE1OS_SHIFT) 1228 #define HFGITR_EL2_TLBIRVAAE1OS_SHIFT 25 1229 #define HFGITR_EL2_TLBIRVAAE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAAE1OS_SHIFT) 1230 #define HFGITR_EL2_TLBIRVAAE1OS_VAL(x) ((x) & HFGITR_EL2_TLBIRVAAE1OS_MASK) 1231 #define HFGITR_EL2_TLBIRVAAE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAAE1OS_SHIFT) 1232 #define HFGITR_EL2_TLBIRVAAE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAAE1OS_SHIFT) 1233 #define HFGITR_EL2_TLBIRVAE1OS_SHIFT 24 1234 #define HFGITR_EL2_TLBIRVAE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAE1OS_SHIFT) 1235 #define HFGITR_EL2_TLBIRVAE1OS_VAL(x) ((x) & HFGITR_EL2_TLBIRVAE1OS_MASK) 1236 #define HFGITR_EL2_TLBIRVAE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAE1OS_SHIFT) 1237 #define HFGITR_EL2_TLBIRVAE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAE1OS_SHIFT) 1238 #define HFGITR_EL2_TLBIVAALE1OS_SHIFT 23 1239 #define HFGITR_EL2_TLBIVAALE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIVAALE1OS_SHIFT) 1240 #define HFGITR_EL2_TLBIVAALE1OS_VAL(x) ((x) & HFGITR_EL2_TLBIVAALE1OS_MASK) 1241 #define HFGITR_EL2_TLBIVAALE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAALE1OS_SHIFT) 1242 #define HFGITR_EL2_TLBIVAALE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAALE1OS_SHIFT) 1243 #define HFGITR_EL2_TLBIVALE1OS_SHIFT 22 1244 #define HFGITR_EL2_TLBIVALE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIVALE1OS_SHIFT) 1245 #define HFGITR_EL2_TLBIVALE1OS_VAL(x) ((x) & HFGITR_EL2_TLBIVALE1OS_MASK) 1246 #define HFGITR_EL2_TLBIVALE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVALE1OS_SHIFT) 1247 #define HFGITR_EL2_TLBIVALE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVALE1OS_SHIFT) 1248 #define HFGITR_EL2_TLBIVAAE1OS_SHIFT 21 1249 #define HFGITR_EL2_TLBIVAAE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIVAAE1OS_SHIFT) 1250 #define HFGITR_EL2_TLBIVAAE1OS_VAL(x) ((x) & HFGITR_EL2_TLBIVAAE1OS_MASK) 1251 #define HFGITR_EL2_TLBIVAAE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAAE1OS_SHIFT) 1252 #define HFGITR_EL2_TLBIVAAE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAAE1OS_SHIFT) 1253 #define HFGITR_EL2_TLBIASIDE1OS_SHIFT 20 1254 #define HFGITR_EL2_TLBIASIDE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIASIDE1OS_SHIFT) 1255 #define HFGITR_EL2_TLBIASIDE1OS_VAL(x) ((x) & HFGITR_EL2_TLBIASIDE1OS_MASK) 1256 #define HFGITR_EL2_TLBIASIDE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIASIDE1OS_SHIFT) 1257 #define HFGITR_EL2_TLBIASIDE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIASIDE1OS_SHIFT) 1258 #define HFGITR_EL2_TLBIVAE1OS_SHIFT 19 1259 #define HFGITR_EL2_TLBIVAE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIVAE1OS_SHIFT) 1260 #define HFGITR_EL2_TLBIVAE1OS_VAL(x) ((x) & HFGITR_EL2_TLBIVAE1OS_MASK) 1261 #define HFGITR_EL2_TLBIVAE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAE1OS_SHIFT) 1262 #define HFGITR_EL2_TLBIVAE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAE1OS_SHIFT) 1263 #define HFGITR_EL2_TLBIVMALLE1OS_SHIFT 18 1264 #define HFGITR_EL2_TLBIVMALLE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIVMALLE1OS_SHIFT) 1265 #define HFGITR_EL2_TLBIVMALLE1OS_VAL(x) ((x) & HFGITR_EL2_TLBIVMALLE1OS_MASK) 1266 #define HFGITR_EL2_TLBIVMALLE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVMALLE1OS_SHIFT) 1267 #define HFGITR_EL2_TLBIVMALLE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVMALLE1OS_SHIFT) 1268 #define HFGITR_EL2_ATS1E1WP_SHIFT 17 1269 #define HFGITR_EL2_ATS1E1WP_MASK (UL(0x1) << HFGITR_EL2_ATS1E1WP_SHIFT) 1270 #define HFGITR_EL2_ATS1E1WP_VAL(x) ((x) & HFGITR_EL2_ATS1E1WP_MASK) 1271 #define HFGITR_EL2_ATS1E1WP_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E1WP_SHIFT) 1272 #define HFGITR_EL2_ATS1E1WP_TRAP (UL(0x1) << HFGITR_EL2_ATS1E1WP_SHIFT) 1273 #define HFGITR_EL2_ATS1E1RP_SHIFT 16 1274 #define HFGITR_EL2_ATS1E1RP_MASK (UL(0x1) << HFGITR_EL2_ATS1E1RP_SHIFT) 1275 #define HFGITR_EL2_ATS1E1RP_VAL(x) ((x) & HFGITR_EL2_ATS1E1RP_MASK) 1276 #define HFGITR_EL2_ATS1E1RP_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E1RP_SHIFT) 1277 #define HFGITR_EL2_ATS1E1RP_TRAP (UL(0x1) << HFGITR_EL2_ATS1E1RP_SHIFT) 1278 #define HFGITR_EL2_ATS1E0W_SHIFT 15 1279 #define HFGITR_EL2_ATS1E0W_MASK (UL(0x1) << HFGITR_EL2_ATS1E0W_SHIFT) 1280 #define HFGITR_EL2_ATS1E0W_VAL(x) ((x) & HFGITR_EL2_ATS1E0W_MASK) 1281 #define HFGITR_EL2_ATS1E0W_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E0W_SHIFT) 1282 #define HFGITR_EL2_ATS1E0W_TRAP (UL(0x1) << HFGITR_EL2_ATS1E0W_SHIFT) 1283 #define HFGITR_EL2_ATS1E0R_SHIFT 14 1284 #define HFGITR_EL2_ATS1E0R_MASK (UL(0x1) << HFGITR_EL2_ATS1E0R_SHIFT) 1285 #define HFGITR_EL2_ATS1E0R_VAL(x) ((x) & HFGITR_EL2_ATS1E0R_MASK) 1286 #define HFGITR_EL2_ATS1E0R_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E0R_SHIFT) 1287 #define HFGITR_EL2_ATS1E0R_TRAP (UL(0x1) << HFGITR_EL2_ATS1E0R_SHIFT) 1288 #define HFGITR_EL2_ATS1E1W_SHIFT 13 1289 #define HFGITR_EL2_ATS1E1W_MASK (UL(0x1) << HFGITR_EL2_ATS1E1W_SHIFT) 1290 #define HFGITR_EL2_ATS1E1W_VAL(x) ((x) & HFGITR_EL2_ATS1E1W_MASK) 1291 #define HFGITR_EL2_ATS1E1W_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E1W_SHIFT) 1292 #define HFGITR_EL2_ATS1E1W_TRAP (UL(0x1) << HFGITR_EL2_ATS1E1W_SHIFT) 1293 #define HFGITR_EL2_ATS1E1R_SHIFT 12 1294 #define HFGITR_EL2_ATS1E1R_MASK (UL(0x1) << HFGITR_EL2_ATS1E1R_SHIFT) 1295 #define HFGITR_EL2_ATS1E1R_VAL(x) ((x) & HFGITR_EL2_ATS1E1R_MASK) 1296 #define HFGITR_EL2_ATS1E1R_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E1R_SHIFT) 1297 #define HFGITR_EL2_ATS1E1R_TRAP (UL(0x1) << HFGITR_EL2_ATS1E1R_SHIFT) 1298 #define HFGITR_EL2_DCZVA_SHIFT 11 1299 #define HFGITR_EL2_DCZVA_MASK (UL(0x1) << HFGITR_EL2_DCZVA_SHIFT) 1300 #define HFGITR_EL2_DCZVA_VAL(x) ((x) & HFGITR_EL2_DCZVA_MASK) 1301 #define HFGITR_EL2_DCZVA_NOTRAP (UL(0x0) << HFGITR_EL2_DCZVA_SHIFT) 1302 #define HFGITR_EL2_DCZVA_TRAP (UL(0x1) << HFGITR_EL2_DCZVA_SHIFT) 1303 #define HFGITR_EL2_DCCIVAC_SHIFT 10 1304 #define HFGITR_EL2_DCCIVAC_MASK (UL(0x1) << HFGITR_EL2_DCCIVAC_SHIFT) 1305 #define HFGITR_EL2_DCCIVAC_VAL(x) ((x) & HFGITR_EL2_DCCIVAC_MASK) 1306 #define HFGITR_EL2_DCCIVAC_NOTRAP (UL(0x0) << HFGITR_EL2_DCCIVAC_SHIFT) 1307 #define HFGITR_EL2_DCCIVAC_TRAP (UL(0x1) << HFGITR_EL2_DCCIVAC_SHIFT) 1308 #define HFGITR_EL2_DCCVADP_SHIFT 9 1309 #define HFGITR_EL2_DCCVADP_MASK (UL(0x1) << HFGITR_EL2_DCCVADP_SHIFT) 1310 #define HFGITR_EL2_DCCVADP_VAL(x) ((x) & HFGITR_EL2_DCCVADP_MASK) 1311 #define HFGITR_EL2_DCCVADP_NOTRAP (UL(0x0) << HFGITR_EL2_DCCVADP_SHIFT) 1312 #define HFGITR_EL2_DCCVADP_TRAP (UL(0x1) << HFGITR_EL2_DCCVADP_SHIFT) 1313 #define HFGITR_EL2_DCCVAP_SHIFT 8 1314 #define HFGITR_EL2_DCCVAP_MASK (UL(0x1) << HFGITR_EL2_DCCVAP_SHIFT) 1315 #define HFGITR_EL2_DCCVAP_VAL(x) ((x) & HFGITR_EL2_DCCVAP_MASK) 1316 #define HFGITR_EL2_DCCVAP_NOTRAP (UL(0x0) << HFGITR_EL2_DCCVAP_SHIFT) 1317 #define HFGITR_EL2_DCCVAP_TRAP (UL(0x1) << HFGITR_EL2_DCCVAP_SHIFT) 1318 #define HFGITR_EL2_DCCVAU_SHIFT 7 1319 #define HFGITR_EL2_DCCVAU_MASK (UL(0x1) << HFGITR_EL2_DCCVAU_SHIFT) 1320 #define HFGITR_EL2_DCCVAU_VAL(x) ((x) & HFGITR_EL2_DCCVAU_MASK) 1321 #define HFGITR_EL2_DCCVAU_NOTRAP (UL(0x0) << HFGITR_EL2_DCCVAU_SHIFT) 1322 #define HFGITR_EL2_DCCVAU_TRAP (UL(0x1) << HFGITR_EL2_DCCVAU_SHIFT) 1323 #define HFGITR_EL2_DCCISW_SHIFT 6 1324 #define HFGITR_EL2_DCCISW_MASK (UL(0x1) << HFGITR_EL2_DCCISW_SHIFT) 1325 #define HFGITR_EL2_DCCISW_VAL(x) ((x) & HFGITR_EL2_DCCISW_MASK) 1326 #define HFGITR_EL2_DCCISW_NOTRAP (UL(0x0) << HFGITR_EL2_DCCISW_SHIFT) 1327 #define HFGITR_EL2_DCCISW_TRAP (UL(0x1) << HFGITR_EL2_DCCISW_SHIFT) 1328 #define HFGITR_EL2_DCCSW_SHIFT 5 1329 #define HFGITR_EL2_DCCSW_MASK (UL(0x1) << HFGITR_EL2_DCCSW_SHIFT) 1330 #define HFGITR_EL2_DCCSW_VAL(x) ((x) & HFGITR_EL2_DCCSW_MASK) 1331 #define HFGITR_EL2_DCCSW_NOTRAP (UL(0x0) << HFGITR_EL2_DCCSW_SHIFT) 1332 #define HFGITR_EL2_DCCSW_TRAP (UL(0x1) << HFGITR_EL2_DCCSW_SHIFT) 1333 #define HFGITR_EL2_DCISW_SHIFT 4 1334 #define HFGITR_EL2_DCISW_MASK (UL(0x1) << HFGITR_EL2_DCISW_SHIFT) 1335 #define HFGITR_EL2_DCISW_VAL(x) ((x) & HFGITR_EL2_DCISW_MASK) 1336 #define HFGITR_EL2_DCISW_NOTRAP (UL(0x0) << HFGITR_EL2_DCISW_SHIFT) 1337 #define HFGITR_EL2_DCISW_TRAP (UL(0x1) << HFGITR_EL2_DCISW_SHIFT) 1338 #define HFGITR_EL2_DCIVAC_SHIFT 3 1339 #define HFGITR_EL2_DCIVAC_MASK (UL(0x1) << HFGITR_EL2_DCIVAC_SHIFT) 1340 #define HFGITR_EL2_DCIVAC_VAL(x) ((x) & HFGITR_EL2_DCIVAC_MASK) 1341 #define HFGITR_EL2_DCIVAC_NOTRAP (UL(0x0) << HFGITR_EL2_DCIVAC_SHIFT) 1342 #define HFGITR_EL2_DCIVAC_TRAP (UL(0x1) << HFGITR_EL2_DCIVAC_SHIFT) 1343 #define HFGITR_EL2_ICIVAU_SHIFT 2 1344 #define HFGITR_EL2_ICIVAU_MASK (UL(0x1) << HFGITR_EL2_ICIVAU_SHIFT) 1345 #define HFGITR_EL2_ICIVAU_VAL(x) ((x) & HFGITR_EL2_ICIVAU_MASK) 1346 #define HFGITR_EL2_ICIVAU_NOTRAP (UL(0x0) << HFGITR_EL2_ICIVAU_SHIFT) 1347 #define HFGITR_EL2_ICIVAU_TRAP (UL(0x1) << HFGITR_EL2_ICIVAU_SHIFT) 1348 #define HFGITR_EL2_ICIALLU_SHIFT 1 1349 #define HFGITR_EL2_ICIALLU_MASK (UL(0x1) << HFGITR_EL2_ICIALLU_SHIFT) 1350 #define HFGITR_EL2_ICIALLU_VAL(x) ((x) & HFGITR_EL2_ICIALLU_MASK) 1351 #define HFGITR_EL2_ICIALLU_NOTRAP (UL(0x0) << HFGITR_EL2_ICIALLU_SHIFT) 1352 #define HFGITR_EL2_ICIALLU_TRAP (UL(0x1) << HFGITR_EL2_ICIALLU_SHIFT) 1353 #define HFGITR_EL2_ICIALLUIS_SHIFT 0 1354 #define HFGITR_EL2_ICIALLUIS_MASK (UL(0x1) << HFGITR_EL2_ICIALLUIS_SHIFT) 1355 #define HFGITR_EL2_ICIALLUIS_VAL(x) ((x) & HFGITR_EL2_ICIALLUIS_MASK) 1356 #define HFGITR_EL2_ICIALLUIS_NOTRAP (UL(0x0) << HFGITR_EL2_ICIALLUIS_SHIFT) 1357 #define HFGITR_EL2_ICIALLUIS_TRAP (UL(0x1) << HFGITR_EL2_ICIALLUIS_SHIFT) 1358 1359 /* HFGRTR2_EL2 */ 1360 #define HFGRTR2_EL2_REG MRS_REG_ALT_NAME(HFGRTR2_EL2) 1361 #define HFGRTR2_EL2_op0 3 1362 #define HFGRTR2_EL2_op1 4 1363 #define HFGRTR2_EL2_CRn 3 1364 #define HFGRTR2_EL2_CRm 1 1365 #define HFGRTR2_EL2_op2 2 1366 #define HFGRTR2_EL2_nRCWSMASK_EL1_SHIFT 2 1367 #define HFGRTR2_EL2_nRCWSMASK_EL1_MASK (UL(0x1) << HFGRTR2_EL2_nRCWSMASK_EL1_SHIFT) 1368 #define HFGRTR2_EL2_nRCWSMASK_EL1_VAL(x) ((x) & HFGRTR2_EL2_nRCWSMASK_EL1_MASK) 1369 #define HFGRTR2_EL2_nRCWSMASK_EL1_TRAP (UL(0x0) << HFGRTR2_EL2_nRCWSMASK_EL1_SHIFT) 1370 #define HFGRTR2_EL2_nRCWSMASK_EL1_NOTRAP (UL(0x1) << HFGRTR2_EL2_nRCWSMASK_EL1_SHIFT) 1371 #define HFGRTR2_EL2_nERXGSR_EL1_SHIFT 1 1372 #define HFGRTR2_EL2_nERXGSR_EL1_MASK (UL(0x1) << HFGRTR2_EL2_nERXGSR_EL1_SHIFT) 1373 #define HFGRTR2_EL2_nERXGSR_EL1_VAL(x) ((x) & HFGRTR2_EL2_nERXGSR_EL1_MASK) 1374 #define HFGRTR2_EL2_nERXGSR_EL1_TRAP (UL(0x0) << HFGRTR2_EL2_nERXGSR_EL1_SHIFT) 1375 #define HFGRTR2_EL2_nERXGSR_EL1_NOTRAP (UL(0x1) << HFGRTR2_EL2_nERXGSR_EL1_SHIFT) 1376 #define HFGRTR2_EL2_nPFAR_EL1_SHIFT 0 1377 #define HFGRTR2_EL2_nPFAR_EL1_MASK (UL(0x1) << HFGRTR2_EL2_nPFAR_EL1_SHIFT) 1378 #define HFGRTR2_EL2_nPFAR_EL1_VAL(x) ((x) & HFGRTR2_EL2_nPFAR_EL1_MASK) 1379 #define HFGRTR2_EL2_nPFAR_EL1_TRAP (UL(0x0) << HFGRTR2_EL2_nPFAR_EL1_SHIFT) 1380 #define HFGRTR2_EL2_nPFAR_EL1_NOTRAP (UL(0x1) << HFGRTR2_EL2_nPFAR_EL1_SHIFT) 1381 1382 /* HFGRTR_EL2 */ 1383 #define HFGRTR_EL2_REG MRS_REG_ALT_NAME(HFGRTR_EL2) 1384 #define HFGRTR_EL2_op0 3 1385 #define HFGRTR_EL2_op1 4 1386 #define HFGRTR_EL2_CRn 1 1387 #define HFGRTR_EL2_CRm 1 1388 #define HFGRTR_EL2_op2 4 1389 #define HFGRTR_EL2_nAMAIR2_EL1_SHIFT 63 1390 #define HFGRTR_EL2_nAMAIR2_EL1_MASK (UL(0x1) << HFGRTR_EL2_nAMAIR2_EL1_SHIFT) 1391 #define HFGRTR_EL2_nAMAIR2_EL1_VAL(x) ((x) & HFGRTR_EL2_nAMAIR2_EL1_MASK) 1392 #define HFGRTR_EL2_nAMAIR2_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nAMAIR2_EL1_SHIFT) 1393 #define HFGRTR_EL2_nAMAIR2_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nAMAIR2_EL1_SHIFT) 1394 #define HFGRTR_EL2_nMAIR2_EL1_SHIFT 62 1395 #define HFGRTR_EL2_nMAIR2_EL1_MASK (UL(0x1) << HFGRTR_EL2_nMAIR2_EL1_SHIFT) 1396 #define HFGRTR_EL2_nMAIR2_EL1_VAL(x) ((x) & HFGRTR_EL2_nMAIR2_EL1_MASK) 1397 #define HFGRTR_EL2_nMAIR2_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nMAIR2_EL1_SHIFT) 1398 #define HFGRTR_EL2_nMAIR2_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nMAIR2_EL1_SHIFT) 1399 #define HFGRTR_EL2_nS2POR_EL1_SHIFT 61 1400 #define HFGRTR_EL2_nS2POR_EL1_MASK (UL(0x1) << HFGRTR_EL2_nS2POR_EL1_SHIFT) 1401 #define HFGRTR_EL2_nS2POR_EL1_VAL(x) ((x) & HFGRTR_EL2_nS2POR_EL1_MASK) 1402 #define HFGRTR_EL2_nS2POR_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nS2POR_EL1_SHIFT) 1403 #define HFGRTR_EL2_nS2POR_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nS2POR_EL1_SHIFT) 1404 #define HFGRTR_EL2_nPOR_EL1_SHIFT 60 1405 #define HFGRTR_EL2_nPOR_EL1_MASK (UL(0x1) << HFGRTR_EL2_nPOR_EL1_SHIFT) 1406 #define HFGRTR_EL2_nPOR_EL1_VAL(x) ((x) & HFGRTR_EL2_nPOR_EL1_MASK) 1407 #define HFGRTR_EL2_nPOR_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nPOR_EL1_SHIFT) 1408 #define HFGRTR_EL2_nPOR_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nPOR_EL1_SHIFT) 1409 #define HFGRTR_EL2_nPOR_EL0_SHIFT 59 1410 #define HFGRTR_EL2_nPOR_EL0_MASK (UL(0x1) << HFGRTR_EL2_nPOR_EL0_SHIFT) 1411 #define HFGRTR_EL2_nPOR_EL0_VAL(x) ((x) & HFGRTR_EL2_nPOR_EL0_MASK) 1412 #define HFGRTR_EL2_nPOR_EL0_TRAP (UL(0x0) << HFGRTR_EL2_nPOR_EL0_SHIFT) 1413 #define HFGRTR_EL2_nPOR_EL0_NOTRAP (UL(0x1) << HFGRTR_EL2_nPOR_EL0_SHIFT) 1414 #define HFGRTR_EL2_nPIR_EL1_SHIFT 58 1415 #define HFGRTR_EL2_nPIR_EL1_MASK (UL(0x1) << HFGRTR_EL2_nPIR_EL1_SHIFT) 1416 #define HFGRTR_EL2_nPIR_EL1_VAL(x) ((x) & HFGRTR_EL2_nPIR_EL1_MASK) 1417 #define HFGRTR_EL2_nPIR_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nPIR_EL1_SHIFT) 1418 #define HFGRTR_EL2_nPIR_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nPIR_EL1_SHIFT) 1419 #define HFGRTR_EL2_nPIRE0_EL1_SHIFT 57 1420 #define HFGRTR_EL2_nPIRE0_EL1_MASK (UL(0x1) << HFGRTR_EL2_nPIRE0_EL1_SHIFT) 1421 #define HFGRTR_EL2_nPIRE0_EL1_VAL(x) ((x) & HFGRTR_EL2_nPIRE0_EL1_MASK) 1422 #define HFGRTR_EL2_nPIRE0_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nPIRE0_EL1_SHIFT) 1423 #define HFGRTR_EL2_nPIRE0_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nPIRE0_EL1_SHIFT) 1424 #define HFGRTR_EL2_nRCWMASK_EL1_SHIFT 56 1425 #define HFGRTR_EL2_nRCWMASK_EL1_MASK (UL(0x1) << HFGRTR_EL2_nRCWMASK_EL1_SHIFT) 1426 #define HFGRTR_EL2_nRCWMASK_EL1_VAL(x) ((x) & HFGRTR_EL2_nRCWMASK_EL1_MASK) 1427 #define HFGRTR_EL2_nRCWMASK_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nRCWMASK_EL1_SHIFT) 1428 #define HFGRTR_EL2_nRCWMASK_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nRCWMASK_EL1_SHIFT) 1429 #define HFGRTR_EL2_nTPIDR2_EL0_SHIFT 55 1430 #define HFGRTR_EL2_nTPIDR2_EL0_MASK (UL(0x1) << HFGRTR_EL2_nTPIDR2_EL0_SHIFT) 1431 #define HFGRTR_EL2_nTPIDR2_EL0_VAL(x) ((x) & HFGRTR_EL2_nTPIDR2_EL0_MASK) 1432 #define HFGRTR_EL2_nTPIDR2_EL0_TRAP (UL(0x0) << HFGRTR_EL2_nTPIDR2_EL0_SHIFT) 1433 #define HFGRTR_EL2_nTPIDR2_EL0_NOTRAP (UL(0x1) << HFGRTR_EL2_nTPIDR2_EL0_SHIFT) 1434 #define HFGRTR_EL2_nSMPRI_EL1_SHIFT 54 1435 #define HFGRTR_EL2_nSMPRI_EL1_MASK (UL(0x1) << HFGRTR_EL2_nSMPRI_EL1_SHIFT) 1436 #define HFGRTR_EL2_nSMPRI_EL1_VAL(x) ((x) & HFGRTR_EL2_nSMPRI_EL1_MASK) 1437 #define HFGRTR_EL2_nSMPRI_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nSMPRI_EL1_SHIFT) 1438 #define HFGRTR_EL2_nSMPRI_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nSMPRI_EL1_SHIFT) 1439 #define HFGRTR_EL2_nGCS_EL1_SHIFT 53 1440 #define HFGRTR_EL2_nGCS_EL1_MASK (UL(0x1) << HFGRTR_EL2_nGCS_EL1_SHIFT) 1441 #define HFGRTR_EL2_nGCS_EL1_VAL(x) ((x) & HFGRTR_EL2_nGCS_EL1_MASK) 1442 #define HFGRTR_EL2_nGCS_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nGCS_EL1_SHIFT) 1443 #define HFGRTR_EL2_nGCS_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nGCS_EL1_SHIFT) 1444 #define HFGRTR_EL2_nGCS_EL0_SHIFT 52 1445 #define HFGRTR_EL2_nGCS_EL0_MASK (UL(0x1) << HFGRTR_EL2_nGCS_EL0_SHIFT) 1446 #define HFGRTR_EL2_nGCS_EL0_VAL(x) ((x) & HFGRTR_EL2_nGCS_EL0_MASK) 1447 #define HFGRTR_EL2_nGCS_EL0_TRAP (UL(0x0) << HFGRTR_EL2_nGCS_EL0_SHIFT) 1448 #define HFGRTR_EL2_nGCS_EL0_NOTRAP (UL(0x1) << HFGRTR_EL2_nGCS_EL0_SHIFT) 1449 #define HFGRTR_EL2_nACCDATA_EL1_SHIFT 50 1450 #define HFGRTR_EL2_nACCDATA_EL1_MASK (UL(0x1) << HFGRTR_EL2_nACCDATA_EL1_SHIFT) 1451 #define HFGRTR_EL2_nACCDATA_EL1_VAL(x) ((x) & HFGRTR_EL2_nACCDATA_EL1_MASK) 1452 #define HFGRTR_EL2_nACCDATA_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nACCDATA_EL1_SHIFT) 1453 #define HFGRTR_EL2_nACCDATA_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nACCDATA_EL1_SHIFT) 1454 #define HFGRTR_EL2_ERXADDR_EL1_SHIFT 49 1455 #define HFGRTR_EL2_ERXADDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXADDR_EL1_SHIFT) 1456 #define HFGRTR_EL2_ERXADDR_EL1_VAL(x) ((x) & HFGRTR_EL2_ERXADDR_EL1_MASK) 1457 #define HFGRTR_EL2_ERXADDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXADDR_EL1_SHIFT) 1458 #define HFGRTR_EL2_ERXADDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXADDR_EL1_SHIFT) 1459 #define HFGRTR_EL2_ERXPFGCDN_EL1_SHIFT 48 1460 #define HFGRTR_EL2_ERXPFGCDN_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXPFGCDN_EL1_SHIFT) 1461 #define HFGRTR_EL2_ERXPFGCDN_EL1_VAL(x) ((x) & HFGRTR_EL2_ERXPFGCDN_EL1_MASK) 1462 #define HFGRTR_EL2_ERXPFGCDN_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXPFGCDN_EL1_SHIFT) 1463 #define HFGRTR_EL2_ERXPFGCDN_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXPFGCDN_EL1_SHIFT) 1464 #define HFGRTR_EL2_ERXPFGCTL_EL1_SHIFT 47 1465 #define HFGRTR_EL2_ERXPFGCTL_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXPFGCTL_EL1_SHIFT) 1466 #define HFGRTR_EL2_ERXPFGCTL_EL1_VAL(x) ((x) & HFGRTR_EL2_ERXPFGCTL_EL1_MASK) 1467 #define HFGRTR_EL2_ERXPFGCTL_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXPFGCTL_EL1_SHIFT) 1468 #define HFGRTR_EL2_ERXPFGCTL_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXPFGCTL_EL1_SHIFT) 1469 #define HFGRTR_EL2_ERXPFGF_EL1_SHIFT 46 1470 #define HFGRTR_EL2_ERXPFGF_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXPFGF_EL1_SHIFT) 1471 #define HFGRTR_EL2_ERXPFGF_EL1_VAL(x) ((x) & HFGRTR_EL2_ERXPFGF_EL1_MASK) 1472 #define HFGRTR_EL2_ERXPFGF_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXPFGF_EL1_SHIFT) 1473 #define HFGRTR_EL2_ERXPFGF_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXPFGF_EL1_SHIFT) 1474 #define HFGRTR_EL2_ERXMISCn_EL1_SHIFT 45 1475 #define HFGRTR_EL2_ERXMISCn_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXMISCn_EL1_SHIFT) 1476 #define HFGRTR_EL2_ERXMISCn_EL1_VAL(x) ((x) & HFGRTR_EL2_ERXMISCn_EL1_MASK) 1477 #define HFGRTR_EL2_ERXMISCn_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXMISCn_EL1_SHIFT) 1478 #define HFGRTR_EL2_ERXMISCn_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXMISCn_EL1_SHIFT) 1479 #define HFGRTR_EL2_ERXSTATUS_EL1_SHIFT 44 1480 #define HFGRTR_EL2_ERXSTATUS_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXSTATUS_EL1_SHIFT) 1481 #define HFGRTR_EL2_ERXSTATUS_EL1_VAL(x) ((x) & HFGRTR_EL2_ERXSTATUS_EL1_MASK) 1482 #define HFGRTR_EL2_ERXSTATUS_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXSTATUS_EL1_SHIFT) 1483 #define HFGRTR_EL2_ERXSTATUS_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXSTATUS_EL1_SHIFT) 1484 #define HFGRTR_EL2_ERXCTLR_EL1_SHIFT 43 1485 #define HFGRTR_EL2_ERXCTLR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXCTLR_EL1_SHIFT) 1486 #define HFGRTR_EL2_ERXCTLR_EL1_VAL(x) ((x) & HFGRTR_EL2_ERXCTLR_EL1_MASK) 1487 #define HFGRTR_EL2_ERXCTLR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXCTLR_EL1_SHIFT) 1488 #define HFGRTR_EL2_ERXCTLR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXCTLR_EL1_SHIFT) 1489 #define HFGRTR_EL2_ERXFR_EL1_SHIFT 42 1490 #define HFGRTR_EL2_ERXFR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXFR_EL1_SHIFT) 1491 #define HFGRTR_EL2_ERXFR_EL1_VAL(x) ((x) & HFGRTR_EL2_ERXFR_EL1_MASK) 1492 #define HFGRTR_EL2_ERXFR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXFR_EL1_SHIFT) 1493 #define HFGRTR_EL2_ERXFR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXFR_EL1_SHIFT) 1494 #define HFGRTR_EL2_ERRSELR_EL1_SHIFT 41 1495 #define HFGRTR_EL2_ERRSELR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERRSELR_EL1_SHIFT) 1496 #define HFGRTR_EL2_ERRSELR_EL1_VAL(x) ((x) & HFGRTR_EL2_ERRSELR_EL1_MASK) 1497 #define HFGRTR_EL2_ERRSELR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERRSELR_EL1_SHIFT) 1498 #define HFGRTR_EL2_ERRSELR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERRSELR_EL1_SHIFT) 1499 #define HFGRTR_EL2_ERRIDR_EL1_SHIFT 40 1500 #define HFGRTR_EL2_ERRIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERRIDR_EL1_SHIFT) 1501 #define HFGRTR_EL2_ERRIDR_EL1_VAL(x) ((x) & HFGRTR_EL2_ERRIDR_EL1_MASK) 1502 #define HFGRTR_EL2_ERRIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERRIDR_EL1_SHIFT) 1503 #define HFGRTR_EL2_ERRIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERRIDR_EL1_SHIFT) 1504 #define HFGRTR_EL2_ICC_IGRPENn_EL1_SHIFT 39 1505 #define HFGRTR_EL2_ICC_IGRPENn_EL1_MASK (UL(0x1) << HFGRTR_EL2_ICC_IGRPENn_EL1_SHIFT) 1506 #define HFGRTR_EL2_ICC_IGRPENn_EL1_VAL(x) ((x) & HFGRTR_EL2_ICC_IGRPENn_EL1_MASK) 1507 #define HFGRTR_EL2_ICC_IGRPENn_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ICC_IGRPENn_EL1_SHIFT) 1508 #define HFGRTR_EL2_ICC_IGRPENn_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ICC_IGRPENn_EL1_SHIFT) 1509 #define HFGRTR_EL2_VBAR_EL1_SHIFT 38 1510 #define HFGRTR_EL2_VBAR_EL1_MASK (UL(0x1) << HFGRTR_EL2_VBAR_EL1_SHIFT) 1511 #define HFGRTR_EL2_VBAR_EL1_VAL(x) ((x) & HFGRTR_EL2_VBAR_EL1_MASK) 1512 #define HFGRTR_EL2_VBAR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_VBAR_EL1_SHIFT) 1513 #define HFGRTR_EL2_VBAR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_VBAR_EL1_SHIFT) 1514 #define HFGRTR_EL2_TTBR1_EL1_SHIFT 37 1515 #define HFGRTR_EL2_TTBR1_EL1_MASK (UL(0x1) << HFGRTR_EL2_TTBR1_EL1_SHIFT) 1516 #define HFGRTR_EL2_TTBR1_EL1_VAL(x) ((x) & HFGRTR_EL2_TTBR1_EL1_MASK) 1517 #define HFGRTR_EL2_TTBR1_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_TTBR1_EL1_SHIFT) 1518 #define HFGRTR_EL2_TTBR1_EL1_TRAP (UL(0x1) << HFGRTR_EL2_TTBR1_EL1_SHIFT) 1519 #define HFGRTR_EL2_TTBR0_EL1_SHIFT 36 1520 #define HFGRTR_EL2_TTBR0_EL1_MASK (UL(0x1) << HFGRTR_EL2_TTBR0_EL1_SHIFT) 1521 #define HFGRTR_EL2_TTBR0_EL1_VAL(x) ((x) & HFGRTR_EL2_TTBR0_EL1_MASK) 1522 #define HFGRTR_EL2_TTBR0_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_TTBR0_EL1_SHIFT) 1523 #define HFGRTR_EL2_TTBR0_EL1_TRAP (UL(0x1) << HFGRTR_EL2_TTBR0_EL1_SHIFT) 1524 #define HFGRTR_EL2_TPIDR_EL0_SHIFT 35 1525 #define HFGRTR_EL2_TPIDR_EL0_MASK (UL(0x1) << HFGRTR_EL2_TPIDR_EL0_SHIFT) 1526 #define HFGRTR_EL2_TPIDR_EL0_VAL(x) ((x) & HFGRTR_EL2_TPIDR_EL0_MASK) 1527 #define HFGRTR_EL2_TPIDR_EL0_NOTRAP (UL(0x0) << HFGRTR_EL2_TPIDR_EL0_SHIFT) 1528 #define HFGRTR_EL2_TPIDR_EL0_TRAP (UL(0x1) << HFGRTR_EL2_TPIDR_EL0_SHIFT) 1529 #define HFGRTR_EL2_TPIDRRO_EL0_SHIFT 34 1530 #define HFGRTR_EL2_TPIDRRO_EL0_MASK (UL(0x1) << HFGRTR_EL2_TPIDRRO_EL0_SHIFT) 1531 #define HFGRTR_EL2_TPIDRRO_EL0_VAL(x) ((x) & HFGRTR_EL2_TPIDRRO_EL0_MASK) 1532 #define HFGRTR_EL2_TPIDRRO_EL0_NOTRAP (UL(0x0) << HFGRTR_EL2_TPIDRRO_EL0_SHIFT) 1533 #define HFGRTR_EL2_TPIDRRO_EL0_TRAP (UL(0x1) << HFGRTR_EL2_TPIDRRO_EL0_SHIFT) 1534 #define HFGRTR_EL2_TPIDR_EL1_SHIFT 33 1535 #define HFGRTR_EL2_TPIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_TPIDR_EL1_SHIFT) 1536 #define HFGRTR_EL2_TPIDR_EL1_VAL(x) ((x) & HFGRTR_EL2_TPIDR_EL1_MASK) 1537 #define HFGRTR_EL2_TPIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_TPIDR_EL1_SHIFT) 1538 #define HFGRTR_EL2_TPIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_TPIDR_EL1_SHIFT) 1539 #define HFGRTR_EL2_TCR_EL1_SHIFT 32 1540 #define HFGRTR_EL2_TCR_EL1_MASK (UL(0x1) << HFGRTR_EL2_TCR_EL1_SHIFT) 1541 #define HFGRTR_EL2_TCR_EL1_VAL(x) ((x) & HFGRTR_EL2_TCR_EL1_MASK) 1542 #define HFGRTR_EL2_TCR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_TCR_EL1_SHIFT) 1543 #define HFGRTR_EL2_TCR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_TCR_EL1_SHIFT) 1544 #define HFGRTR_EL2_SCXTNUM_EL0_SHIFT 31 1545 #define HFGRTR_EL2_SCXTNUM_EL0_MASK (UL(0x1) << HFGRTR_EL2_SCXTNUM_EL0_SHIFT) 1546 #define HFGRTR_EL2_SCXTNUM_EL0_VAL(x) ((x) & HFGRTR_EL2_SCXTNUM_EL0_MASK) 1547 #define HFGRTR_EL2_SCXTNUM_EL0_NOTRAP (UL(0x0) << HFGRTR_EL2_SCXTNUM_EL0_SHIFT) 1548 #define HFGRTR_EL2_SCXTNUM_EL0_TRAP (UL(0x1) << HFGRTR_EL2_SCXTNUM_EL0_SHIFT) 1549 #define HFGRTR_EL2_SCXTNUM_EL1_SHIFT 30 1550 #define HFGRTR_EL2_SCXTNUM_EL1_MASK (UL(0x1) << HFGRTR_EL2_SCXTNUM_EL1_SHIFT) 1551 #define HFGRTR_EL2_SCXTNUM_EL1_VAL(x) ((x) & HFGRTR_EL2_SCXTNUM_EL1_MASK) 1552 #define HFGRTR_EL2_SCXTNUM_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_SCXTNUM_EL1_SHIFT) 1553 #define HFGRTR_EL2_SCXTNUM_EL1_TRAP (UL(0x1) << HFGRTR_EL2_SCXTNUM_EL1_SHIFT) 1554 #define HFGRTR_EL2_SCTLR_EL1_SHIFT 29 1555 #define HFGRTR_EL2_SCTLR_EL1_MASK (UL(0x1) << HFGRTR_EL2_SCTLR_EL1_SHIFT) 1556 #define HFGRTR_EL2_SCTLR_EL1_VAL(x) ((x) & HFGRTR_EL2_SCTLR_EL1_MASK) 1557 #define HFGRTR_EL2_SCTLR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_SCTLR_EL1_SHIFT) 1558 #define HFGRTR_EL2_SCTLR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_SCTLR_EL1_SHIFT) 1559 #define HFGRTR_EL2_REVIDR_EL1_SHIFT 28 1560 #define HFGRTR_EL2_REVIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_REVIDR_EL1_SHIFT) 1561 #define HFGRTR_EL2_REVIDR_EL1_VAL(x) ((x) & HFGRTR_EL2_REVIDR_EL1_MASK) 1562 #define HFGRTR_EL2_REVIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_REVIDR_EL1_SHIFT) 1563 #define HFGRTR_EL2_REVIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_REVIDR_EL1_SHIFT) 1564 #define HFGRTR_EL2_PAR_EL1_SHIFT 27 1565 #define HFGRTR_EL2_PAR_EL1_MASK (UL(0x1) << HFGRTR_EL2_PAR_EL1_SHIFT) 1566 #define HFGRTR_EL2_PAR_EL1_VAL(x) ((x) & HFGRTR_EL2_PAR_EL1_MASK) 1567 #define HFGRTR_EL2_PAR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_PAR_EL1_SHIFT) 1568 #define HFGRTR_EL2_PAR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_PAR_EL1_SHIFT) 1569 #define HFGRTR_EL2_MPIDR_EL1_SHIFT 26 1570 #define HFGRTR_EL2_MPIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_MPIDR_EL1_SHIFT) 1571 #define HFGRTR_EL2_MPIDR_EL1_VAL(x) ((x) & HFGRTR_EL2_MPIDR_EL1_MASK) 1572 #define HFGRTR_EL2_MPIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_MPIDR_EL1_SHIFT) 1573 #define HFGRTR_EL2_MPIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_MPIDR_EL1_SHIFT) 1574 #define HFGRTR_EL2_MIDR_EL1_SHIFT 25 1575 #define HFGRTR_EL2_MIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_MIDR_EL1_SHIFT) 1576 #define HFGRTR_EL2_MIDR_EL1_VAL(x) ((x) & HFGRTR_EL2_MIDR_EL1_MASK) 1577 #define HFGRTR_EL2_MIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_MIDR_EL1_SHIFT) 1578 #define HFGRTR_EL2_MIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_MIDR_EL1_SHIFT) 1579 #define HFGRTR_EL2_MAIR_EL1_SHIFT 24 1580 #define HFGRTR_EL2_MAIR_EL1_MASK (UL(0x1) << HFGRTR_EL2_MAIR_EL1_SHIFT) 1581 #define HFGRTR_EL2_MAIR_EL1_VAL(x) ((x) & HFGRTR_EL2_MAIR_EL1_MASK) 1582 #define HFGRTR_EL2_MAIR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_MAIR_EL1_SHIFT) 1583 #define HFGRTR_EL2_MAIR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_MAIR_EL1_SHIFT) 1584 #define HFGRTR_EL2_LORSA_EL1_SHIFT 23 1585 #define HFGRTR_EL2_LORSA_EL1_MASK (UL(0x1) << HFGRTR_EL2_LORSA_EL1_SHIFT) 1586 #define HFGRTR_EL2_LORSA_EL1_VAL(x) ((x) & HFGRTR_EL2_LORSA_EL1_MASK) 1587 #define HFGRTR_EL2_LORSA_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_LORSA_EL1_SHIFT) 1588 #define HFGRTR_EL2_LORSA_EL1_TRAP (UL(0x1) << HFGRTR_EL2_LORSA_EL1_SHIFT) 1589 #define HFGRTR_EL2_LORN_EL1_SHIFT 22 1590 #define HFGRTR_EL2_LORN_EL1_MASK (UL(0x1) << HFGRTR_EL2_LORN_EL1_SHIFT) 1591 #define HFGRTR_EL2_LORN_EL1_VAL(x) ((x) & HFGRTR_EL2_LORN_EL1_MASK) 1592 #define HFGRTR_EL2_LORN_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_LORN_EL1_SHIFT) 1593 #define HFGRTR_EL2_LORN_EL1_TRAP (UL(0x1) << HFGRTR_EL2_LORN_EL1_SHIFT) 1594 #define HFGRTR_EL2_LORID_EL1_SHIFT 21 1595 #define HFGRTR_EL2_LORID_EL1_MASK (UL(0x1) << HFGRTR_EL2_LORID_EL1_SHIFT) 1596 #define HFGRTR_EL2_LORID_EL1_VAL(x) ((x) & HFGRTR_EL2_LORID_EL1_MASK) 1597 #define HFGRTR_EL2_LORID_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_LORID_EL1_SHIFT) 1598 #define HFGRTR_EL2_LORID_EL1_TRAP (UL(0x1) << HFGRTR_EL2_LORID_EL1_SHIFT) 1599 #define HFGRTR_EL2_LOREA_EL1_SHIFT 20 1600 #define HFGRTR_EL2_LOREA_EL1_MASK (UL(0x1) << HFGRTR_EL2_LOREA_EL1_SHIFT) 1601 #define HFGRTR_EL2_LOREA_EL1_VAL(x) ((x) & HFGRTR_EL2_LOREA_EL1_MASK) 1602 #define HFGRTR_EL2_LOREA_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_LOREA_EL1_SHIFT) 1603 #define HFGRTR_EL2_LOREA_EL1_TRAP (UL(0x1) << HFGRTR_EL2_LOREA_EL1_SHIFT) 1604 #define HFGRTR_EL2_LORC_EL1_SHIFT 19 1605 #define HFGRTR_EL2_LORC_EL1_MASK (UL(0x1) << HFGRTR_EL2_LORC_EL1_SHIFT) 1606 #define HFGRTR_EL2_LORC_EL1_VAL(x) ((x) & HFGRTR_EL2_LORC_EL1_MASK) 1607 #define HFGRTR_EL2_LORC_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_LORC_EL1_SHIFT) 1608 #define HFGRTR_EL2_LORC_EL1_TRAP (UL(0x1) << HFGRTR_EL2_LORC_EL1_SHIFT) 1609 #define HFGRTR_EL2_ISR_EL1_SHIFT 18 1610 #define HFGRTR_EL2_ISR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ISR_EL1_SHIFT) 1611 #define HFGRTR_EL2_ISR_EL1_VAL(x) ((x) & HFGRTR_EL2_ISR_EL1_MASK) 1612 #define HFGRTR_EL2_ISR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ISR_EL1_SHIFT) 1613 #define HFGRTR_EL2_ISR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ISR_EL1_SHIFT) 1614 #define HFGRTR_EL2_FAR_EL1_SHIFT 17 1615 #define HFGRTR_EL2_FAR_EL1_MASK (UL(0x1) << HFGRTR_EL2_FAR_EL1_SHIFT) 1616 #define HFGRTR_EL2_FAR_EL1_VAL(x) ((x) & HFGRTR_EL2_FAR_EL1_MASK) 1617 #define HFGRTR_EL2_FAR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_FAR_EL1_SHIFT) 1618 #define HFGRTR_EL2_FAR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_FAR_EL1_SHIFT) 1619 #define HFGRTR_EL2_ESR_EL1_SHIFT 16 1620 #define HFGRTR_EL2_ESR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ESR_EL1_SHIFT) 1621 #define HFGRTR_EL2_ESR_EL1_VAL(x) ((x) & HFGRTR_EL2_ESR_EL1_MASK) 1622 #define HFGRTR_EL2_ESR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ESR_EL1_SHIFT) 1623 #define HFGRTR_EL2_ESR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ESR_EL1_SHIFT) 1624 #define HFGRTR_EL2_DCZID_EL0_SHIFT 15 1625 #define HFGRTR_EL2_DCZID_EL0_MASK (UL(0x1) << HFGRTR_EL2_DCZID_EL0_SHIFT) 1626 #define HFGRTR_EL2_DCZID_EL0_VAL(x) ((x) & HFGRTR_EL2_DCZID_EL0_MASK) 1627 #define HFGRTR_EL2_DCZID_EL0_NOTRAP (UL(0x0) << HFGRTR_EL2_DCZID_EL0_SHIFT) 1628 #define HFGRTR_EL2_DCZID_EL0_TRAP (UL(0x1) << HFGRTR_EL2_DCZID_EL0_SHIFT) 1629 #define HFGRTR_EL2_CTR_EL0_SHIFT 14 1630 #define HFGRTR_EL2_CTR_EL0_MASK (UL(0x1) << HFGRTR_EL2_CTR_EL0_SHIFT) 1631 #define HFGRTR_EL2_CTR_EL0_VAL(x) ((x) & HFGRTR_EL2_CTR_EL0_MASK) 1632 #define HFGRTR_EL2_CTR_EL0_NOTRAP (UL(0x0) << HFGRTR_EL2_CTR_EL0_SHIFT) 1633 #define HFGRTR_EL2_CTR_EL0_TRAP (UL(0x1) << HFGRTR_EL2_CTR_EL0_SHIFT) 1634 #define HFGRTR_EL2_CSSELR_EL1_SHIFT 13 1635 #define HFGRTR_EL2_CSSELR_EL1_MASK (UL(0x1) << HFGRTR_EL2_CSSELR_EL1_SHIFT) 1636 #define HFGRTR_EL2_CSSELR_EL1_VAL(x) ((x) & HFGRTR_EL2_CSSELR_EL1_MASK) 1637 #define HFGRTR_EL2_CSSELR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_CSSELR_EL1_SHIFT) 1638 #define HFGRTR_EL2_CSSELR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_CSSELR_EL1_SHIFT) 1639 #define HFGRTR_EL2_CPACR_EL1_SHIFT 12 1640 #define HFGRTR_EL2_CPACR_EL1_MASK (UL(0x1) << HFGRTR_EL2_CPACR_EL1_SHIFT) 1641 #define HFGRTR_EL2_CPACR_EL1_VAL(x) ((x) & HFGRTR_EL2_CPACR_EL1_MASK) 1642 #define HFGRTR_EL2_CPACR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_CPACR_EL1_SHIFT) 1643 #define HFGRTR_EL2_CPACR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_CPACR_EL1_SHIFT) 1644 #define HFGRTR_EL2_CONTEXTIDR_EL1_SHIFT 11 1645 #define HFGRTR_EL2_CONTEXTIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_CONTEXTIDR_EL1_SHIFT) 1646 #define HFGRTR_EL2_CONTEXTIDR_EL1_VAL(x) ((x) & HFGRTR_EL2_CONTEXTIDR_EL1_MASK) 1647 #define HFGRTR_EL2_CONTEXTIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_CONTEXTIDR_EL1_SHIFT) 1648 #define HFGRTR_EL2_CONTEXTIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_CONTEXTIDR_EL1_SHIFT) 1649 #define HFGRTR_EL2_CLIDR_EL1_SHIFT 10 1650 #define HFGRTR_EL2_CLIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_CLIDR_EL1_SHIFT) 1651 #define HFGRTR_EL2_CLIDR_EL1_VAL(x) ((x) & HFGRTR_EL2_CLIDR_EL1_MASK) 1652 #define HFGRTR_EL2_CLIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_CLIDR_EL1_SHIFT) 1653 #define HFGRTR_EL2_CLIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_CLIDR_EL1_SHIFT) 1654 #define HFGRTR_EL2_CCSIDR_EL1_SHIFT 9 1655 #define HFGRTR_EL2_CCSIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_CCSIDR_EL1_SHIFT) 1656 #define HFGRTR_EL2_CCSIDR_EL1_VAL(x) ((x) & HFGRTR_EL2_CCSIDR_EL1_MASK) 1657 #define HFGRTR_EL2_CCSIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_CCSIDR_EL1_SHIFT) 1658 #define HFGRTR_EL2_CCSIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_CCSIDR_EL1_SHIFT) 1659 #define HFGRTR_EL2_APIBKey_SHIFT 8 1660 #define HFGRTR_EL2_APIBKey_MASK (UL(0x1) << HFGRTR_EL2_APIBKey_SHIFT) 1661 #define HFGRTR_EL2_APIBKey_VAL(x) ((x) & HFGRTR_EL2_APIBKey_MASK) 1662 #define HFGRTR_EL2_APIBKey_NOTRAP (UL(0x0) << HFGRTR_EL2_APIBKey_SHIFT) 1663 #define HFGRTR_EL2_APIBKey_TRAP (UL(0x1) << HFGRTR_EL2_APIBKey_SHIFT) 1664 #define HFGRTR_EL2_APIAKey_SHIFT 7 1665 #define HFGRTR_EL2_APIAKey_MASK (UL(0x1) << HFGRTR_EL2_APIAKey_SHIFT) 1666 #define HFGRTR_EL2_APIAKey_VAL(x) ((x) & HFGRTR_EL2_APIAKey_MASK) 1667 #define HFGRTR_EL2_APIAKey_NOTRAP (UL(0x0) << HFGRTR_EL2_APIAKey_SHIFT) 1668 #define HFGRTR_EL2_APIAKey_TRAP (UL(0x1) << HFGRTR_EL2_APIAKey_SHIFT) 1669 #define HFGRTR_EL2_APGAKey_SHIFT 6 1670 #define HFGRTR_EL2_APGAKey_MASK (UL(0x1) << HFGRTR_EL2_APGAKey_SHIFT) 1671 #define HFGRTR_EL2_APGAKey_VAL(x) ((x) & HFGRTR_EL2_APGAKey_MASK) 1672 #define HFGRTR_EL2_APGAKey_NOTRAP (UL(0x0) << HFGRTR_EL2_APGAKey_SHIFT) 1673 #define HFGRTR_EL2_APGAKey_TRAP (UL(0x1) << HFGRTR_EL2_APGAKey_SHIFT) 1674 #define HFGRTR_EL2_APDBKey_SHIFT 5 1675 #define HFGRTR_EL2_APDBKey_MASK (UL(0x1) << HFGRTR_EL2_APDBKey_SHIFT) 1676 #define HFGRTR_EL2_APDBKey_VAL(x) ((x) & HFGRTR_EL2_APDBKey_MASK) 1677 #define HFGRTR_EL2_APDBKey_NOTRAP (UL(0x0) << HFGRTR_EL2_APDBKey_SHIFT) 1678 #define HFGRTR_EL2_APDBKey_TRAP (UL(0x1) << HFGRTR_EL2_APDBKey_SHIFT) 1679 #define HFGRTR_EL2_APDAKey_SHIFT 4 1680 #define HFGRTR_EL2_APDAKey_MASK (UL(0x1) << HFGRTR_EL2_APDAKey_SHIFT) 1681 #define HFGRTR_EL2_APDAKey_VAL(x) ((x) & HFGRTR_EL2_APDAKey_MASK) 1682 #define HFGRTR_EL2_APDAKey_NOTRAP (UL(0x0) << HFGRTR_EL2_APDAKey_SHIFT) 1683 #define HFGRTR_EL2_APDAKey_TRAP (UL(0x1) << HFGRTR_EL2_APDAKey_SHIFT) 1684 #define HFGRTR_EL2_AMAIR_EL1_SHIFT 3 1685 #define HFGRTR_EL2_AMAIR_EL1_MASK (UL(0x1) << HFGRTR_EL2_AMAIR_EL1_SHIFT) 1686 #define HFGRTR_EL2_AMAIR_EL1_VAL(x) ((x) & HFGRTR_EL2_AMAIR_EL1_MASK) 1687 #define HFGRTR_EL2_AMAIR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_AMAIR_EL1_SHIFT) 1688 #define HFGRTR_EL2_AMAIR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_AMAIR_EL1_SHIFT) 1689 #define HFGRTR_EL2_AIDR_EL1_SHIFT 2 1690 #define HFGRTR_EL2_AIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_AIDR_EL1_SHIFT) 1691 #define HFGRTR_EL2_AIDR_EL1_VAL(x) ((x) & HFGRTR_EL2_AIDR_EL1_MASK) 1692 #define HFGRTR_EL2_AIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_AIDR_EL1_SHIFT) 1693 #define HFGRTR_EL2_AIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_AIDR_EL1_SHIFT) 1694 #define HFGRTR_EL2_AFSR1_EL1_SHIFT 1 1695 #define HFGRTR_EL2_AFSR1_EL1_MASK (UL(0x1) << HFGRTR_EL2_AFSR1_EL1_SHIFT) 1696 #define HFGRTR_EL2_AFSR1_EL1_VAL(x) ((x) & HFGRTR_EL2_AFSR1_EL1_MASK) 1697 #define HFGRTR_EL2_AFSR1_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_AFSR1_EL1_SHIFT) 1698 #define HFGRTR_EL2_AFSR1_EL1_TRAP (UL(0x1) << HFGRTR_EL2_AFSR1_EL1_SHIFT) 1699 #define HFGRTR_EL2_AFSR0_EL1_SHIFT 0 1700 #define HFGRTR_EL2_AFSR0_EL1_MASK (UL(0x1) << HFGRTR_EL2_AFSR0_EL1_SHIFT) 1701 #define HFGRTR_EL2_AFSR0_EL1_VAL(x) ((x) & HFGRTR_EL2_AFSR0_EL1_MASK) 1702 #define HFGRTR_EL2_AFSR0_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_AFSR0_EL1_SHIFT) 1703 #define HFGRTR_EL2_AFSR0_EL1_TRAP (UL(0x1) << HFGRTR_EL2_AFSR0_EL1_SHIFT) 1704 1705 /* HFGWTR2_EL2 */ 1706 #define HFGWTR2_EL2_REG MRS_REG_ALT_NAME(HFGWTR2_EL2) 1707 #define HFGWTR2_EL2_op0 3 1708 #define HFGWTR2_EL2_op1 4 1709 #define HFGWTR2_EL2_CRn 3 1710 #define HFGWTR2_EL2_CRm 1 1711 #define HFGWTR2_EL2_op2 3 1712 #define HFGWTR2_EL2_nRCWSMASK_EL1_SHIFT 2 1713 #define HFGWTR2_EL2_nRCWSMASK_EL1_MASK (UL(0x1) << HFGWTR2_EL2_nRCWSMASK_EL1_SHIFT) 1714 #define HFGWTR2_EL2_nRCWSMASK_EL1_VAL(x) ((x) & HFGWTR2_EL2_nRCWSMASK_EL1_MASK) 1715 #define HFGWTR2_EL2_nRCWSMASK_EL1_TRAP (UL(0x0) << HFGWTR2_EL2_nRCWSMASK_EL1_SHIFT) 1716 #define HFGWTR2_EL2_nRCWSMASK_EL1_NOTRAP (UL(0x1) << HFGWTR2_EL2_nRCWSMASK_EL1_SHIFT) 1717 #define HFGWTR2_EL2_nPFAR_EL1_SHIFT 0 1718 #define HFGWTR2_EL2_nPFAR_EL1_MASK (UL(0x1) << HFGWTR2_EL2_nPFAR_EL1_SHIFT) 1719 #define HFGWTR2_EL2_nPFAR_EL1_VAL(x) ((x) & HFGWTR2_EL2_nPFAR_EL1_MASK) 1720 #define HFGWTR2_EL2_nPFAR_EL1_TRAP (UL(0x0) << HFGWTR2_EL2_nPFAR_EL1_SHIFT) 1721 #define HFGWTR2_EL2_nPFAR_EL1_NOTRAP (UL(0x1) << HFGWTR2_EL2_nPFAR_EL1_SHIFT) 1722 1723 /* HFGWTR_EL2 */ 1724 #define HFGWTR_EL2_REG MRS_REG_ALT_NAME(HFGWTR_EL2) 1725 #define HFGWTR_EL2_op0 3 1726 #define HFGWTR_EL2_op1 4 1727 #define HFGWTR_EL2_CRn 1 1728 #define HFGWTR_EL2_CRm 1 1729 #define HFGWTR_EL2_op2 5 1730 #define HFGWTR_EL2_nAMAIR2_EL1_SHIFT 63 1731 #define HFGWTR_EL2_nAMAIR2_EL1_MASK (UL(0x1) << HFGWTR_EL2_nAMAIR2_EL1_SHIFT) 1732 #define HFGWTR_EL2_nAMAIR2_EL1_VAL(x) ((x) & HFGWTR_EL2_nAMAIR2_EL1_MASK) 1733 #define HFGWTR_EL2_nAMAIR2_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nAMAIR2_EL1_SHIFT) 1734 #define HFGWTR_EL2_nAMAIR2_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nAMAIR2_EL1_SHIFT) 1735 #define HFGWTR_EL2_nMAIR2_EL1_SHIFT 62 1736 #define HFGWTR_EL2_nMAIR2_EL1_MASK (UL(0x1) << HFGWTR_EL2_nMAIR2_EL1_SHIFT) 1737 #define HFGWTR_EL2_nMAIR2_EL1_VAL(x) ((x) & HFGWTR_EL2_nMAIR2_EL1_MASK) 1738 #define HFGWTR_EL2_nMAIR2_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nMAIR2_EL1_SHIFT) 1739 #define HFGWTR_EL2_nMAIR2_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nMAIR2_EL1_SHIFT) 1740 #define HFGWTR_EL2_nS2POR_EL1_SHIFT 61 1741 #define HFGWTR_EL2_nS2POR_EL1_MASK (UL(0x1) << HFGWTR_EL2_nS2POR_EL1_SHIFT) 1742 #define HFGWTR_EL2_nS2POR_EL1_VAL(x) ((x) & HFGWTR_EL2_nS2POR_EL1_MASK) 1743 #define HFGWTR_EL2_nS2POR_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nS2POR_EL1_SHIFT) 1744 #define HFGWTR_EL2_nS2POR_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nS2POR_EL1_SHIFT) 1745 #define HFGWTR_EL2_nPOR_EL1_SHIFT 60 1746 #define HFGWTR_EL2_nPOR_EL1_MASK (UL(0x1) << HFGWTR_EL2_nPOR_EL1_SHIFT) 1747 #define HFGWTR_EL2_nPOR_EL1_VAL(x) ((x) & HFGWTR_EL2_nPOR_EL1_MASK) 1748 #define HFGWTR_EL2_nPOR_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nPOR_EL1_SHIFT) 1749 #define HFGWTR_EL2_nPOR_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nPOR_EL1_SHIFT) 1750 #define HFGWTR_EL2_nPOR_EL0_SHIFT 59 1751 #define HFGWTR_EL2_nPOR_EL0_MASK (UL(0x1) << HFGWTR_EL2_nPOR_EL0_SHIFT) 1752 #define HFGWTR_EL2_nPOR_EL0_VAL(x) ((x) & HFGWTR_EL2_nPOR_EL0_MASK) 1753 #define HFGWTR_EL2_nPOR_EL0_TRAP (UL(0x0) << HFGWTR_EL2_nPOR_EL0_SHIFT) 1754 #define HFGWTR_EL2_nPOR_EL0_NOTRAP (UL(0x1) << HFGWTR_EL2_nPOR_EL0_SHIFT) 1755 #define HFGWTR_EL2_nPIR_EL1_SHIFT 58 1756 #define HFGWTR_EL2_nPIR_EL1_MASK (UL(0x1) << HFGWTR_EL2_nPIR_EL1_SHIFT) 1757 #define HFGWTR_EL2_nPIR_EL1_VAL(x) ((x) & HFGWTR_EL2_nPIR_EL1_MASK) 1758 #define HFGWTR_EL2_nPIR_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nPIR_EL1_SHIFT) 1759 #define HFGWTR_EL2_nPIR_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nPIR_EL1_SHIFT) 1760 #define HFGWTR_EL2_nPIRE0_EL1_SHIFT 57 1761 #define HFGWTR_EL2_nPIRE0_EL1_MASK (UL(0x1) << HFGWTR_EL2_nPIRE0_EL1_SHIFT) 1762 #define HFGWTR_EL2_nPIRE0_EL1_VAL(x) ((x) & HFGWTR_EL2_nPIRE0_EL1_MASK) 1763 #define HFGWTR_EL2_nPIRE0_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nPIRE0_EL1_SHIFT) 1764 #define HFGWTR_EL2_nPIRE0_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nPIRE0_EL1_SHIFT) 1765 #define HFGWTR_EL2_nRCWMASK_EL1_SHIFT 56 1766 #define HFGWTR_EL2_nRCWMASK_EL1_MASK (UL(0x1) << HFGWTR_EL2_nRCWMASK_EL1_SHIFT) 1767 #define HFGWTR_EL2_nRCWMASK_EL1_VAL(x) ((x) & HFGWTR_EL2_nRCWMASK_EL1_MASK) 1768 #define HFGWTR_EL2_nRCWMASK_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nRCWMASK_EL1_SHIFT) 1769 #define HFGWTR_EL2_nRCWMASK_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nRCWMASK_EL1_SHIFT) 1770 #define HFGWTR_EL2_nTPIDR2_EL0_SHIFT 55 1771 #define HFGWTR_EL2_nTPIDR2_EL0_MASK (UL(0x1) << HFGWTR_EL2_nTPIDR2_EL0_SHIFT) 1772 #define HFGWTR_EL2_nTPIDR2_EL0_VAL(x) ((x) & HFGWTR_EL2_nTPIDR2_EL0_MASK) 1773 #define HFGWTR_EL2_nTPIDR2_EL0_TRAP (UL(0x0) << HFGWTR_EL2_nTPIDR2_EL0_SHIFT) 1774 #define HFGWTR_EL2_nTPIDR2_EL0_NOTRAP (UL(0x1) << HFGWTR_EL2_nTPIDR2_EL0_SHIFT) 1775 #define HFGWTR_EL2_nSMPRI_EL1_SHIFT 54 1776 #define HFGWTR_EL2_nSMPRI_EL1_MASK (UL(0x1) << HFGWTR_EL2_nSMPRI_EL1_SHIFT) 1777 #define HFGWTR_EL2_nSMPRI_EL1_VAL(x) ((x) & HFGWTR_EL2_nSMPRI_EL1_MASK) 1778 #define HFGWTR_EL2_nSMPRI_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nSMPRI_EL1_SHIFT) 1779 #define HFGWTR_EL2_nSMPRI_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nSMPRI_EL1_SHIFT) 1780 #define HFGWTR_EL2_nGCS_EL1_SHIFT 53 1781 #define HFGWTR_EL2_nGCS_EL1_MASK (UL(0x1) << HFGWTR_EL2_nGCS_EL1_SHIFT) 1782 #define HFGWTR_EL2_nGCS_EL1_VAL(x) ((x) & HFGWTR_EL2_nGCS_EL1_MASK) 1783 #define HFGWTR_EL2_nGCS_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nGCS_EL1_SHIFT) 1784 #define HFGWTR_EL2_nGCS_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nGCS_EL1_SHIFT) 1785 #define HFGWTR_EL2_nGCS_EL0_SHIFT 52 1786 #define HFGWTR_EL2_nGCS_EL0_MASK (UL(0x1) << HFGWTR_EL2_nGCS_EL0_SHIFT) 1787 #define HFGWTR_EL2_nGCS_EL0_VAL(x) ((x) & HFGWTR_EL2_nGCS_EL0_MASK) 1788 #define HFGWTR_EL2_nGCS_EL0_TRAP (UL(0x0) << HFGWTR_EL2_nGCS_EL0_SHIFT) 1789 #define HFGWTR_EL2_nGCS_EL0_NOTRAP (UL(0x1) << HFGWTR_EL2_nGCS_EL0_SHIFT) 1790 #define HFGWTR_EL2_nACCDATA_EL1_SHIFT 50 1791 #define HFGWTR_EL2_nACCDATA_EL1_MASK (UL(0x1) << HFGWTR_EL2_nACCDATA_EL1_SHIFT) 1792 #define HFGWTR_EL2_nACCDATA_EL1_VAL(x) ((x) & HFGWTR_EL2_nACCDATA_EL1_MASK) 1793 #define HFGWTR_EL2_nACCDATA_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nACCDATA_EL1_SHIFT) 1794 #define HFGWTR_EL2_nACCDATA_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nACCDATA_EL1_SHIFT) 1795 #define HFGWTR_EL2_ERXADDR_EL1_SHIFT 49 1796 #define HFGWTR_EL2_ERXADDR_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERXADDR_EL1_SHIFT) 1797 #define HFGWTR_EL2_ERXADDR_EL1_VAL(x) ((x) & HFGWTR_EL2_ERXADDR_EL1_MASK) 1798 #define HFGWTR_EL2_ERXADDR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERXADDR_EL1_SHIFT) 1799 #define HFGWTR_EL2_ERXADDR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERXADDR_EL1_SHIFT) 1800 #define HFGWTR_EL2_ERXPFGCDN_EL1_SHIFT 48 1801 #define HFGWTR_EL2_ERXPFGCDN_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERXPFGCDN_EL1_SHIFT) 1802 #define HFGWTR_EL2_ERXPFGCDN_EL1_VAL(x) ((x) & HFGWTR_EL2_ERXPFGCDN_EL1_MASK) 1803 #define HFGWTR_EL2_ERXPFGCDN_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERXPFGCDN_EL1_SHIFT) 1804 #define HFGWTR_EL2_ERXPFGCDN_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERXPFGCDN_EL1_SHIFT) 1805 #define HFGWTR_EL2_ERXPFGCTL_EL1_SHIFT 47 1806 #define HFGWTR_EL2_ERXPFGCTL_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERXPFGCTL_EL1_SHIFT) 1807 #define HFGWTR_EL2_ERXPFGCTL_EL1_VAL(x) ((x) & HFGWTR_EL2_ERXPFGCTL_EL1_MASK) 1808 #define HFGWTR_EL2_ERXPFGCTL_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERXPFGCTL_EL1_SHIFT) 1809 #define HFGWTR_EL2_ERXPFGCTL_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERXPFGCTL_EL1_SHIFT) 1810 #define HFGWTR_EL2_ERXMISCn_EL1_SHIFT 45 1811 #define HFGWTR_EL2_ERXMISCn_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERXMISCn_EL1_SHIFT) 1812 #define HFGWTR_EL2_ERXMISCn_EL1_VAL(x) ((x) & HFGWTR_EL2_ERXMISCn_EL1_MASK) 1813 #define HFGWTR_EL2_ERXMISCn_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERXMISCn_EL1_SHIFT) 1814 #define HFGWTR_EL2_ERXMISCn_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERXMISCn_EL1_SHIFT) 1815 #define HFGWTR_EL2_ERXSTATUS_EL1_SHIFT 44 1816 #define HFGWTR_EL2_ERXSTATUS_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERXSTATUS_EL1_SHIFT) 1817 #define HFGWTR_EL2_ERXSTATUS_EL1_VAL(x) ((x) & HFGWTR_EL2_ERXSTATUS_EL1_MASK) 1818 #define HFGWTR_EL2_ERXSTATUS_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERXSTATUS_EL1_SHIFT) 1819 #define HFGWTR_EL2_ERXSTATUS_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERXSTATUS_EL1_SHIFT) 1820 #define HFGWTR_EL2_ERXCTLR_EL1_SHIFT 43 1821 #define HFGWTR_EL2_ERXCTLR_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERXCTLR_EL1_SHIFT) 1822 #define HFGWTR_EL2_ERXCTLR_EL1_VAL(x) ((x) & HFGWTR_EL2_ERXCTLR_EL1_MASK) 1823 #define HFGWTR_EL2_ERXCTLR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERXCTLR_EL1_SHIFT) 1824 #define HFGWTR_EL2_ERXCTLR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERXCTLR_EL1_SHIFT) 1825 #define HFGWTR_EL2_ERRSELR_EL1_SHIFT 41 1826 #define HFGWTR_EL2_ERRSELR_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERRSELR_EL1_SHIFT) 1827 #define HFGWTR_EL2_ERRSELR_EL1_VAL(x) ((x) & HFGWTR_EL2_ERRSELR_EL1_MASK) 1828 #define HFGWTR_EL2_ERRSELR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERRSELR_EL1_SHIFT) 1829 #define HFGWTR_EL2_ERRSELR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERRSELR_EL1_SHIFT) 1830 #define HFGWTR_EL2_ICC_IGRPENn_EL1_SHIFT 39 1831 #define HFGWTR_EL2_ICC_IGRPENn_EL1_MASK (UL(0x1) << HFGWTR_EL2_ICC_IGRPENn_EL1_SHIFT) 1832 #define HFGWTR_EL2_ICC_IGRPENn_EL1_VAL(x) ((x) & HFGWTR_EL2_ICC_IGRPENn_EL1_MASK) 1833 #define HFGWTR_EL2_ICC_IGRPENn_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ICC_IGRPENn_EL1_SHIFT) 1834 #define HFGWTR_EL2_ICC_IGRPENn_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ICC_IGRPENn_EL1_SHIFT) 1835 #define HFGWTR_EL2_VBAR_EL1_SHIFT 38 1836 #define HFGWTR_EL2_VBAR_EL1_MASK (UL(0x1) << HFGWTR_EL2_VBAR_EL1_SHIFT) 1837 #define HFGWTR_EL2_VBAR_EL1_VAL(x) ((x) & HFGWTR_EL2_VBAR_EL1_MASK) 1838 #define HFGWTR_EL2_VBAR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_VBAR_EL1_SHIFT) 1839 #define HFGWTR_EL2_VBAR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_VBAR_EL1_SHIFT) 1840 #define HFGWTR_EL2_TTBR1_EL1_SHIFT 37 1841 #define HFGWTR_EL2_TTBR1_EL1_MASK (UL(0x1) << HFGWTR_EL2_TTBR1_EL1_SHIFT) 1842 #define HFGWTR_EL2_TTBR1_EL1_VAL(x) ((x) & HFGWTR_EL2_TTBR1_EL1_MASK) 1843 #define HFGWTR_EL2_TTBR1_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_TTBR1_EL1_SHIFT) 1844 #define HFGWTR_EL2_TTBR1_EL1_TRAP (UL(0x1) << HFGWTR_EL2_TTBR1_EL1_SHIFT) 1845 #define HFGWTR_EL2_TTBR0_EL1_SHIFT 36 1846 #define HFGWTR_EL2_TTBR0_EL1_MASK (UL(0x1) << HFGWTR_EL2_TTBR0_EL1_SHIFT) 1847 #define HFGWTR_EL2_TTBR0_EL1_VAL(x) ((x) & HFGWTR_EL2_TTBR0_EL1_MASK) 1848 #define HFGWTR_EL2_TTBR0_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_TTBR0_EL1_SHIFT) 1849 #define HFGWTR_EL2_TTBR0_EL1_TRAP (UL(0x1) << HFGWTR_EL2_TTBR0_EL1_SHIFT) 1850 #define HFGWTR_EL2_TPIDR_EL0_SHIFT 35 1851 #define HFGWTR_EL2_TPIDR_EL0_MASK (UL(0x1) << HFGWTR_EL2_TPIDR_EL0_SHIFT) 1852 #define HFGWTR_EL2_TPIDR_EL0_VAL(x) ((x) & HFGWTR_EL2_TPIDR_EL0_MASK) 1853 #define HFGWTR_EL2_TPIDR_EL0_NOTRAP (UL(0x0) << HFGWTR_EL2_TPIDR_EL0_SHIFT) 1854 #define HFGWTR_EL2_TPIDR_EL0_TRAP (UL(0x1) << HFGWTR_EL2_TPIDR_EL0_SHIFT) 1855 #define HFGWTR_EL2_TPIDRRO_EL0_SHIFT 34 1856 #define HFGWTR_EL2_TPIDRRO_EL0_MASK (UL(0x1) << HFGWTR_EL2_TPIDRRO_EL0_SHIFT) 1857 #define HFGWTR_EL2_TPIDRRO_EL0_VAL(x) ((x) & HFGWTR_EL2_TPIDRRO_EL0_MASK) 1858 #define HFGWTR_EL2_TPIDRRO_EL0_NOTRAP (UL(0x0) << HFGWTR_EL2_TPIDRRO_EL0_SHIFT) 1859 #define HFGWTR_EL2_TPIDRRO_EL0_TRAP (UL(0x1) << HFGWTR_EL2_TPIDRRO_EL0_SHIFT) 1860 #define HFGWTR_EL2_TPIDR_EL1_SHIFT 33 1861 #define HFGWTR_EL2_TPIDR_EL1_MASK (UL(0x1) << HFGWTR_EL2_TPIDR_EL1_SHIFT) 1862 #define HFGWTR_EL2_TPIDR_EL1_VAL(x) ((x) & HFGWTR_EL2_TPIDR_EL1_MASK) 1863 #define HFGWTR_EL2_TPIDR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_TPIDR_EL1_SHIFT) 1864 #define HFGWTR_EL2_TPIDR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_TPIDR_EL1_SHIFT) 1865 #define HFGWTR_EL2_TCR_EL1_SHIFT 32 1866 #define HFGWTR_EL2_TCR_EL1_MASK (UL(0x1) << HFGWTR_EL2_TCR_EL1_SHIFT) 1867 #define HFGWTR_EL2_TCR_EL1_VAL(x) ((x) & HFGWTR_EL2_TCR_EL1_MASK) 1868 #define HFGWTR_EL2_TCR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_TCR_EL1_SHIFT) 1869 #define HFGWTR_EL2_TCR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_TCR_EL1_SHIFT) 1870 #define HFGWTR_EL2_SCXTNUM_EL0_SHIFT 31 1871 #define HFGWTR_EL2_SCXTNUM_EL0_MASK (UL(0x1) << HFGWTR_EL2_SCXTNUM_EL0_SHIFT) 1872 #define HFGWTR_EL2_SCXTNUM_EL0_VAL(x) ((x) & HFGWTR_EL2_SCXTNUM_EL0_MASK) 1873 #define HFGWTR_EL2_SCXTNUM_EL0_NOTRAP (UL(0x0) << HFGWTR_EL2_SCXTNUM_EL0_SHIFT) 1874 #define HFGWTR_EL2_SCXTNUM_EL0_TRAP (UL(0x1) << HFGWTR_EL2_SCXTNUM_EL0_SHIFT) 1875 #define HFGWTR_EL2_SCXTNUM_EL1_SHIFT 30 1876 #define HFGWTR_EL2_SCXTNUM_EL1_MASK (UL(0x1) << HFGWTR_EL2_SCXTNUM_EL1_SHIFT) 1877 #define HFGWTR_EL2_SCXTNUM_EL1_VAL(x) ((x) & HFGWTR_EL2_SCXTNUM_EL1_MASK) 1878 #define HFGWTR_EL2_SCXTNUM_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_SCXTNUM_EL1_SHIFT) 1879 #define HFGWTR_EL2_SCXTNUM_EL1_TRAP (UL(0x1) << HFGWTR_EL2_SCXTNUM_EL1_SHIFT) 1880 #define HFGWTR_EL2_SCTLR_EL1_SHIFT 29 1881 #define HFGWTR_EL2_SCTLR_EL1_MASK (UL(0x1) << HFGWTR_EL2_SCTLR_EL1_SHIFT) 1882 #define HFGWTR_EL2_SCTLR_EL1_VAL(x) ((x) & HFGWTR_EL2_SCTLR_EL1_MASK) 1883 #define HFGWTR_EL2_SCTLR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_SCTLR_EL1_SHIFT) 1884 #define HFGWTR_EL2_SCTLR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_SCTLR_EL1_SHIFT) 1885 #define HFGWTR_EL2_PAR_EL1_SHIFT 27 1886 #define HFGWTR_EL2_PAR_EL1_MASK (UL(0x1) << HFGWTR_EL2_PAR_EL1_SHIFT) 1887 #define HFGWTR_EL2_PAR_EL1_VAL(x) ((x) & HFGWTR_EL2_PAR_EL1_MASK) 1888 #define HFGWTR_EL2_PAR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_PAR_EL1_SHIFT) 1889 #define HFGWTR_EL2_PAR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_PAR_EL1_SHIFT) 1890 #define HFGWTR_EL2_MAIR_EL1_SHIFT 24 1891 #define HFGWTR_EL2_MAIR_EL1_MASK (UL(0x1) << HFGWTR_EL2_MAIR_EL1_SHIFT) 1892 #define HFGWTR_EL2_MAIR_EL1_VAL(x) ((x) & HFGWTR_EL2_MAIR_EL1_MASK) 1893 #define HFGWTR_EL2_MAIR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_MAIR_EL1_SHIFT) 1894 #define HFGWTR_EL2_MAIR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_MAIR_EL1_SHIFT) 1895 #define HFGWTR_EL2_LORSA_EL1_SHIFT 23 1896 #define HFGWTR_EL2_LORSA_EL1_MASK (UL(0x1) << HFGWTR_EL2_LORSA_EL1_SHIFT) 1897 #define HFGWTR_EL2_LORSA_EL1_VAL(x) ((x) & HFGWTR_EL2_LORSA_EL1_MASK) 1898 #define HFGWTR_EL2_LORSA_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_LORSA_EL1_SHIFT) 1899 #define HFGWTR_EL2_LORSA_EL1_TRAP (UL(0x1) << HFGWTR_EL2_LORSA_EL1_SHIFT) 1900 #define HFGWTR_EL2_LORN_EL1_SHIFT 22 1901 #define HFGWTR_EL2_LORN_EL1_MASK (UL(0x1) << HFGWTR_EL2_LORN_EL1_SHIFT) 1902 #define HFGWTR_EL2_LORN_EL1_VAL(x) ((x) & HFGWTR_EL2_LORN_EL1_MASK) 1903 #define HFGWTR_EL2_LORN_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_LORN_EL1_SHIFT) 1904 #define HFGWTR_EL2_LORN_EL1_TRAP (UL(0x1) << HFGWTR_EL2_LORN_EL1_SHIFT) 1905 #define HFGWTR_EL2_LOREA_EL1_SHIFT 20 1906 #define HFGWTR_EL2_LOREA_EL1_MASK (UL(0x1) << HFGWTR_EL2_LOREA_EL1_SHIFT) 1907 #define HFGWTR_EL2_LOREA_EL1_VAL(x) ((x) & HFGWTR_EL2_LOREA_EL1_MASK) 1908 #define HFGWTR_EL2_LOREA_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_LOREA_EL1_SHIFT) 1909 #define HFGWTR_EL2_LOREA_EL1_TRAP (UL(0x1) << HFGWTR_EL2_LOREA_EL1_SHIFT) 1910 #define HFGWTR_EL2_LORC_EL1_SHIFT 19 1911 #define HFGWTR_EL2_LORC_EL1_MASK (UL(0x1) << HFGWTR_EL2_LORC_EL1_SHIFT) 1912 #define HFGWTR_EL2_LORC_EL1_VAL(x) ((x) & HFGWTR_EL2_LORC_EL1_MASK) 1913 #define HFGWTR_EL2_LORC_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_LORC_EL1_SHIFT) 1914 #define HFGWTR_EL2_LORC_EL1_TRAP (UL(0x1) << HFGWTR_EL2_LORC_EL1_SHIFT) 1915 #define HFGWTR_EL2_FAR_EL1_SHIFT 17 1916 #define HFGWTR_EL2_FAR_EL1_MASK (UL(0x1) << HFGWTR_EL2_FAR_EL1_SHIFT) 1917 #define HFGWTR_EL2_FAR_EL1_VAL(x) ((x) & HFGWTR_EL2_FAR_EL1_MASK) 1918 #define HFGWTR_EL2_FAR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_FAR_EL1_SHIFT) 1919 #define HFGWTR_EL2_FAR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_FAR_EL1_SHIFT) 1920 #define HFGWTR_EL2_ESR_EL1_SHIFT 16 1921 #define HFGWTR_EL2_ESR_EL1_MASK (UL(0x1) << HFGWTR_EL2_ESR_EL1_SHIFT) 1922 #define HFGWTR_EL2_ESR_EL1_VAL(x) ((x) & HFGWTR_EL2_ESR_EL1_MASK) 1923 #define HFGWTR_EL2_ESR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ESR_EL1_SHIFT) 1924 #define HFGWTR_EL2_ESR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ESR_EL1_SHIFT) 1925 #define HFGWTR_EL2_CSSELR_EL1_SHIFT 13 1926 #define HFGWTR_EL2_CSSELR_EL1_MASK (UL(0x1) << HFGWTR_EL2_CSSELR_EL1_SHIFT) 1927 #define HFGWTR_EL2_CSSELR_EL1_VAL(x) ((x) & HFGWTR_EL2_CSSELR_EL1_MASK) 1928 #define HFGWTR_EL2_CSSELR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_CSSELR_EL1_SHIFT) 1929 #define HFGWTR_EL2_CSSELR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_CSSELR_EL1_SHIFT) 1930 #define HFGWTR_EL2_CPACR_EL1_SHIFT 12 1931 #define HFGWTR_EL2_CPACR_EL1_MASK (UL(0x1) << HFGWTR_EL2_CPACR_EL1_SHIFT) 1932 #define HFGWTR_EL2_CPACR_EL1_VAL(x) ((x) & HFGWTR_EL2_CPACR_EL1_MASK) 1933 #define HFGWTR_EL2_CPACR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_CPACR_EL1_SHIFT) 1934 #define HFGWTR_EL2_CPACR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_CPACR_EL1_SHIFT) 1935 #define HFGWTR_EL2_CONTEXTIDR_EL1_SHIFT 11 1936 #define HFGWTR_EL2_CONTEXTIDR_EL1_MASK (UL(0x1) << HFGWTR_EL2_CONTEXTIDR_EL1_SHIFT) 1937 #define HFGWTR_EL2_CONTEXTIDR_EL1_VAL(x) ((x) & HFGWTR_EL2_CONTEXTIDR_EL1_MASK) 1938 #define HFGWTR_EL2_CONTEXTIDR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_CONTEXTIDR_EL1_SHIFT) 1939 #define HFGWTR_EL2_CONTEXTIDR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_CONTEXTIDR_EL1_SHIFT) 1940 #define HFGWTR_EL2_APIBKey_SHIFT 8 1941 #define HFGWTR_EL2_APIBKey_MASK (UL(0x1) << HFGWTR_EL2_APIBKey_SHIFT) 1942 #define HFGWTR_EL2_APIBKey_VAL(x) ((x) & HFGWTR_EL2_APIBKey_MASK) 1943 #define HFGWTR_EL2_APIBKey_NOTRAP (UL(0x0) << HFGWTR_EL2_APIBKey_SHIFT) 1944 #define HFGWTR_EL2_APIBKey_TRAP (UL(0x1) << HFGWTR_EL2_APIBKey_SHIFT) 1945 #define HFGWTR_EL2_APIAKey_SHIFT 7 1946 #define HFGWTR_EL2_APIAKey_MASK (UL(0x1) << HFGWTR_EL2_APIAKey_SHIFT) 1947 #define HFGWTR_EL2_APIAKey_VAL(x) ((x) & HFGWTR_EL2_APIAKey_MASK) 1948 #define HFGWTR_EL2_APIAKey_NOTRAP (UL(0x0) << HFGWTR_EL2_APIAKey_SHIFT) 1949 #define HFGWTR_EL2_APIAKey_TRAP (UL(0x1) << HFGWTR_EL2_APIAKey_SHIFT) 1950 #define HFGWTR_EL2_APGAKey_SHIFT 6 1951 #define HFGWTR_EL2_APGAKey_MASK (UL(0x1) << HFGWTR_EL2_APGAKey_SHIFT) 1952 #define HFGWTR_EL2_APGAKey_VAL(x) ((x) & HFGWTR_EL2_APGAKey_MASK) 1953 #define HFGWTR_EL2_APGAKey_NOTRAP (UL(0x0) << HFGWTR_EL2_APGAKey_SHIFT) 1954 #define HFGWTR_EL2_APGAKey_TRAP (UL(0x1) << HFGWTR_EL2_APGAKey_SHIFT) 1955 #define HFGWTR_EL2_APDBKey_SHIFT 5 1956 #define HFGWTR_EL2_APDBKey_MASK (UL(0x1) << HFGWTR_EL2_APDBKey_SHIFT) 1957 #define HFGWTR_EL2_APDBKey_VAL(x) ((x) & HFGWTR_EL2_APDBKey_MASK) 1958 #define HFGWTR_EL2_APDBKey_NOTRAP (UL(0x0) << HFGWTR_EL2_APDBKey_SHIFT) 1959 #define HFGWTR_EL2_APDBKey_TRAP (UL(0x1) << HFGWTR_EL2_APDBKey_SHIFT) 1960 #define HFGWTR_EL2_APDAKey_SHIFT 4 1961 #define HFGWTR_EL2_APDAKey_MASK (UL(0x1) << HFGWTR_EL2_APDAKey_SHIFT) 1962 #define HFGWTR_EL2_APDAKey_VAL(x) ((x) & HFGWTR_EL2_APDAKey_MASK) 1963 #define HFGWTR_EL2_APDAKey_NOTRAP (UL(0x0) << HFGWTR_EL2_APDAKey_SHIFT) 1964 #define HFGWTR_EL2_APDAKey_TRAP (UL(0x1) << HFGWTR_EL2_APDAKey_SHIFT) 1965 #define HFGWTR_EL2_AMAIR_EL1_SHIFT 3 1966 #define HFGWTR_EL2_AMAIR_EL1_MASK (UL(0x1) << HFGWTR_EL2_AMAIR_EL1_SHIFT) 1967 #define HFGWTR_EL2_AMAIR_EL1_VAL(x) ((x) & HFGWTR_EL2_AMAIR_EL1_MASK) 1968 #define HFGWTR_EL2_AMAIR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_AMAIR_EL1_SHIFT) 1969 #define HFGWTR_EL2_AMAIR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_AMAIR_EL1_SHIFT) 1970 #define HFGWTR_EL2_AFSR1_EL1_SHIFT 1 1971 #define HFGWTR_EL2_AFSR1_EL1_MASK (UL(0x1) << HFGWTR_EL2_AFSR1_EL1_SHIFT) 1972 #define HFGWTR_EL2_AFSR1_EL1_VAL(x) ((x) & HFGWTR_EL2_AFSR1_EL1_MASK) 1973 #define HFGWTR_EL2_AFSR1_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_AFSR1_EL1_SHIFT) 1974 #define HFGWTR_EL2_AFSR1_EL1_TRAP (UL(0x1) << HFGWTR_EL2_AFSR1_EL1_SHIFT) 1975 #define HFGWTR_EL2_AFSR0_EL1_SHIFT 0 1976 #define HFGWTR_EL2_AFSR0_EL1_MASK (UL(0x1) << HFGWTR_EL2_AFSR0_EL1_SHIFT) 1977 #define HFGWTR_EL2_AFSR0_EL1_VAL(x) ((x) & HFGWTR_EL2_AFSR0_EL1_MASK) 1978 #define HFGWTR_EL2_AFSR0_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_AFSR0_EL1_SHIFT) 1979 #define HFGWTR_EL2_AFSR0_EL1_TRAP (UL(0x1) << HFGWTR_EL2_AFSR0_EL1_SHIFT) 1980 1981 /* HPFAR_EL2 - Hypervisor IPA Fault Address Register */ 1982 #define HPFAR_EL2_FIPA_SHIFT 4 1983 #define HPFAR_EL2_FIPA_MASK 0xfffffffff0 1984 #define HPFAR_EL2_FIPA_GET(x) \ 1985 (((x) & HPFAR_EL2_FIPA_MASK) >> HPFAR_EL2_FIPA_SHIFT) 1986 /* HPFAR_EL2_FIPA holds the 4k page address */ 1987 #define HPFAR_EL2_FIPA_ADDR(x) \ 1988 (HPFAR_EL2_FIPA_GET(x) << 12) 1989 /* The bits from FAR_EL2 we need to add to HPFAR_EL2_FIPA_ADDR */ 1990 #define FAR_EL2_HPFAR_PAGE_MASK (0xffful) 1991 1992 /* ICC_SRE_EL2 */ 1993 #define ICC_SRE_EL2_SRE (1UL << 0) 1994 #define ICC_SRE_EL2_EN (1UL << 3) 1995 1996 /* MDCR_EL2 - Hyp Debug Control Register */ 1997 #define MDCR_EL2_HPMN_MASK 0x1f 1998 #define MDCR_EL2_HPMN_SHIFT 0 1999 #define MDCR_EL2_TPMCR_SHIFT 5 2000 #define MDCR_EL2_TPMCR (0x1UL << MDCR_EL2_TPMCR_SHIFT) 2001 #define MDCR_EL2_TPM_SHIFT 6 2002 #define MDCR_EL2_TPM (0x1UL << MDCR_EL2_TPM_SHIFT) 2003 #define MDCR_EL2_HPME_SHIFT 7 2004 #define MDCR_EL2_HPME (0x1UL << MDCR_EL2_HPME_SHIFT) 2005 #define MDCR_EL2_TDE_SHIFT 8 2006 #define MDCR_EL2_TDE (0x1UL << MDCR_EL2_TDE_SHIFT) 2007 #define MDCR_EL2_TDA_SHIFT 9 2008 #define MDCR_EL2_TDA (0x1UL << MDCR_EL2_TDA_SHIFT) 2009 #define MDCR_EL2_TDOSA_SHIFT 10 2010 #define MDCR_EL2_TDOSA (0x1UL << MDCR_EL2_TDOSA_SHIFT) 2011 #define MDCR_EL2_TDRA_SHIFT 11 2012 #define MDCR_EL2_TDRA (0x1UL << MDCR_EL2_TDRA_SHIFT) 2013 #define MDCR_EL2_E2PB_SHIFT 12 2014 #define MDCR_EL2_E2PB_MASK (0x3UL << MDCR_EL2_E2PB_SHIFT) 2015 #define MDCR_EL2_E2PB_EL1_0_NO_TRAP (0x3UL << MDCR_EL2_E2PB_SHIFT) 2016 #define MDCR_EL2_TPMS_SHIFT 14 2017 #define MDCR_EL2_TPMS (0x1UL << MDCR_EL2_TPMS_SHIFT) 2018 #define MDCR_EL2_EnSPM_SHIFT 15 2019 #define MDCR_EL2_EnSPM (0x1UL << MDCR_EL2_EnSPM_SHIFT) 2020 #define MDCR_EL2_HPMD_SHIFT 17 2021 #define MDCR_EL2_HPMD (0x1UL << MDCR_EL2_HPMD_SHIFT) 2022 #define MDCR_EL2_TTRF_SHIFT 19 2023 #define MDCR_EL2_TTRF (0x1UL << MDCR_EL2_TTRF_SHIFT) 2024 #define MDCR_EL2_HCCD_SHIFT 23 2025 #define MDCR_EL2_HCCD (0x1UL << MDCR_EL2_HCCD_SHIFT) 2026 #define MDCR_EL2_E2TB_SHIFT 24 2027 #define MDCR_EL2_E2TB_MASK (0x3UL << MDCR_EL2_E2TB_SHIFT) 2028 #define MDCR_EL2_HLP_SHIFT 26 2029 #define MDCR_EL2_HLP (0x1UL << MDCR_EL2_HLP_SHIFT) 2030 #define MDCR_EL2_TDCC_SHIFT 27 2031 #define MDCR_EL2_TDCC (0x1UL << MDCR_EL2_TDCC_SHIFT) 2032 #define MDCR_EL2_MTPME_SHIFT 28 2033 #define MDCR_EL2_MTPME (0x1UL << MDCR_EL2_MTPME_SHIFT) 2034 #define MDCR_EL2_HPMFZO_SHIFT 29 2035 #define MDCR_EL2_HPMFZO (0x1UL << MDCR_EL2_HPMFZO_SHIFT) 2036 #define MDCR_EL2_PMSSE_SHIFT 30 2037 #define MDCR_EL2_PMSSE_MASK (0x3UL << MDCR_EL2_PMSSE_SHIFT) 2038 #define MDCR_EL2_HPMFZS_SHIFT 36 2039 #define MDCR_EL2_HPMFZS (0x1UL << MDCR_EL2_HPMFZS_SHIFT) 2040 #define MDCR_EL2_PMEE_SHIFT 40 2041 #define MDCR_EL2_PMEE_MASK (0x3UL << MDCR_EL2_PMEE_SHIFT) 2042 #define MDCR_EL2_EBWE_SHIFT 43 2043 #define MDCR_EL2_EBWE (0x1UL << MDCR_EL2_EBWE_SHIFT) 2044 2045 /* SCTLR_EL2 - System Control Register */ 2046 #define SCTLR_EL2_RES1 0x30c50830 2047 #define SCTLR_EL2_M_SHIFT 0 2048 #define SCTLR_EL2_M (0x1UL << SCTLR_EL2_M_SHIFT) 2049 #define SCTLR_EL2_A_SHIFT 1 2050 #define SCTLR_EL2_A (0x1UL << SCTLR_EL2_A_SHIFT) 2051 #define SCTLR_EL2_C_SHIFT 2 2052 #define SCTLR_EL2_C (0x1UL << SCTLR_EL2_C_SHIFT) 2053 #define SCTLR_EL2_SA_SHIFT 3 2054 #define SCTLR_EL2_SA (0x1UL << SCTLR_EL2_SA_SHIFT) 2055 #define SCTLR_EL2_EOS_SHIFT 11 2056 #define SCTLR_EL2_EOS (0x1UL << SCTLR_EL2_EOS_SHIFT) 2057 #define SCTLR_EL2_I_SHIFT 12 2058 #define SCTLR_EL2_I (0x1UL << SCTLR_EL2_I_SHIFT) 2059 #define SCTLR_EL2_WXN_SHIFT 19 2060 #define SCTLR_EL2_WXN (0x1UL << SCTLR_EL2_WXN_SHIFT) 2061 #define SCTLR_EL2_EIS_SHIFT 22 2062 #define SCTLR_EL2_EIS (0x1UL << SCTLR_EL2_EIS_SHIFT) 2063 #define SCTLR_EL2_EE_SHIFT 25 2064 #define SCTLR_EL2_EE (0x1UL << SCTLR_EL2_EE_SHIFT) 2065 2066 /* TCR_EL2 - Translation Control Register */ 2067 #define TCR_EL2_RES1 ((0x1UL << 31) | (0x1UL << 23)) 2068 #define TCR_EL2_T0SZ_SHIFT 0 2069 #define TCR_EL2_T0SZ_MASK (0x3fUL << TCR_EL2_T0SZ_SHIFT) 2070 #define TCR_EL2_T0SZ(x) ((x) << TCR_EL2_T0SZ_SHIFT) 2071 /* Bits 7:6 are reserved */ 2072 #define TCR_EL2_IRGN0_SHIFT 8 2073 #define TCR_EL2_IRGN0_MASK (0x3UL << TCR_EL2_IRGN0_SHIFT) 2074 #define TCR_EL2_IRGN0_WBWA (1UL << TCR_EL2_IRGN0_SHIFT) 2075 #define TCR_EL2_ORGN0_SHIFT 10 2076 #define TCR_EL2_ORGN0_MASK (0x3UL << TCR_EL2_ORGN0_SHIFT) 2077 #define TCR_EL2_ORGN0_WBWA (1UL << TCR_EL2_ORGN0_SHIFT) 2078 #define TCR_EL2_SH0_SHIFT 12 2079 #define TCR_EL2_SH0_MASK (0x3UL << TCR_EL2_SH0_SHIFT) 2080 #define TCR_EL2_SH0_IS (3UL << TCR_EL2_SH0_SHIFT) 2081 #define TCR_EL2_TG0_SHIFT 14 2082 #define TCR_EL2_TG0_MASK (0x3UL << TCR_EL2_TG0_SHIFT) 2083 #define TCR_EL2_TG0_4K (0x0UL << TCR_EL2_TG0_SHIFT) 2084 #define TCR_EL2_TG0_64K (0x1UL << TCR_EL2_TG0_SHIFT) 2085 #define TCR_EL2_TG0_16K (0x2UL << TCR_EL2_TG0_SHIFT) 2086 #define TCR_EL2_PS_SHIFT 16 2087 #define TCR_EL2_PS_MASK (0xfUL << TCR_EL2_PS_SHIFT) 2088 #define TCR_EL2_PS_32BITS (0UL << TCR_EL2_PS_SHIFT) 2089 #define TCR_EL2_PS_36BITS (1UL << TCR_EL2_PS_SHIFT) 2090 #define TCR_EL2_PS_40BITS (2UL << TCR_EL2_PS_SHIFT) 2091 #define TCR_EL2_PS_42BITS (3UL << TCR_EL2_PS_SHIFT) 2092 #define TCR_EL2_PS_44BITS (4UL << TCR_EL2_PS_SHIFT) 2093 #define TCR_EL2_PS_48BITS (5UL << TCR_EL2_PS_SHIFT) 2094 #define TCR_EL2_PS_52BITS (6UL << TCR_EL2_PS_SHIFT) 2095 #define TCR_EL2_HPD_SHIFT 24 2096 #define TCR_EL2_HPD (1UL << TCR_EL2_HPD_SHIFT) 2097 #define TCR_EL2_HWU59_SHIFT 25 2098 #define TCR_EL2_HWU59 (1UL << TCR_EL2_HWU59_SHIFT) 2099 #define TCR_EL2_HWU60_SHIFT 26 2100 #define TCR_EL2_HWU60 (1UL << TCR_EL2_HWU60_SHIFT) 2101 #define TCR_EL2_HWU61_SHIFT 27 2102 #define TCR_EL2_HWU61 (1UL << TCR_EL2_HWU61_SHIFT) 2103 #define TCR_EL2_HWU62_SHIFT 28 2104 #define TCR_EL2_HWU62 (1UL << TCR_EL2_HWU62_SHIFT) 2105 #define TCR_EL2_HWU \ 2106 (TCR_EL2_HWU59 | TCR_EL2_HWU60 | TCR_EL2_HWU61 | TCR_EL2_HWU62) 2107 2108 /* VMPDIR_EL2 - Virtualization Multiprocessor ID Register */ 2109 #define VMPIDR_EL2_U 0x0000000040000000 2110 #define VMPIDR_EL2_MT 0x0000000001000000 2111 #define VMPIDR_EL2_RES1 0x0000000080000000 2112 2113 /* VTCR_EL2 - Virtualization Translation Control Register */ 2114 #define VTCR_EL2_RES1 (0x1UL << 31) 2115 #define VTCR_EL2_T0SZ_SHIFT 0 2116 #define VTCR_EL2_T0SZ_MASK (0x3fUL << VTCR_EL2_T0SZ_SHIFT) 2117 #define VTCR_EL2_T0SZ(x) ((x) << VTCR_EL2_T0SZ_SHIFT) 2118 #define VTCR_EL2_SL0_SHIFT 6 2119 #define VTCR_EL2_SL0_4K_LVL2 (0x0UL << VTCR_EL2_SL0_SHIFT) 2120 #define VTCR_EL2_SL0_4K_LVL1 (0x1UL << VTCR_EL2_SL0_SHIFT) 2121 #define VTCR_EL2_SL0_4K_LVL0 (0x2UL << VTCR_EL2_SL0_SHIFT) 2122 #define VTCR_EL2_SL0_16K_LVL2 (0x1UL << VTCR_EL2_SL0_SHIFT) 2123 #define VTCR_EL2_SL0_16K_LVL1 (0x2UL << VTCR_EL2_SL0_SHIFT) 2124 #define VTCR_EL2_SL0_16K_LVL0 (0x3UL << VTCR_EL2_SL0_SHIFT) 2125 #define VTCR_EL2_IRGN0_SHIFT 8 2126 #define VTCR_EL2_IRGN0_WBWA (0x1UL << VTCR_EL2_IRGN0_SHIFT) 2127 #define VTCR_EL2_ORGN0_SHIFT 10 2128 #define VTCR_EL2_ORGN0_WBWA (0x1UL << VTCR_EL2_ORGN0_SHIFT) 2129 #define VTCR_EL2_SH0_SHIFT 12 2130 #define VTCR_EL2_SH0_NS (0x0UL << VTCR_EL2_SH0_SHIFT) 2131 #define VTCR_EL2_SH0_OS (0x2UL << VTCR_EL2_SH0_SHIFT) 2132 #define VTCR_EL2_SH0_IS (0x3UL << VTCR_EL2_SH0_SHIFT) 2133 #define VTCR_EL2_TG0_SHIFT 14 2134 #define VTCR_EL2_TG0_4K (0x0UL << VTCR_EL2_TG0_SHIFT) 2135 #define VTCR_EL2_TG0_64K (0x1UL << VTCR_EL2_TG0_SHIFT) 2136 #define VTCR_EL2_TG0_16K (0x2UL << VTCR_EL2_TG0_SHIFT) 2137 #define VTCR_EL2_PS_SHIFT 16 2138 #define VTCR_EL2_PS_32BIT (0x0UL << VTCR_EL2_PS_SHIFT) 2139 #define VTCR_EL2_PS_36BIT (0x1UL << VTCR_EL2_PS_SHIFT) 2140 #define VTCR_EL2_PS_40BIT (0x2UL << VTCR_EL2_PS_SHIFT) 2141 #define VTCR_EL2_PS_42BIT (0x3UL << VTCR_EL2_PS_SHIFT) 2142 #define VTCR_EL2_PS_44BIT (0x4UL << VTCR_EL2_PS_SHIFT) 2143 #define VTCR_EL2_PS_48BIT (0x5UL << VTCR_EL2_PS_SHIFT) 2144 #define VTCR_EL2_PS_52BIT (0x6UL << VTCR_EL2_PS_SHIFT) 2145 #define VTCR_EL2_DS_SHIFT 32 2146 #define VTCR_EL2_DS (0x1UL << VTCR_EL2_DS_SHIFT) 2147 2148 /* VTTBR_EL2 - Virtualization Translation Table Base Register */ 2149 #define VTTBR_VMID_MASK 0xffff000000000000 2150 #define VTTBR_VMID_SHIFT 48 2151 /* Assumed to be 0 by locore.S */ 2152 #define VTTBR_HOST 0x0000000000000000 2153 2154 #endif /* !_MACHINE_HYPERVISOR_H_ */ 2155