1 /*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2021 The FreeBSD Foundation 4 * 5 * Portions of this software were developed by Andrew Turner 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef _MACHINE_HYPERVISOR_H_ 31 #define _MACHINE_HYPERVISOR_H_ 32 33 /* 34 * These registers are only useful when in hypervisor context, 35 * e.g. specific to EL2, or controlling the hypervisor. 36 */ 37 38 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */ 39 #define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ 40 /* Valid if HCR_EL2.E2H == 0 */ 41 #define CNTHCTL_EL1PCTEN (1 << 0) /* Allow physical counter access */ 42 #define CNTHCTL_EL1PCEN (1 << 1) /* Allow physical timer access */ 43 /* Valid if HCR_EL2.E2H == 1 */ 44 #define CNTHCTL_E2H_EL0PCTEN (1 << 0) /* Allow EL0 physical counter access */ 45 #define CNTHCTL_E2H_EL0VCTEN (1 << 1) /* Allow EL0 virtual counter access */ 46 #define CNTHCTL_E2H_EL0VTEN (1 << 8) 47 #define CNTHCTL_E2H_EL0PTEN (1 << 9) 48 #define CNTHCTL_E2H_EL1PCTEN (1 << 10) /* Allow physical counter access */ 49 #define CNTHCTL_E2H_EL1PTEN (1 << 11) /* Allow physical timer access */ 50 /* Unconditionally valid */ 51 #define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ 52 #define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ 53 54 /* CPTR_EL2 - Architecture feature trap register */ 55 /* Valid if HCR_EL2.E2H == 0 */ 56 #define CPTR_RES0 0x7fefc800 57 #define CPTR_RES1 0x000033ff 58 #define CPTR_TFP 0x00000400 59 /* Valid if HCR_EL2.E2H == 1 */ 60 #define CPTR_FPEN 0x00300000 61 /* Unconditionally valid */ 62 #define CPTR_TTA 0x00100000 63 #define CPTR_TCPAC 0x80000000 64 65 /* HCR_EL2 - Hypervisor Config Register */ 66 #define HCR_VM (UL(0x1) << 0) 67 #define HCR_SWIO (UL(0x1) << 1) 68 #define HCR_PTW (UL(0x1) << 2) 69 #define HCR_FMO (UL(0x1) << 3) 70 #define HCR_IMO (UL(0x1) << 4) 71 #define HCR_AMO (UL(0x1) << 5) 72 #define HCR_VF (UL(0x1) << 6) 73 #define HCR_VI (UL(0x1) << 7) 74 #define HCR_VSE (UL(0x1) << 8) 75 #define HCR_FB (UL(0x1) << 9) 76 #define HCR_BSU_MASK (UL(0x3) << 10) 77 #define HCR_BSU_IS (UL(0x1) << 10) 78 #define HCR_BSU_OS (UL(0x2) << 10) 79 #define HCR_BSU_FS (UL(0x3) << 10) 80 #define HCR_DC (UL(0x1) << 12) 81 #define HCR_TWI (UL(0x1) << 13) 82 #define HCR_TWE (UL(0x1) << 14) 83 #define HCR_TID0 (UL(0x1) << 15) 84 #define HCR_TID1 (UL(0x1) << 16) 85 #define HCR_TID2 (UL(0x1) << 17) 86 #define HCR_TID3 (UL(0x1) << 18) 87 #define HCR_TSC (UL(0x1) << 19) 88 #define HCR_TIDCP (UL(0x1) << 20) 89 #define HCR_TACR (UL(0x1) << 21) 90 #define HCR_TSW (UL(0x1) << 22) 91 #define HCR_TPCP (UL(0x1) << 23) 92 #define HCR_TPU (UL(0x1) << 24) 93 #define HCR_TTLB (UL(0x1) << 25) 94 #define HCR_TVM (UL(0x1) << 26) 95 #define HCR_TGE (UL(0x1) << 27) 96 #define HCR_TDZ (UL(0x1) << 28) 97 #define HCR_HCD (UL(0x1) << 29) 98 #define HCR_TRVM (UL(0x1) << 30) 99 #define HCR_RW (UL(0x1) << 31) 100 #define HCR_CD (UL(0x1) << 32) 101 #define HCR_ID (UL(0x1) << 33) 102 #define HCR_E2H (UL(0x1) << 34) 103 #define HCR_TLOR (UL(0x1) << 35) 104 #define HCR_TERR (UL(0x1) << 36) 105 #define HCR_TEA (UL(0x1) << 37) 106 #define HCR_MIOCNCE (UL(0x1) << 38) 107 /* Bit 39 is reserved */ 108 #define HCR_APK (UL(0x1) << 40) 109 #define HCR_API (UL(0x1) << 41) 110 #define HCR_NV (UL(0x1) << 42) 111 #define HCR_NV1 (UL(0x1) << 43) 112 #define HCR_AT (UL(0x1) << 44) 113 #define HCR_NV2 (UL(0x1) << 45) 114 #define HCR_FWB (UL(0x1) << 46) 115 #define HCR_FIEN (UL(0x1) << 47) 116 /* Bit 48 is reserved */ 117 #define HCR_TID4 (UL(0x1) << 49) 118 #define HCR_TICAB (UL(0x1) << 50) 119 #define HCR_AMVOFFEN (UL(0x1) << 51) 120 #define HCR_TOCU (UL(0x1) << 52) 121 #define HCR_EnSCXT (UL(0x1) << 53) 122 #define HCR_TTLBIS (UL(0x1) << 54) 123 #define HCR_TTLBOS (UL(0x1) << 55) 124 #define HCR_ATA (UL(0x1) << 56) 125 #define HCR_DCT (UL(0x1) << 57) 126 #define HCR_TID5 (UL(0x1) << 58) 127 #define HCR_TWEDEn (UL(0x1) << 59) 128 #define HCR_TWEDEL_MASK (UL(0xf) << 60) 129 130 /* HPFAR_EL2 - Hypervisor IPA Fault Address Register */ 131 #define HPFAR_EL2_FIPA_SHIFT 4 132 #define HPFAR_EL2_FIPA_MASK 0xfffffffff0 133 #define HPFAR_EL2_FIPA_GET(x) \ 134 (((x) & HPFAR_EL2_FIPA_MASK) >> HPFAR_EL2_FIPA_SHIFT) 135 /* HPFAR_EL2_FIPA holds the 4k page address */ 136 #define HPFAR_EL2_FIPA_ADDR(x) \ 137 (HPFAR_EL2_FIPA_GET(x) << 12) 138 /* The bits from FAR_EL2 we need to add to HPFAR_EL2_FIPA_ADDR */ 139 #define FAR_EL2_HPFAR_PAGE_MASK (0xffful) 140 141 /* ICC_SRE_EL2 */ 142 #define ICC_SRE_EL2_SRE (1UL << 0) 143 #define ICC_SRE_EL2_EN (1UL << 3) 144 145 /* SCTLR_EL2 - System Control Register */ 146 #define SCTLR_EL2_RES1 0x30c50830 147 #define SCTLR_EL2_M_SHIFT 0 148 #define SCTLR_EL2_M (0x1UL << SCTLR_EL2_M_SHIFT) 149 #define SCTLR_EL2_A_SHIFT 1 150 #define SCTLR_EL2_A (0x1UL << SCTLR_EL2_A_SHIFT) 151 #define SCTLR_EL2_C_SHIFT 2 152 #define SCTLR_EL2_C (0x1UL << SCTLR_EL2_C_SHIFT) 153 #define SCTLR_EL2_SA_SHIFT 3 154 #define SCTLR_EL2_SA (0x1UL << SCTLR_EL2_SA_SHIFT) 155 #define SCTLR_EL2_EOS_SHIFT 11 156 #define SCTLR_EL2_EOS (0x1UL << SCTLR_EL2_EOS_SHIFT) 157 #define SCTLR_EL2_I_SHIFT 12 158 #define SCTLR_EL2_I (0x1UL << SCTLR_EL2_I_SHIFT) 159 #define SCTLR_EL2_WXN_SHIFT 19 160 #define SCTLR_EL2_WXN (0x1UL << SCTLR_EL2_WXN_SHIFT) 161 #define SCTLR_EL2_EIS_SHIFT 22 162 #define SCTLR_EL2_EIS (0x1UL << SCTLR_EL2_EIS_SHIFT) 163 #define SCTLR_EL2_EE_SHIFT 25 164 #define SCTLR_EL2_EE (0x1UL << SCTLR_EL2_EE_SHIFT) 165 166 /* TCR_EL2 - Translation Control Register */ 167 #define TCR_EL2_RES1 ((0x1UL << 31) | (0x1UL << 23)) 168 #define TCR_EL2_T0SZ_SHIFT 0 169 #define TCR_EL2_T0SZ_MASK (0x3fUL << TCR_EL2_T0SZ_SHIFT) 170 #define TCR_EL2_T0SZ(x) ((x) << TCR_EL2_T0SZ_SHIFT) 171 /* Bits 7:6 are reserved */ 172 #define TCR_EL2_IRGN0_SHIFT 8 173 #define TCR_EL2_IRGN0_MASK (0x3UL << TCR_EL2_IRGN0_SHIFT) 174 #define TCR_EL2_IRGN0_WBWA (1UL << TCR_EL2_IRGN0_SHIFT) 175 #define TCR_EL2_ORGN0_SHIFT 10 176 #define TCR_EL2_ORGN0_MASK (0x3UL << TCR_EL2_ORGN0_SHIFT) 177 #define TCR_EL2_ORGN0_WBWA (1UL << TCR_EL2_ORGN0_SHIFT) 178 #define TCR_EL2_SH0_SHIFT 12 179 #define TCR_EL2_SH0_MASK (0x3UL << TCR_EL2_SH0_SHIFT) 180 #define TCR_EL2_SH0_IS (3UL << TCR_EL2_SH0_SHIFT) 181 #define TCR_EL2_TG0_SHIFT 14 182 #define TCR_EL2_TG0_MASK (0x3UL << TCR_EL2_TG0_SHIFT) 183 #define TCR_EL2_TG0_4K (0x0UL << TCR_EL2_TG0_SHIFT) 184 #define TCR_EL2_TG0_64K (0x1UL << TCR_EL2_TG0_SHIFT) 185 #define TCR_EL2_TG0_16K (0x2UL << TCR_EL2_TG0_SHIFT) 186 #define TCR_EL2_PS_SHIFT 16 187 #define TCR_EL2_PS_MASK (0xfUL << TCR_EL2_PS_SHIFT) 188 #define TCR_EL2_PS_32BITS (0UL << TCR_EL2_PS_SHIFT) 189 #define TCR_EL2_PS_36BITS (1UL << TCR_EL2_PS_SHIFT) 190 #define TCR_EL2_PS_40BITS (2UL << TCR_EL2_PS_SHIFT) 191 #define TCR_EL2_PS_42BITS (3UL << TCR_EL2_PS_SHIFT) 192 #define TCR_EL2_PS_44BITS (4UL << TCR_EL2_PS_SHIFT) 193 #define TCR_EL2_PS_48BITS (5UL << TCR_EL2_PS_SHIFT) 194 #define TCR_EL2_PS_52BITS (6UL << TCR_EL2_PS_SHIFT) 195 #define TCR_EL2_HPD_SHIFT 24 196 #define TCR_EL2_HPD (1UL << TCR_EL2_HPD_SHIFT) 197 #define TCR_EL2_HWU59_SHIFT 25 198 #define TCR_EL2_HWU59 (1UL << TCR_EL2_HWU59_SHIFT) 199 #define TCR_EL2_HWU60_SHIFT 26 200 #define TCR_EL2_HWU60 (1UL << TCR_EL2_HWU60_SHIFT) 201 #define TCR_EL2_HWU61_SHIFT 27 202 #define TCR_EL2_HWU61 (1UL << TCR_EL2_HWU61_SHIFT) 203 #define TCR_EL2_HWU62_SHIFT 28 204 #define TCR_EL2_HWU62 (1UL << TCR_EL2_HWU62_SHIFT) 205 #define TCR_EL2_HWU \ 206 (TCR_EL2_HWU59 | TCR_EL2_HWU60 | TCR_EL2_HWU61 | TCR_EL2_HWU62) 207 208 /* VMPDIR_EL2 - Virtualization Multiprocessor ID Register */ 209 #define VMPIDR_EL2_U 0x0000000040000000 210 #define VMPIDR_EL2_MT 0x0000000001000000 211 #define VMPIDR_EL2_RES1 0x0000000080000000 212 213 /* VTCR_EL2 - Virtualization Translation Control Register */ 214 #define VTCR_EL2_RES1 (0x1UL << 31) 215 #define VTCR_EL2_T0SZ_SHIFT 0 216 #define VTCR_EL2_T0SZ_MASK (0x3fUL << VTCR_EL2_T0SZ_SHIFT) 217 #define VTCR_EL2_T0SZ(x) ((x) << VTCR_EL2_T0SZ_SHIFT) 218 #define VTCR_EL2_SL0_SHIFT 6 219 #define VTCR_EL2_SL0_4K_LVL2 (0x0UL << VTCR_EL2_SL0_SHIFT) 220 #define VTCR_EL2_SL0_4K_LVL1 (0x1UL << VTCR_EL2_SL0_SHIFT) 221 #define VTCR_EL2_SL0_4K_LVL0 (0x2UL << VTCR_EL2_SL0_SHIFT) 222 #define VTCR_EL2_SL0_16K_LVL2 (0x1UL << VTCR_EL2_SL0_SHIFT) 223 #define VTCR_EL2_SL0_16K_LVL1 (0x2UL << VTCR_EL2_SL0_SHIFT) 224 #define VTCR_EL2_SL0_16K_LVL0 (0x3UL << VTCR_EL2_SL0_SHIFT) 225 #define VTCR_EL2_IRGN0_SHIFT 8 226 #define VTCR_EL2_IRGN0_WBWA (0x1UL << VTCR_EL2_IRGN0_SHIFT) 227 #define VTCR_EL2_ORGN0_SHIFT 10 228 #define VTCR_EL2_ORGN0_WBWA (0x1UL << VTCR_EL2_ORGN0_SHIFT) 229 #define VTCR_EL2_SH0_SHIFT 12 230 #define VTCR_EL2_SH0_NS (0x0UL << VTCR_EL2_SH0_SHIFT) 231 #define VTCR_EL2_SH0_OS (0x2UL << VTCR_EL2_SH0_SHIFT) 232 #define VTCR_EL2_SH0_IS (0x3UL << VTCR_EL2_SH0_SHIFT) 233 #define VTCR_EL2_TG0_SHIFT 14 234 #define VTCR_EL2_TG0_4K (0x0UL << VTCR_EL2_TG0_SHIFT) 235 #define VTCR_EL2_TG0_64K (0x1UL << VTCR_EL2_TG0_SHIFT) 236 #define VTCR_EL2_TG0_16K (0x2UL << VTCR_EL2_TG0_SHIFT) 237 #define VTCR_EL2_PS_SHIFT 16 238 #define VTCR_EL2_PS_32BIT (0x0UL << VTCR_EL2_PS_SHIFT) 239 #define VTCR_EL2_PS_36BIT (0x1UL << VTCR_EL2_PS_SHIFT) 240 #define VTCR_EL2_PS_40BIT (0x2UL << VTCR_EL2_PS_SHIFT) 241 #define VTCR_EL2_PS_42BIT (0x3UL << VTCR_EL2_PS_SHIFT) 242 #define VTCR_EL2_PS_44BIT (0x4UL << VTCR_EL2_PS_SHIFT) 243 #define VTCR_EL2_PS_48BIT (0x5UL << VTCR_EL2_PS_SHIFT) 244 245 /* VTTBR_EL2 - Virtualization Translation Table Base Register */ 246 #define VTTBR_VMID_MASK 0xffff000000000000 247 #define VTTBR_VMID_SHIFT 48 248 /* Assumed to be 0 by locore.S */ 249 #define VTTBR_HOST 0x0000000000000000 250 251 /* MDCR_EL2 - Hyp Debug Control Register */ 252 #define MDCR_EL2_HPMN_MASK 0x1f 253 #define MDCR_EL2_HPMN_SHIFT 0 254 #define MDCR_EL2_TPMCR_SHIFT 5 255 #define MDCR_EL2_TPMCR (0x1UL << MDCR_EL2_TPMCR_SHIFT) 256 #define MDCR_EL2_TPM_SHIFT 6 257 #define MDCR_EL2_TPM (0x1UL << MDCR_EL2_TPM_SHIFT) 258 #define MDCR_EL2_HPME_SHIFT 7 259 #define MDCR_EL2_HPME (0x1UL << MDCR_EL2_HPME_SHIFT) 260 #define MDCR_EL2_TDE_SHIFT 8 261 #define MDCR_EL2_TDE (0x1UL << MDCR_EL2_TDE_SHIFT) 262 #define MDCR_EL2_TDA_SHIFT 9 263 #define MDCR_EL2_TDA (0x1UL << MDCR_EL2_TDA_SHIFT) 264 #define MDCR_EL2_TDOSA_SHIFT 10 265 #define MDCR_EL2_TDOSA (0x1UL << MDCR_EL2_TDOSA_SHIFT) 266 #define MDCR_EL2_TDRA_SHIFT 11 267 #define MDCR_EL2_TDRA (0x1UL << MDCR_EL2_TDRA_SHIFT) 268 269 #endif /* !_MACHINE_HYPERVISOR_H_ */ 270