1 /*- 2 * Copyright (c) 2015 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Semihalf under 6 * the sponsorship of the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* PCIe external MAC root complex driver (PEM) for Cavium Thunder SOC */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include "opt_platform.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/rman.h> 44 #include <sys/endian.h> 45 46 #ifdef FDT 47 #include <dev/ofw/openfirm.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 #include <dev/ofw/ofw_pci.h> 51 #endif 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pci_host_generic.h> 56 #include <dev/pci/pcib_private.h> 57 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 #include <machine/smp.h> 61 #include <machine/intr.h> 62 63 #include <arm64/cavium/thunder_pcie_common.h> 64 #include <arm64/cavium/thunder_pcie_pem.h> 65 #include "pcib_if.h" 66 67 #define THUNDER_PEM_DEVICE_ID 0xa020 68 #define THUNDER_PEM_VENDOR_ID 0x177d 69 70 /* ThunderX specific defines */ 71 #define THUNDER_PEMn_REG_BASE(unit) (0x87e0c0000000UL | ((unit) << 24)) 72 #define PCIERC_CFG002 0x08 73 #define PCIERC_CFG006 0x18 74 #define PCIERC_CFG032 0x80 75 #define PCIERC_CFG006_SEC_BUS(reg) (((reg) >> 8) & 0xFF) 76 #define PEM_CFG_RD_REG_ALIGN(reg) ((reg) & ~0x3) 77 #define PEM_CFG_RD_REG_DATA(val) (((val) >> 32) & 0xFFFFFFFF) 78 #define PEM_CFG_RD 0x30 79 #define PEM_CFG_LINK_MASK 0x3 80 #define PEM_CFG_LINK_RDY 0x3 81 #define PEM_CFG_SLIX_TO_REG(slix) ((slix) << 4) 82 #define SBNUM_OFFSET 0x8 83 #define SBNUM_MASK 0xFF 84 #define PEM_ON_REG 0x420 85 #define PEM_CTL_STATUS 0x0 86 #define PEM_LINK_ENABLE (1 << 4) 87 #define PEM_LINK_DLLA (1 << 29) 88 #define PEM_LINK_LT (1 << 27) 89 #define PEM_BUS_SHIFT (24) 90 #define PEM_SLOT_SHIFT (19) 91 #define PEM_FUNC_SHIFT (16) 92 #define SLIX_S2M_REGX_ACC 0x874001000000UL 93 #define SLIX_S2M_REGX_ACC_SIZE 0x1000 94 #define SLIX_S2M_REGX_ACC_SPACING 0x001000000000UL 95 #define SLI_BASE 0x880000000000UL 96 #define SLI_WINDOW_SPACING 0x004000000000UL 97 #define SLI_PCI_OFFSET 0x001000000000UL 98 #define SLI_NODE_SHIFT (44) 99 #define SLI_NODE_MASK (3) 100 #define SLI_GROUP_SHIFT (40) 101 #define SLI_ID_SHIFT (24) 102 #define SLI_ID_MASK (7) 103 #define SLI_PEMS_PER_GROUP (3) 104 #define SLI_GROUPS_PER_NODE (2) 105 #define SLI_PEMS_PER_NODE (SLI_PEMS_PER_GROUP * SLI_GROUPS_PER_NODE) 106 #define SLI_ACC_REG_CNT (256) 107 108 /* 109 * Each PEM device creates its own bus with 110 * own address translation, so we can adjust bus addresses 111 * as we want. To support 32-bit cards let's assume 112 * PCI window assignment looks as following: 113 * 114 * 0x00000000 - 0x000FFFFF IO 115 * 0x00100000 - 0xFFFFFFFF Memory 116 */ 117 #define PCI_IO_BASE 0x00000000UL 118 #define PCI_IO_SIZE 0x00100000UL 119 #define PCI_MEMORY_BASE PCI_IO_SIZE 120 #define PCI_MEMORY_SIZE 0xFFF00000UL 121 122 #define RID_PEM_SPACE 1 123 124 static int thunder_pem_activate_resource(device_t, device_t, int, int, 125 struct resource *); 126 static int thunder_pem_adjust_resource(device_t, device_t, int, 127 struct resource *, rman_res_t, rman_res_t); 128 static struct resource * thunder_pem_alloc_resource(device_t, device_t, int, 129 int *, rman_res_t, rman_res_t, rman_res_t, u_int); 130 static int thunder_pem_alloc_msi(device_t, device_t, int, int, int *); 131 static int thunder_pem_release_msi(device_t, device_t, int, int *); 132 static int thunder_pem_alloc_msix(device_t, device_t, int *); 133 static int thunder_pem_release_msix(device_t, device_t, int); 134 static int thunder_pem_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); 135 static int thunder_pem_get_id(device_t, device_t, enum pci_id_type, 136 uintptr_t *); 137 static int thunder_pem_attach(device_t); 138 static int thunder_pem_deactivate_resource(device_t, device_t, int, int, 139 struct resource *); 140 static int thunder_pem_detach(device_t); 141 static uint64_t thunder_pem_config_reg_read(struct thunder_pem_softc *, int); 142 static int thunder_pem_link_init(struct thunder_pem_softc *); 143 static int thunder_pem_maxslots(device_t); 144 static int thunder_pem_probe(device_t); 145 static uint32_t thunder_pem_read_config(device_t, u_int, u_int, u_int, u_int, 146 int); 147 static int thunder_pem_read_ivar(device_t, device_t, int, uintptr_t *); 148 static void thunder_pem_release_all(device_t); 149 static int thunder_pem_release_resource(device_t, device_t, int, int, 150 struct resource *); 151 static struct rman * thunder_pem_rman(struct thunder_pem_softc *, int); 152 static void thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *, 153 int, int); 154 static void thunder_pem_write_config(device_t, u_int, u_int, u_int, u_int, 155 uint32_t, int); 156 static int thunder_pem_write_ivar(device_t, device_t, int, uintptr_t); 157 158 /* Global handlers for SLI interface */ 159 static bus_space_handle_t sli0_s2m_regx_base = 0; 160 static bus_space_handle_t sli1_s2m_regx_base = 0; 161 162 static device_method_t thunder_pem_methods[] = { 163 /* Device interface */ 164 DEVMETHOD(device_probe, thunder_pem_probe), 165 DEVMETHOD(device_attach, thunder_pem_attach), 166 DEVMETHOD(device_detach, thunder_pem_detach), 167 168 /* Bus interface */ 169 DEVMETHOD(bus_read_ivar, thunder_pem_read_ivar), 170 DEVMETHOD(bus_write_ivar, thunder_pem_write_ivar), 171 DEVMETHOD(bus_alloc_resource, thunder_pem_alloc_resource), 172 DEVMETHOD(bus_release_resource, thunder_pem_release_resource), 173 DEVMETHOD(bus_adjust_resource, thunder_pem_adjust_resource), 174 DEVMETHOD(bus_activate_resource, thunder_pem_activate_resource), 175 DEVMETHOD(bus_deactivate_resource, thunder_pem_deactivate_resource), 176 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 177 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 178 179 /* pcib interface */ 180 DEVMETHOD(pcib_maxslots, thunder_pem_maxslots), 181 DEVMETHOD(pcib_read_config, thunder_pem_read_config), 182 DEVMETHOD(pcib_write_config, thunder_pem_write_config), 183 DEVMETHOD(pcib_alloc_msix, thunder_pem_alloc_msix), 184 DEVMETHOD(pcib_release_msix, thunder_pem_release_msix), 185 DEVMETHOD(pcib_alloc_msi, thunder_pem_alloc_msi), 186 DEVMETHOD(pcib_release_msi, thunder_pem_release_msi), 187 DEVMETHOD(pcib_map_msi, thunder_pem_map_msi), 188 DEVMETHOD(pcib_get_id, thunder_pem_get_id), 189 190 DEVMETHOD_END 191 }; 192 193 DEFINE_CLASS_0(pcib, thunder_pem_driver, thunder_pem_methods, 194 sizeof(struct thunder_pem_softc)); 195 196 static devclass_t thunder_pem_devclass; 197 extern struct bus_space memmap_bus; 198 199 DRIVER_MODULE(thunder_pem, pci, thunder_pem_driver, thunder_pem_devclass, 0, 0); 200 MODULE_DEPEND(thunder_pem, pci, 1, 1, 1); 201 202 static int 203 thunder_pem_maxslots(device_t dev) 204 { 205 206 #if 0 207 /* max slots per bus acc. to standard */ 208 return (PCI_SLOTMAX); 209 #else 210 /* 211 * ARM64TODO Workaround - otherwise an em(4) interface appears to be 212 * present on every PCI function on the bus to which it is connected 213 */ 214 return (0); 215 #endif 216 } 217 218 static int 219 thunder_pem_read_ivar(device_t dev, device_t child, int index, 220 uintptr_t *result) 221 { 222 struct thunder_pem_softc *sc; 223 int secondary_bus = 0; 224 225 sc = device_get_softc(dev); 226 227 if (index == PCIB_IVAR_BUS) { 228 secondary_bus = thunder_pem_config_reg_read(sc, PCIERC_CFG006); 229 *result = PCIERC_CFG006_SEC_BUS(secondary_bus); 230 return (0); 231 } 232 if (index == PCIB_IVAR_DOMAIN) { 233 *result = sc->id; 234 return (0); 235 } 236 237 return (ENOENT); 238 } 239 240 static int 241 thunder_pem_write_ivar(device_t dev, device_t child, int index, 242 uintptr_t value) 243 { 244 245 return (ENOENT); 246 } 247 248 static int 249 thunder_pem_activate_resource(device_t dev, device_t child, int type, int rid, 250 struct resource *r) 251 { 252 int err; 253 bus_addr_t paddr; 254 bus_size_t psize; 255 bus_space_handle_t vaddr; 256 struct thunder_pem_softc *sc; 257 258 if ((err = rman_activate_resource(r)) != 0) 259 return (err); 260 261 sc = device_get_softc(dev); 262 263 /* 264 * If this is a memory resource, map it into the kernel. 265 */ 266 if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) { 267 paddr = (bus_addr_t)rman_get_start(r); 268 psize = (bus_size_t)rman_get_size(r); 269 270 paddr = range_addr_pci_to_phys(sc->ranges, paddr); 271 272 err = bus_space_map(&memmap_bus, paddr, psize, 0, &vaddr); 273 if (err != 0) { 274 rman_deactivate_resource(r); 275 return (err); 276 } 277 rman_set_bustag(r, &memmap_bus); 278 rman_set_virtual(r, (void *)vaddr); 279 rman_set_bushandle(r, vaddr); 280 } 281 return (0); 282 } 283 284 /* 285 * This function is an exact copy of nexus_deactivate_resource() 286 * Keep it up-to-date with all changes in nexus. To be removed 287 * once bus-mapping interface is developed. 288 */ 289 static int 290 thunder_pem_deactivate_resource(device_t bus, device_t child, int type, int rid, 291 struct resource *r) 292 { 293 bus_size_t psize; 294 bus_space_handle_t vaddr; 295 296 psize = (bus_size_t)rman_get_size(r); 297 vaddr = rman_get_bushandle(r); 298 299 if (vaddr != 0) { 300 bus_space_unmap(&memmap_bus, vaddr, psize); 301 rman_set_virtual(r, NULL); 302 rman_set_bushandle(r, 0); 303 } 304 305 return (rman_deactivate_resource(r)); 306 } 307 308 static int 309 thunder_pem_adjust_resource(device_t dev, device_t child, int type, 310 struct resource *res, rman_res_t start, rman_res_t end) 311 { 312 struct thunder_pem_softc *sc; 313 struct rman *rm; 314 315 sc = device_get_softc(dev); 316 317 rm = thunder_pem_rman(sc, type); 318 if (rm == NULL) 319 return (bus_generic_adjust_resource(dev, child, type, res, 320 start, end)); 321 if (!rman_is_region_manager(res, rm)) 322 /* 323 * This means a child device has a memory or I/O 324 * resource not from you which shouldn't happen. 325 */ 326 return (EINVAL); 327 return (rman_adjust_resource(res, start, end)); 328 } 329 330 static int 331 thunder_pem_alloc_msi(device_t pci, device_t child, int count, int maxcount, 332 int *irqs) 333 { 334 device_t bus; 335 336 bus = device_get_parent(pci); 337 return (PCIB_ALLOC_MSI(device_get_parent(bus), child, count, maxcount, 338 irqs)); 339 } 340 341 static int 342 thunder_pem_release_msi(device_t pci, device_t child, int count, int *irqs) 343 { 344 device_t bus; 345 346 bus = device_get_parent(pci); 347 return (PCIB_RELEASE_MSI(device_get_parent(bus), child, count, irqs)); 348 } 349 350 static int 351 thunder_pem_alloc_msix(device_t pci, device_t child, int *irq) 352 { 353 device_t bus; 354 355 bus = device_get_parent(pci); 356 return (PCIB_ALLOC_MSIX(device_get_parent(bus), child, irq)); 357 } 358 359 static int 360 thunder_pem_release_msix(device_t pci, device_t child, int irq) 361 { 362 device_t bus; 363 364 bus = device_get_parent(pci); 365 return (PCIB_RELEASE_MSIX(device_get_parent(bus), child, irq)); 366 } 367 368 static int 369 thunder_pem_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 370 uint32_t *data) 371 { 372 device_t bus; 373 374 bus = device_get_parent(pci); 375 return (PCIB_MAP_MSI(device_get_parent(bus), child, irq, addr, data)); 376 } 377 378 static int 379 thunder_pem_get_id(device_t pci, device_t child, enum pci_id_type type, 380 uintptr_t *id) 381 { 382 int bsf; 383 int pem; 384 385 if (type != PCI_ID_MSI) 386 return (pcib_get_id(pci, child, type, id)); 387 388 bsf = pci_get_rid(child); 389 390 /* PEM (PCIe MAC/root complex) number is equal to domain */ 391 pem = pci_get_domain(child); 392 393 /* 394 * Set appropriate device ID (passed by the HW along with 395 * the transaction to memory) for different root complex 396 * numbers using hard-coded domain portion for each group. 397 */ 398 if (pem < 3) 399 *id = (0x1 << PCI_RID_DOMAIN_SHIFT) | bsf; 400 else if (pem < 6) 401 *id = (0x3 << PCI_RID_DOMAIN_SHIFT) | bsf; 402 else if (pem < 9) 403 *id = (0x9 << PCI_RID_DOMAIN_SHIFT) | bsf; 404 else if (pem < 12) 405 *id = (0xB << PCI_RID_DOMAIN_SHIFT) | bsf; 406 else 407 return (ENXIO); 408 409 return (0); 410 } 411 412 static int 413 thunder_pem_identify(device_t dev) 414 { 415 struct thunder_pem_softc *sc; 416 rman_res_t start; 417 418 sc = device_get_softc(dev); 419 start = rman_get_start(sc->reg); 420 421 /* Calculate PEM designations from its address */ 422 sc->node = (start >> SLI_NODE_SHIFT) & SLI_NODE_MASK; 423 sc->id = ((start >> SLI_ID_SHIFT) & SLI_ID_MASK) + 424 (SLI_PEMS_PER_NODE * sc->node); 425 sc->sli = sc->id % SLI_PEMS_PER_GROUP; 426 sc->sli_group = (sc->id / SLI_PEMS_PER_GROUP) % SLI_GROUPS_PER_NODE; 427 sc->sli_window_base = SLI_BASE | 428 (((uint64_t)sc->node) << SLI_NODE_SHIFT) | 429 ((uint64_t)sc->sli_group << SLI_GROUP_SHIFT); 430 sc->sli_window_base += SLI_WINDOW_SPACING * sc->sli; 431 432 return (0); 433 } 434 435 static void 436 thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *sc, 437 int sli_group, int slix) 438 { 439 uint64_t regval; 440 bus_space_handle_t handle = 0; 441 442 KASSERT(slix >= 0 && slix <= SLI_ACC_REG_CNT, ("Invalid SLI index")); 443 444 if (sli_group == 0) 445 handle = sli0_s2m_regx_base; 446 else if (sli_group == 1) 447 handle = sli1_s2m_regx_base; 448 else 449 device_printf(sc->dev, "SLI group is not correct\n"); 450 451 if (handle) { 452 /* Clear lower 32-bits of the SLIx register */ 453 regval = bus_space_read_8(sc->reg_bst, handle, 454 PEM_CFG_SLIX_TO_REG(slix)); 455 regval &= ~(0xFFFFFFFFUL); 456 bus_space_write_8(sc->reg_bst, handle, 457 PEM_CFG_SLIX_TO_REG(slix), regval); 458 } 459 } 460 461 static int 462 thunder_pem_link_init(struct thunder_pem_softc *sc) 463 { 464 uint64_t regval; 465 466 /* check whether PEM is safe to access. */ 467 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_ON_REG); 468 if ((regval & PEM_CFG_LINK_MASK) != PEM_CFG_LINK_RDY) { 469 device_printf(sc->dev, "PEM%d is not ON\n", sc->id); 470 return (ENXIO); 471 } 472 473 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS); 474 regval |= PEM_LINK_ENABLE; 475 bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS, regval); 476 477 /* Wait 1ms as per Cavium specification */ 478 DELAY(1000); 479 480 regval = thunder_pem_config_reg_read(sc, PCIERC_CFG032); 481 482 if (((regval & PEM_LINK_DLLA) == 0) || ((regval & PEM_LINK_LT) != 0)) { 483 device_printf(sc->dev, "PCIe RC: Port %d Link Timeout\n", 484 sc->id); 485 return (ENXIO); 486 } 487 488 return (0); 489 } 490 491 static int 492 thunder_pem_init(struct thunder_pem_softc *sc) 493 { 494 int i, retval = 0; 495 496 retval = thunder_pem_link_init(sc); 497 if (retval) { 498 device_printf(sc->dev, "%s failed\n", __func__); 499 return retval; 500 } 501 502 /* To support 32-bit PCIe devices, set S2M_REGx_ACC[BA]=0x0 */ 503 for (i = 0; i < SLI_ACC_REG_CNT; i++) { 504 thunder_pem_slix_s2m_regx_acc_modify(sc, sc->sli_group, i); 505 } 506 507 return (retval); 508 } 509 510 static uint64_t 511 thunder_pem_config_reg_read(struct thunder_pem_softc *sc, int reg) 512 { 513 uint64_t data; 514 515 /* Write to ADDR register */ 516 bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 517 PEM_CFG_RD_REG_ALIGN(reg)); 518 bus_space_barrier(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 8, 519 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 520 /* Read from DATA register */ 521 data = PEM_CFG_RD_REG_DATA(bus_space_read_8(sc->reg_bst, sc->reg_bsh, 522 PEM_CFG_RD)); 523 524 return (data); 525 } 526 527 static uint32_t 528 thunder_pem_read_config(device_t dev, u_int bus, u_int slot, 529 u_int func, u_int reg, int bytes) 530 { 531 uint64_t offset; 532 uint32_t data; 533 struct thunder_pem_softc *sc; 534 bus_space_tag_t t; 535 bus_space_handle_t h; 536 537 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || 538 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) 539 return (~0U); 540 541 sc = device_get_softc(dev); 542 543 /* Calculate offset */ 544 offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) | 545 (func << PEM_FUNC_SHIFT); 546 t = sc->reg_bst; 547 h = sc->pem_sli_base; 548 549 bus_space_map(sc->reg_bst, sc->sli_window_base + offset, 550 PCIE_REGMAX, 0, &h); 551 552 switch (bytes) { 553 case 1: 554 data = bus_space_read_1(t, h, reg); 555 break; 556 case 2: 557 data = le16toh(bus_space_read_2(t, h, reg)); 558 break; 559 case 4: 560 data = le32toh(bus_space_read_4(t, h, reg)); 561 break; 562 default: 563 data = ~0U; 564 break; 565 } 566 567 bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX); 568 569 return (data); 570 } 571 572 static void 573 thunder_pem_write_config(device_t dev, u_int bus, u_int slot, 574 u_int func, u_int reg, uint32_t val, int bytes) 575 { 576 uint64_t offset; 577 struct thunder_pem_softc *sc; 578 bus_space_tag_t t; 579 bus_space_handle_t h; 580 581 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || 582 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) 583 return; 584 585 sc = device_get_softc(dev); 586 587 /* Calculate offset */ 588 offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) | 589 (func << PEM_FUNC_SHIFT); 590 t = sc->reg_bst; 591 h = sc->pem_sli_base; 592 593 bus_space_map(sc->reg_bst, sc->sli_window_base + offset, 594 PCIE_REGMAX, 0, &h); 595 596 switch (bytes) { 597 case 1: 598 bus_space_write_1(t, h, reg, val); 599 break; 600 case 2: 601 bus_space_write_2(t, h, reg, htole16(val)); 602 break; 603 case 4: 604 bus_space_write_4(t, h, reg, htole32(val)); 605 break; 606 default: 607 break; 608 } 609 610 bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX); 611 } 612 613 static struct resource * 614 thunder_pem_alloc_resource(device_t dev, device_t child, int type, int *rid, 615 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 616 { 617 struct thunder_pem_softc *sc = device_get_softc(dev); 618 struct rman *rm = NULL; 619 struct resource *res; 620 device_t parent_dev; 621 622 rm = thunder_pem_rman(sc, type); 623 if (rm == NULL) { 624 /* Find parent device. On ThunderX we know an exact path. */ 625 parent_dev = device_get_parent(device_get_parent(dev)); 626 return (BUS_ALLOC_RESOURCE(parent_dev, dev, type, rid, start, 627 end, count, flags)); 628 } 629 630 631 if (!RMAN_IS_DEFAULT_RANGE(start, end)) { 632 /* 633 * We might get PHYS addresses here inherited from EFI. 634 * Convert to PCI if necessary. 635 */ 636 if (range_addr_is_phys(sc->ranges, start, count)) { 637 start = range_addr_phys_to_pci(sc->ranges, start); 638 end = start + count - 1; 639 } 640 641 } 642 643 if (bootverbose) { 644 device_printf(dev, 645 "thunder_pem_alloc_resource: start=%#lx, end=%#lx, count=%#lx\n", 646 start, end, count); 647 } 648 649 res = rman_reserve_resource(rm, start, end, count, flags, child); 650 if (res == NULL) 651 goto fail; 652 653 rman_set_rid(res, *rid); 654 655 if (flags & RF_ACTIVE) 656 if (bus_activate_resource(child, type, *rid, res)) { 657 rman_release_resource(res); 658 goto fail; 659 } 660 661 return (res); 662 663 fail: 664 if (bootverbose) { 665 device_printf(dev, "%s FAIL: type=%d, rid=%d, " 666 "start=%016lx, end=%016lx, count=%016lx, flags=%x\n", 667 __func__, type, *rid, start, end, count, flags); 668 } 669 670 return (NULL); 671 } 672 673 static int 674 thunder_pem_release_resource(device_t dev, device_t child, int type, int rid, 675 struct resource *res) 676 { 677 device_t parent_dev; 678 679 /* Find parent device. On ThunderX we know an exact path. */ 680 parent_dev = device_get_parent(device_get_parent(dev)); 681 682 if ((type != SYS_RES_MEMORY) && (type != SYS_RES_IOPORT)) 683 return (BUS_RELEASE_RESOURCE(parent_dev, child, 684 type, rid, res)); 685 686 return (rman_release_resource(res)); 687 } 688 689 static struct rman * 690 thunder_pem_rman(struct thunder_pem_softc *sc, int type) 691 { 692 693 switch (type) { 694 case SYS_RES_IOPORT: 695 return (&sc->io_rman); 696 case SYS_RES_MEMORY: 697 return (&sc->mem_rman); 698 default: 699 break; 700 } 701 702 return (NULL); 703 } 704 705 static int 706 thunder_pem_probe(device_t dev) 707 { 708 uint16_t pci_vendor_id; 709 uint16_t pci_device_id; 710 711 pci_vendor_id = pci_get_vendor(dev); 712 pci_device_id = pci_get_device(dev); 713 714 if ((pci_vendor_id == THUNDER_PEM_VENDOR_ID) && 715 (pci_device_id == THUNDER_PEM_DEVICE_ID)) { 716 device_set_desc_copy(dev, THUNDER_PEM_DESC); 717 return (0); 718 } 719 720 return (ENXIO); 721 } 722 723 static int 724 thunder_pem_attach(device_t dev) 725 { 726 devclass_t pci_class; 727 device_t parent; 728 struct thunder_pem_softc *sc; 729 int error; 730 int rid; 731 int tuple; 732 uint64_t base, size; 733 struct rman *rman; 734 735 sc = device_get_softc(dev); 736 sc->dev = dev; 737 738 /* Allocate memory for resource */ 739 pci_class = devclass_find("pci"); 740 parent = device_get_parent(dev); 741 if (device_get_devclass(parent) == pci_class) 742 rid = PCIR_BAR(0); 743 else 744 rid = RID_PEM_SPACE; 745 746 sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 747 &rid, RF_ACTIVE); 748 if (sc->reg == NULL) { 749 device_printf(dev, "Failed to allocate resource\n"); 750 return (ENXIO); 751 } 752 sc->reg_bst = rman_get_bustag(sc->reg); 753 sc->reg_bsh = rman_get_bushandle(sc->reg); 754 755 /* Map SLI, do it only once */ 756 if (!sli0_s2m_regx_base) { 757 bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC, 758 SLIX_S2M_REGX_ACC_SIZE, 0, &sli0_s2m_regx_base); 759 } 760 if (!sli1_s2m_regx_base) { 761 bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC + 762 SLIX_S2M_REGX_ACC_SPACING, SLIX_S2M_REGX_ACC_SIZE, 0, 763 &sli1_s2m_regx_base); 764 } 765 766 if ((sli0_s2m_regx_base == 0) || (sli1_s2m_regx_base == 0)) { 767 device_printf(dev, 768 "bus_space_map failed to map slix_s2m_regx_base\n"); 769 goto fail; 770 } 771 772 /* Identify PEM */ 773 if (thunder_pem_identify(dev) != 0) 774 goto fail; 775 776 /* Initialize rman and allocate regions */ 777 sc->mem_rman.rm_type = RMAN_ARRAY; 778 sc->mem_rman.rm_descr = "PEM PCIe Memory"; 779 error = rman_init(&sc->mem_rman); 780 if (error != 0) { 781 device_printf(dev, "memory rman_init() failed. error = %d\n", 782 error); 783 goto fail; 784 } 785 sc->io_rman.rm_type = RMAN_ARRAY; 786 sc->io_rman.rm_descr = "PEM PCIe IO"; 787 error = rman_init(&sc->io_rman); 788 if (error != 0) { 789 device_printf(dev, "IO rman_init() failed. error = %d\n", 790 error); 791 goto fail_mem; 792 } 793 794 /* 795 * We ignore the values that may have been provided in FDT 796 * and configure ranges according to the below formula 797 * for all types of devices. This is because some DTBs provided 798 * by EFI do not have proper ranges property or don't have them 799 * at all. 800 */ 801 /* Fill memory window */ 802 sc->ranges[0].pci_base = PCI_MEMORY_BASE; 803 sc->ranges[0].size = PCI_MEMORY_SIZE; 804 sc->ranges[0].phys_base = sc->sli_window_base + SLI_PCI_OFFSET + 805 sc->ranges[0].pci_base; 806 sc->ranges[0].flags = SYS_RES_MEMORY; 807 808 /* Fill IO window */ 809 sc->ranges[1].pci_base = PCI_IO_BASE; 810 sc->ranges[1].size = PCI_IO_SIZE; 811 sc->ranges[1].phys_base = sc->sli_window_base + SLI_PCI_OFFSET + 812 sc->ranges[1].pci_base; 813 sc->ranges[1].flags = SYS_RES_IOPORT; 814 815 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { 816 base = sc->ranges[tuple].pci_base; 817 size = sc->ranges[tuple].size; 818 if (size == 0) 819 continue; /* empty range element */ 820 821 rman = thunder_pem_rman(sc, sc->ranges[tuple].flags); 822 if (rman != NULL) 823 error = rman_manage_region(rman, base, 824 base + size - 1); 825 else 826 error = EINVAL; 827 if (error) { 828 device_printf(dev, 829 "rman_manage_region() failed. error = %d\n", error); 830 rman_fini(&sc->mem_rman); 831 return (error); 832 } 833 if (bootverbose) { 834 device_printf(dev, 835 "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx, Flags:0x%jx\n", 836 sc->ranges[tuple].pci_base, 837 sc->ranges[tuple].phys_base, 838 sc->ranges[tuple].size, 839 sc->ranges[tuple].flags); 840 } 841 } 842 843 if (thunder_pem_init(sc)) { 844 device_printf(dev, "Failure during PEM init\n"); 845 goto fail_io; 846 } 847 848 device_add_child(dev, "pci", -1); 849 850 return (bus_generic_attach(dev)); 851 852 fail_io: 853 rman_fini(&sc->io_rman); 854 fail_mem: 855 rman_fini(&sc->mem_rman); 856 fail: 857 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg); 858 return (ENXIO); 859 } 860 861 static void 862 thunder_pem_release_all(device_t dev) 863 { 864 struct thunder_pem_softc *sc; 865 866 sc = device_get_softc(dev); 867 868 rman_fini(&sc->io_rman); 869 rman_fini(&sc->mem_rman); 870 871 if (sc->reg != NULL) 872 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg); 873 } 874 875 static int 876 thunder_pem_detach(device_t dev) 877 { 878 879 thunder_pem_release_all(dev); 880 881 return (0); 882 } 883