xref: /freebsd/sys/arm/nvidia/tegra_uart.c (revision 3e13ea16a6aca1a97d14f3c7cba9c29c9f3fd414)
1ef2ee5d0SMichal Meloun /*-
2ef2ee5d0SMichal Meloun  * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3ef2ee5d0SMichal Meloun  * All rights reserved.
4ef2ee5d0SMichal Meloun  *
5ef2ee5d0SMichal Meloun  * Redistribution and use in source and binary forms, with or without
6ef2ee5d0SMichal Meloun  * modification, are permitted provided that the following conditions
7ef2ee5d0SMichal Meloun  * are met:
8ef2ee5d0SMichal Meloun  * 1. Redistributions of source code must retain the above copyright
9ef2ee5d0SMichal Meloun  *    notice, this list of conditions and the following disclaimer.
10ef2ee5d0SMichal Meloun  * 2. Redistributions in binary form must reproduce the above copyright
11ef2ee5d0SMichal Meloun  *    notice, this list of conditions and the following disclaimer in the
12ef2ee5d0SMichal Meloun  *    documentation and/or other materials provided with the distribution.
13ef2ee5d0SMichal Meloun  *
14ef2ee5d0SMichal Meloun  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15ef2ee5d0SMichal Meloun  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16ef2ee5d0SMichal Meloun  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17ef2ee5d0SMichal Meloun  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18ef2ee5d0SMichal Meloun  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19ef2ee5d0SMichal Meloun  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20ef2ee5d0SMichal Meloun  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21ef2ee5d0SMichal Meloun  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22ef2ee5d0SMichal Meloun  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23ef2ee5d0SMichal Meloun  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24ef2ee5d0SMichal Meloun  * SUCH DAMAGE.
25ef2ee5d0SMichal Meloun  */
26ef2ee5d0SMichal Meloun 
27ef2ee5d0SMichal Meloun #include <sys/cdefs.h>
28ef2ee5d0SMichal Meloun __FBSDID("$FreeBSD$");
29ef2ee5d0SMichal Meloun 
30ef2ee5d0SMichal Meloun 
31ef2ee5d0SMichal Meloun /*
32ef2ee5d0SMichal Meloun  * UART driver for Tegra SoCs.
33ef2ee5d0SMichal Meloun  */
34ef2ee5d0SMichal Meloun #include "opt_platform.h"
35ef2ee5d0SMichal Meloun 
36ef2ee5d0SMichal Meloun #include <sys/param.h>
37ef2ee5d0SMichal Meloun #include <sys/systm.h>
38ef2ee5d0SMichal Meloun #include <sys/bus.h>
39ef2ee5d0SMichal Meloun #include <sys/conf.h>
40ef2ee5d0SMichal Meloun #include <sys/kernel.h>
41ef2ee5d0SMichal Meloun #include <sys/module.h>
42ef2ee5d0SMichal Meloun #include <sys/sysctl.h>
43ef2ee5d0SMichal Meloun #include <machine/bus.h>
44ef2ee5d0SMichal Meloun 
45ef2ee5d0SMichal Meloun #include <dev/extres/clk/clk.h>
46ef2ee5d0SMichal Meloun #include <dev/extres/hwreset/hwreset.h>
47ef2ee5d0SMichal Meloun #include <dev/ofw/ofw_bus.h>
48ef2ee5d0SMichal Meloun #include <dev/ofw/ofw_bus_subr.h>
49ef2ee5d0SMichal Meloun #include <dev/uart/uart.h>
50ef2ee5d0SMichal Meloun #include <dev/uart/uart_cpu.h>
51ef2ee5d0SMichal Meloun #include <dev/uart/uart_cpu_fdt.h>
52ef2ee5d0SMichal Meloun #include <dev/uart/uart_bus.h>
53ef2ee5d0SMichal Meloun #include <dev/uart/uart_dev_ns8250.h>
54ef2ee5d0SMichal Meloun #include <dev/ic/ns16550.h>
55ef2ee5d0SMichal Meloun 
56ef2ee5d0SMichal Meloun #include "uart_if.h"
57ef2ee5d0SMichal Meloun 
58ef2ee5d0SMichal Meloun /*
59ef2ee5d0SMichal Meloun  * High-level UART interface.
60ef2ee5d0SMichal Meloun  */
61ef2ee5d0SMichal Meloun struct tegra_softc {
62ef2ee5d0SMichal Meloun 	struct ns8250_softc 	ns8250_base;
63ef2ee5d0SMichal Meloun 	clk_t			clk;
64ef2ee5d0SMichal Meloun 	hwreset_t		reset;
65ef2ee5d0SMichal Meloun };
66ef2ee5d0SMichal Meloun 
67ef2ee5d0SMichal Meloun /*
68ef2ee5d0SMichal Meloun  * UART class interface.
69ef2ee5d0SMichal Meloun  */
70ef2ee5d0SMichal Meloun static int
71ef2ee5d0SMichal Meloun tegra_uart_attach(struct uart_softc *sc)
72ef2ee5d0SMichal Meloun {
73ef2ee5d0SMichal Meloun 	int rv;
74ef2ee5d0SMichal Meloun 	struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
75ef2ee5d0SMichal Meloun 	struct uart_bas *bas = &sc->sc_bas;
76ef2ee5d0SMichal Meloun 
77ef2ee5d0SMichal Meloun 	rv = ns8250_bus_attach(sc);
78ef2ee5d0SMichal Meloun 	if (rv != 0)
79ef2ee5d0SMichal Meloun 		return (rv);
80ef2ee5d0SMichal Meloun 
81ef2ee5d0SMichal Meloun 	ns8250->ier_rxbits = 0x1d;
82ef2ee5d0SMichal Meloun 	ns8250->ier_mask = 0xc0;
83ef2ee5d0SMichal Meloun 	ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
8458872fc0SMichal Meloun 	ns8250->ier |= ns8250->ier_rxbits;
85ef2ee5d0SMichal Meloun 	uart_setreg(bas, REG_IER, ns8250->ier);
86ef2ee5d0SMichal Meloun 	uart_barrier(bas);
87ef2ee5d0SMichal Meloun 	return (0);
88ef2ee5d0SMichal Meloun }
89ef2ee5d0SMichal Meloun 
90ef2ee5d0SMichal Meloun static void
91ef2ee5d0SMichal Meloun tegra_uart_grab(struct uart_softc *sc)
92ef2ee5d0SMichal Meloun {
93ef2ee5d0SMichal Meloun 	struct uart_bas *bas = &sc->sc_bas;
94ef2ee5d0SMichal Meloun 	struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
95ef2ee5d0SMichal Meloun 	u_char ier;
96ef2ee5d0SMichal Meloun 
97ef2ee5d0SMichal Meloun 	/*
98ef2ee5d0SMichal Meloun 	 * turn off all interrupts to enter polling mode. Leave the
99ef2ee5d0SMichal Meloun 	 * saved mask alone. We'll restore whatever it was in ungrab.
100ef2ee5d0SMichal Meloun 	 * All pending interrupt signals are reset when IER is set to 0.
101ef2ee5d0SMichal Meloun 	 */
102ef2ee5d0SMichal Meloun 	uart_lock(sc->sc_hwmtx);
103ef2ee5d0SMichal Meloun 	ier = uart_getreg(bas, REG_IER);
104ef2ee5d0SMichal Meloun 	uart_setreg(bas, REG_IER, ier & ns8250->ier_mask);
105*3e13ea16SMichal Meloun 
106*3e13ea16SMichal Meloun 	while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0)
107*3e13ea16SMichal Meloun 		;
108*3e13ea16SMichal Meloun 
109ef2ee5d0SMichal Meloun 	uart_setreg(bas, REG_FCR, 0);
110ef2ee5d0SMichal Meloun 	uart_barrier(bas);
111ef2ee5d0SMichal Meloun 	uart_unlock(sc->sc_hwmtx);
112ef2ee5d0SMichal Meloun }
113ef2ee5d0SMichal Meloun 
114ef2ee5d0SMichal Meloun static void
115ef2ee5d0SMichal Meloun tegra_uart_ungrab(struct uart_softc *sc)
116ef2ee5d0SMichal Meloun {
117ef2ee5d0SMichal Meloun 	struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
118ef2ee5d0SMichal Meloun 	struct uart_bas *bas = &sc->sc_bas;
119ef2ee5d0SMichal Meloun 
120ef2ee5d0SMichal Meloun 	/*
121ef2ee5d0SMichal Meloun 	 * Restore previous interrupt mask
122ef2ee5d0SMichal Meloun 	 */
123ef2ee5d0SMichal Meloun 	uart_lock(sc->sc_hwmtx);
124ef2ee5d0SMichal Meloun 	uart_setreg(bas, REG_FCR, ns8250->fcr);
125ef2ee5d0SMichal Meloun 	uart_setreg(bas, REG_IER, ns8250->ier);
126ef2ee5d0SMichal Meloun 	uart_barrier(bas);
127ef2ee5d0SMichal Meloun 	uart_unlock(sc->sc_hwmtx);
128ef2ee5d0SMichal Meloun }
129ef2ee5d0SMichal Meloun 
130ef2ee5d0SMichal Meloun static kobj_method_t tegra_methods[] = {
131ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_probe,		ns8250_bus_probe),
132ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_attach,		tegra_uart_attach),
133ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_detach,		ns8250_bus_detach),
134ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_flush,		ns8250_bus_flush),
135ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_getsig,		ns8250_bus_getsig),
136ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_ioctl,		ns8250_bus_ioctl),
137ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_ipend,		ns8250_bus_ipend),
138ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_param,		ns8250_bus_param),
139ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_receive,	ns8250_bus_receive),
140ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_setsig,		ns8250_bus_setsig),
141ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_transmit,	ns8250_bus_transmit),
142ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_grab,		tegra_uart_grab),
143ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_ungrab,		tegra_uart_ungrab),
144ef2ee5d0SMichal Meloun 	KOBJMETHOD_END
145ef2ee5d0SMichal Meloun };
146ef2ee5d0SMichal Meloun 
147ef2ee5d0SMichal Meloun static struct uart_class tegra_uart_class = {
148ef2ee5d0SMichal Meloun 	"tegra class",
149ef2ee5d0SMichal Meloun 	tegra_methods,
150ef2ee5d0SMichal Meloun 	sizeof(struct tegra_softc),
151ef2ee5d0SMichal Meloun 	.uc_ops = &uart_ns8250_ops,
152ef2ee5d0SMichal Meloun 	.uc_range = 8,
153ef2ee5d0SMichal Meloun 	.uc_rclk = 0,
154ef2ee5d0SMichal Meloun };
155ef2ee5d0SMichal Meloun 
156ef2ee5d0SMichal Meloun /* Compatible devices. */
157ef2ee5d0SMichal Meloun static struct ofw_compat_data compat_data[] = {
158ef2ee5d0SMichal Meloun 	{"nvidia,tegra124-uart", (uintptr_t)&tegra_uart_class},
159ef2ee5d0SMichal Meloun 	{NULL,			(uintptr_t)NULL},
160ef2ee5d0SMichal Meloun };
161ef2ee5d0SMichal Meloun 
162ef2ee5d0SMichal Meloun UART_FDT_CLASS(compat_data);
163ef2ee5d0SMichal Meloun 
164ef2ee5d0SMichal Meloun /*
165ef2ee5d0SMichal Meloun  * UART Driver interface.
166ef2ee5d0SMichal Meloun  */
167ef2ee5d0SMichal Meloun static int
168ef2ee5d0SMichal Meloun uart_fdt_get_shift1(phandle_t node)
169ef2ee5d0SMichal Meloun {
170ef2ee5d0SMichal Meloun 	pcell_t shift;
171ef2ee5d0SMichal Meloun 
172ef2ee5d0SMichal Meloun 	if ((OF_getencprop(node, "reg-shift", &shift, sizeof(shift))) <= 0)
173ef2ee5d0SMichal Meloun 		shift = 2;
174ef2ee5d0SMichal Meloun 	return ((int)shift);
175ef2ee5d0SMichal Meloun }
176ef2ee5d0SMichal Meloun 
177ef2ee5d0SMichal Meloun static int
178ef2ee5d0SMichal Meloun tegra_uart_probe(device_t dev)
179ef2ee5d0SMichal Meloun {
180ef2ee5d0SMichal Meloun 	struct tegra_softc *sc;
181ef2ee5d0SMichal Meloun 	phandle_t node;
182ef2ee5d0SMichal Meloun 	uint64_t freq;
183ef2ee5d0SMichal Meloun 	int shift;
184ef2ee5d0SMichal Meloun 	int rv;
185ef2ee5d0SMichal Meloun 	const struct ofw_compat_data *cd;
186ef2ee5d0SMichal Meloun 
187ef2ee5d0SMichal Meloun 	sc = device_get_softc(dev);
188ef2ee5d0SMichal Meloun 	if (!ofw_bus_status_okay(dev))
189ef2ee5d0SMichal Meloun 		return (ENXIO);
190ef2ee5d0SMichal Meloun 	cd = ofw_bus_search_compatible(dev, compat_data);
191ef2ee5d0SMichal Meloun 	if (cd->ocd_data == 0)
192ef2ee5d0SMichal Meloun 		return (ENXIO);
193ef2ee5d0SMichal Meloun 	sc->ns8250_base.base.sc_class = (struct uart_class *)cd->ocd_data;
194ef2ee5d0SMichal Meloun 
195dac93553SMichal Meloun 	rv = hwreset_get_by_ofw_name(dev, 0, "serial", &sc->reset);
196ef2ee5d0SMichal Meloun 	if (rv != 0) {
197ef2ee5d0SMichal Meloun 		device_printf(dev, "Cannot get 'serial' reset\n");
198ef2ee5d0SMichal Meloun 		return (ENXIO);
199ef2ee5d0SMichal Meloun 	}
200ef2ee5d0SMichal Meloun 	rv = hwreset_deassert(sc->reset);
201ef2ee5d0SMichal Meloun 	if (rv != 0) {
202ef2ee5d0SMichal Meloun 		device_printf(dev, "Cannot unreset 'serial' reset\n");
203ef2ee5d0SMichal Meloun 		return (ENXIO);
204ef2ee5d0SMichal Meloun 	}
205ef2ee5d0SMichal Meloun 
206ef2ee5d0SMichal Meloun 	node = ofw_bus_get_node(dev);
207ef2ee5d0SMichal Meloun 	shift = uart_fdt_get_shift1(node);
208dac93553SMichal Meloun 	rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
209ef2ee5d0SMichal Meloun 	if (rv != 0) {
210ef2ee5d0SMichal Meloun 		device_printf(dev, "Cannot get UART clock: %d\n", rv);
211ef2ee5d0SMichal Meloun 		return (ENXIO);
212ef2ee5d0SMichal Meloun 	}
213ef2ee5d0SMichal Meloun 	rv = clk_enable(sc->clk);
214ef2ee5d0SMichal Meloun 	if (rv != 0) {
215ef2ee5d0SMichal Meloun 		device_printf(dev, "Cannot enable UART clock: %d\n", rv);
216ef2ee5d0SMichal Meloun 		return (ENXIO);
217ef2ee5d0SMichal Meloun 	}
218ef2ee5d0SMichal Meloun 	rv = clk_get_freq(sc->clk, &freq);
219ef2ee5d0SMichal Meloun 	if (rv != 0) {
220ef2ee5d0SMichal Meloun 		device_printf(dev, "Cannot enable UART clock: %d\n", rv);
221ef2ee5d0SMichal Meloun 		return (ENXIO);
222ef2ee5d0SMichal Meloun 	}
223381388b9SMatt Macy 	return (uart_bus_probe(dev, shift, 0, (int)freq, 0, 0, 0));
224ef2ee5d0SMichal Meloun }
225ef2ee5d0SMichal Meloun 
226ef2ee5d0SMichal Meloun static int
227ef2ee5d0SMichal Meloun tegra_uart_detach(device_t dev)
228ef2ee5d0SMichal Meloun {
229ef2ee5d0SMichal Meloun 	struct tegra_softc *sc;
230ef2ee5d0SMichal Meloun 
231ef2ee5d0SMichal Meloun 	sc = device_get_softc(dev);
232ef2ee5d0SMichal Meloun 	if (sc->clk != NULL) {
233ef2ee5d0SMichal Meloun 		clk_release(sc->clk);
234ef2ee5d0SMichal Meloun 	}
235ef2ee5d0SMichal Meloun 
236ef2ee5d0SMichal Meloun 	return (uart_bus_detach(dev));
237ef2ee5d0SMichal Meloun }
238ef2ee5d0SMichal Meloun 
239ef2ee5d0SMichal Meloun static device_method_t tegra_uart_bus_methods[] = {
240ef2ee5d0SMichal Meloun 	/* Device interface */
241ef2ee5d0SMichal Meloun 	DEVMETHOD(device_probe,		tegra_uart_probe),
242ef2ee5d0SMichal Meloun 	DEVMETHOD(device_attach,	uart_bus_attach),
243ef2ee5d0SMichal Meloun 	DEVMETHOD(device_detach,	tegra_uart_detach),
244ef2ee5d0SMichal Meloun 	{ 0, 0 }
245ef2ee5d0SMichal Meloun };
246ef2ee5d0SMichal Meloun 
247ef2ee5d0SMichal Meloun static driver_t tegra_uart_driver = {
248ef2ee5d0SMichal Meloun 	uart_driver_name,
249ef2ee5d0SMichal Meloun 	tegra_uart_bus_methods,
250ef2ee5d0SMichal Meloun 	sizeof(struct tegra_softc),
251ef2ee5d0SMichal Meloun };
252ef2ee5d0SMichal Meloun 
253ef2ee5d0SMichal Meloun DRIVER_MODULE(tegra_uart, simplebus,  tegra_uart_driver, uart_devclass,
254ef2ee5d0SMichal Meloun     0, 0);
255