1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 #include <sys/lock.h> 32 #include <sys/mutex.h> 33 #include <sys/rman.h> 34 35 #include <machine/bus.h> 36 37 #include <dev/extres/clk/clk.h> 38 39 #include <dt-bindings/clock/tegra124-car.h> 40 #include "tegra124_car.h" 41 42 /* The TEGRA124_CLK_XUSB_GATE is missing in current 43 * DT bindings, define it localy 44 */ 45 #ifdef TEGRA124_CLK_XUSB_GATE 46 #error "TEGRA124_CLK_XUSB_GATE is now defined, revisit XUSB code!" 47 #else 48 #define TEGRA124_CLK_XUSB_GATE 143 49 #endif 50 51 /* Bits in base register. */ 52 #define PERLCK_AMUX_MASK 0x0F 53 #define PERLCK_AMUX_SHIFT 16 54 #define PERLCK_AMUX_DIS (1 << 20) 55 #define PERLCK_UDIV_DIS (1 << 24) 56 #define PERLCK_ENA_MASK (1 << 28) 57 #define PERLCK_MUX_SHIFT 29 58 #define PERLCK_MUX_MASK 0x07 59 60 struct periph_def { 61 struct clknode_init_def clkdef; 62 uint32_t base_reg; 63 uint32_t div_width; 64 uint32_t div_mask; 65 uint32_t div_f_width; 66 uint32_t div_f_mask; 67 uint32_t flags; 68 }; 69 70 struct pgate_def { 71 struct clknode_init_def clkdef; 72 uint32_t idx; 73 uint32_t flags; 74 }; 75 #define PLIST(x) static const char *x[] 76 77 #define GATE(_id, cname, plist, _idx) \ 78 { \ 79 .clkdef.id = TEGRA124_CLK_##_id, \ 80 .clkdef.name = cname, \ 81 .clkdef.parent_names = (const char *[]){plist}, \ 82 .clkdef.parent_cnt = 1, \ 83 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 84 .idx = _idx, \ 85 .flags = 0, \ 86 } 87 88 /* Sources for multiplexors. */ 89 PLIST(mux_a_N_audio_N_p_N_clkm) = 90 {"pllA_out0", NULL, "audio", NULL, 91 "pllP_out0", NULL, "clk_m"}; 92 PLIST(mux_a_N_audio0_N_p_N_clkm) = 93 {"pllA_out0", NULL, "audio0", NULL, 94 "pllP_out0", NULL, "clk_m"}; 95 PLIST(mux_a_N_audio1_N_p_N_clkm) = 96 {"pllA_out0", NULL, "audio1", NULL, 97 "pllP_out0", NULL, "clk_m"}; 98 PLIST(mux_a_N_audio2_N_p_N_clkm) = 99 {"pllA_out0", NULL, "audio2", NULL, 100 "pllP_out0", NULL, "clk_m"}; 101 PLIST(mux_a_N_audio3_N_p_N_clkm) = 102 {"pllA_out0", NULL, "audio3", NULL, 103 "pllP_out0", NULL, "clk_m"}; 104 PLIST(mux_a_N_audio4_N_p_N_clkm) = 105 {"pllA_out0", NULL, "audio4", NULL, 106 "pllP_out0", NULL, "clk_m"}; 107 PLIST(mux_a_clks_p_clkm_e) = 108 {"pllA_out0", "clk_s", "pllP_out0", 109 "clk_m", "pllE_out0"}; 110 PLIST(mux_a_c2_c_c3_p_N_clkm) = 111 {"pllA_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 112 "pllP_out0", NULL, "clk_m"}; 113 114 PLIST(mux_m_c_p_a_c2_c3) = 115 {"pllM_out0", "pllC_out0", "pllP_out0", "pllA_out0", 116 "pllC2_out0", "pllC3_out0"}; 117 PLIST(mux_m_c_p_a_c2_c3_clkm) = 118 {"pllM_out0", "pllC_out0", "pllP_out0", "pllA_out0", 119 "pllC2_out0", "pllC3_out0", "clk_m"}; 120 PLIST(mux_m_c_p_a_c2_c3_clkm_c4) = 121 {"pllM_out0", "pllC_out0", "pllP_out0", "pllA_out0", 122 "pllC2_out0", "pllC3_out0", "clk_m", "pllC4_out0"}; 123 PLIST(mux_m_c_p_clkm_mud_c2_c3) = 124 {"pllM_out0", "pllC_out0", "pllP_out0", "clk_m", 125 "pllM_UD", "pllC2_out0", "pllC3_out0"}; 126 PLIST(mux_m_c_p_clkm_mud_c2_c3_cud) = 127 {"pllM_out0", "pllC_out0", "pllP_out0", "clk_m", 128 "pllM_UD", "pllC2_out0", "pllC3_out0", "pllC_UD"}; 129 130 PLIST(mux_m_c2_c_c3_p_N_a) = 131 {"pllM_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 132 "pllP_out0", NULL, "pllA_out0"}; 133 PLIST(mux_m_c2_c_c3_p_N_a_c4) = 134 {"pllM_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 135 NULL, "pllA_out0", "pllC4_out0"}; 136 137 PLIST(mux_p_N_c_N_N_N_clkm) = 138 {"pllP_out0", NULL, "pllC_out0", NULL, 139 NULL, NULL, "clk_m"}; 140 PLIST(mux_p_N_c_N_m_N_clkm) = 141 {"pllP_out0", NULL, "pllC_out0", NULL, 142 "pllM_out0", NULL, "clk_m"}; 143 PLIST(mux_p_c_c2_clkm) = 144 {"pllP_out0", "pllC_out0", "pllC2_out0", "clk_m"}; 145 PLIST(mux_p_c2_c_c3_m) = 146 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 147 "pllM_out0"}; 148 PLIST(mux_p_c2_c_c3_m_N_clkm) = 149 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 150 "pllM_out0", NULL, "clk_m"}; 151 PLIST(mux_p_c2_c_c3_m_e_clkm) = 152 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 153 "pllM_out0", "pllE_out0", "clk_m"}; 154 PLIST(mux_p_c2_c_c3_m_a_clkm) = 155 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 156 "pllM_out0", "pllA_out0", "clk_m"}; 157 PLIST(mux_p_c2_c_c3_m_clks_clkm) = 158 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 159 "pllM_out0", "clk_s", "clk_m"}; 160 PLIST(mux_p_c2_c_c3_clks_N_clkm) = 161 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 162 "clk_s", NULL, "clk_m"}; 163 PLIST(mux_p_c2_c_c3_clkm_N_clks) = 164 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 165 "clk_m", NULL, "clk_s"}; 166 PLIST(mux_p_clkm_clks_E) = 167 {"pllP_out0", "clk_m", "clk_s", "pllE_out0"}; 168 PLIST(mux_p_m_d_a_c_d2_clkm) = 169 {"pllP_out0", "pllM_out0", "pllD_out0", "pllA_out0", 170 "pllC_out0", "pllD2_out0", "clk_m"}; 171 172 PLIST(mux_clkm_N_u48_N_p_N_u480) = 173 {"clk_m", NULL, "pllU_48", NULL, 174 "pllP_out0", NULL, "pllU_480"}; 175 PLIST(mux_clkm_p_c2_c_c3_refre) = 176 {"clk_m", "pllP_out0", "pllC2_out0", "pllC_out0", 177 "pllC3_out0", "pllREFE_out"}; 178 PLIST(mux_clkm_refe_clks_u480_c_c2_c3_oscdiv) = 179 {"clk_m", "pllREFE_out", "clk_s", "pllU_480", 180 "pllC_out0", "pllC2_out0", "pllC3_out0", "osc_div_clk"}; 181 182 PLIST(mux_sep_audio) = 183 {"pllA_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 184 "pllP_out0", NULL, "clk_m", NULL, 185 "spdif_in", "i2s0", "i2s1", "i2s2", 186 "i2s4", "pllA_out0", "ext_vimclk"}; 187 188 static uint32_t clk_enable_reg[] = { 189 CLK_OUT_ENB_L, 190 CLK_OUT_ENB_H, 191 CLK_OUT_ENB_U, 192 CLK_OUT_ENB_V, 193 CLK_OUT_ENB_W, 194 CLK_OUT_ENB_X, 195 }; 196 197 static uint32_t clk_reset_reg[] = { 198 RST_DEVICES_L, 199 RST_DEVICES_H, 200 RST_DEVICES_U, 201 RST_DEVICES_V, 202 RST_DEVICES_W, 203 RST_DEVICES_X, 204 }; 205 206 #define L(n) ((0 * 32) + (n)) 207 #define H(n) ((1 * 32) + (n)) 208 #define U(n) ((2 * 32) + (n)) 209 #define V(n) ((3 * 32) + (n)) 210 #define W(n) ((4 * 32) + (n)) 211 #define X(n) ((5 * 32) + (n)) 212 213 static struct pgate_def pgate_def[] = { 214 /* bank L -> 0-31 */ 215 /* GATE(CPU, "cpu", "clk_m", L(0)), */ 216 GATE(ISPB, "ispb", "clk_m", L(3)), 217 GATE(RTC, "rtc", "clk_s", L(4)), 218 GATE(TIMER, "timer", "clk_m", L(5)), 219 GATE(UARTA, "uarta", "pc_uarta" , L(6)), 220 GATE(UARTB, "uartb", "pc_uartb", L(7)), 221 GATE(VFIR, "vfir", "pc_vfir", L(7)), 222 /* GATE(GPIO, "gpio", "clk_m", L(8)), */ 223 GATE(SDMMC2, "sdmmc2", "pc_sdmmc2", L(9)), 224 GATE(SPDIF_OUT, "spdif_out", "pc_spdif_out", L(10)), 225 GATE(SPDIF_IN, "spdif_in", "pc_spdif_in", L(10)), 226 GATE(I2S1, "i2s1", "pc_i2s1", L(11)), 227 GATE(I2C1, "i2c1", "pc_i2c1", L(12)), 228 GATE(SDMMC1, "sdmmc1", "pc_sdmmc1", L(14)), 229 GATE(SDMMC4, "sdmmc4", "pc_sdmmc4", L(15)), 230 GATE(PWM, "pwm", "pc_pwm", L(17)), 231 GATE(I2S2, "i2s2", "pc_i2s2", L(18)), 232 GATE(VI, "vi", "pc_vi", L(20)), 233 GATE(USBD, "usbd", "clk_m", L(22)), 234 GATE(ISP, "isp", "pc_isp", L(23)), 235 GATE(DISP2, "disp2", "pc_disp2", L(26)), 236 GATE(DISP1, "disp1", "pc_disp1", L(27)), 237 GATE(HOST1X, "host1x", "pc_host1x", L(28)), 238 GATE(VCP, "vcp", "clk_m", L(29)), 239 GATE(I2S0, "i2s0", "pc_i2s0", L(30)), 240 /* GATE(CACHE2, "ccache2", "clk_m", L(31)), */ 241 242 /* bank H -> 32-63 */ 243 GATE(MC, "mem", "clk_m", H(0)), 244 /* GATE(AHBDMA, "ahbdma", "clk_m", H(1)), */ 245 GATE(APBDMA, "apbdma", "clk_m", H(2)), 246 GATE(KBC, "kbc", "clk_s", H(4)), 247 /* GATE(STAT_MON, "stat_mon", "clk_s", H(5)), */ 248 /* GATE(PMC, "pmc", "clk_s", H(6)), */ 249 GATE(FUSE, "fuse", "clk_m", H(7)), 250 GATE(KFUSE, "kfuse", "clk_m", H(8)), 251 GATE(SBC1, "spi1", "pc_spi1", H(9)), 252 GATE(NOR, "snor", "pc_snor", H(10)), 253 /* GATE(JTAG2TBC, "jtag2tbc", "clk_m", H(11)), */ 254 GATE(SBC2, "spi2", "pc_spi2", H(12)), 255 GATE(SBC3, "spi3", "pc_spi3", H(14)), 256 GATE(I2C5, "i2c5", "pc_i2c5", H(15)), 257 GATE(DSIA, "dsia", "dsia_mux", H(16)), 258 GATE(MIPI, "hsi", "pc_hsi", H(18)), 259 GATE(HDMI, "hdmi", "pc_hdmi", H(19)), 260 GATE(CSI, "csi", "pllP_out3", H(20)), 261 GATE(I2C2, "i2c2", "pc_i2c2", H(22)), 262 GATE(UARTC, "uartc", "pc_uartc", H(23)), 263 GATE(MIPI_CAL, "mipi_cal", "clk_m", H(24)), 264 GATE(EMC, "emc", "pc_emc_2x", H(25)), 265 GATE(USB2, "usb2", "clk_m", H(26)), 266 GATE(USB3, "usb3", "clk_m", H(27)), 267 GATE(VDE, "vde", "pc_vde", H(29)), 268 GATE(BSEA, "bsea", "clk_m", H(30)), 269 GATE(BSEV, "bsev", "clk_m", H(31)), 270 271 /* bank U -> 64-95 */ 272 GATE(UARTD, "uartd", "pc_uartd", U(1)), 273 GATE(I2C3, "i2c3", "pc_i2c3", U(3)), 274 GATE(SBC4, "spi4", "pc_spi4", U(4)), 275 GATE(SDMMC3, "sdmmc3", "pc_sdmmc3", U(5)), 276 GATE(PCIE, "pcie", "clk_m", U(6)), 277 GATE(OWR, "owr", "pc_owr", U(7)), 278 GATE(AFI, "afi", "clk_m", U(8)), 279 GATE(CSITE, "csite", "pc_csite", U(9)), 280 /* GATE(AVPUCQ, "avpucq", clk_m, U(11)), */ 281 GATE(TRACE, "traceclkin", "pc_traceclkin", U(13)), 282 GATE(SOC_THERM, "soc_therm", "pc_soc_therm", U(14)), 283 GATE(DTV, "dtv", "clk_m", U(15)), 284 GATE(I2CSLOW, "i2c_slow", "pc_i2c_slow", U(17)), 285 GATE(DSIB, "dsib", "dsib_mux", U(18)), 286 GATE(TSEC, "tsec", "pc_tsec", U(19)), 287 /* GATE(IRAMA, "irama", "clk_m", U(20)), */ 288 /* GATE(IRAMB, "iramb", "clk_m", U(21)), */ 289 /* GATE(IRAMC, "iramc", "clk_m", U(22)), */ 290 /* GATE(IRAMD, "iramd", "clk_m", U(23)), */ 291 /* GATE(CRAM2, "cram2", "clk_m", U(24)), */ 292 GATE(XUSB_HOST, "xusb_core_host", "pc_xusb_core_host", U(25)), 293 /* GATE(M_DOUBLER, "m_doubler", "clk_m", U(26)), */ 294 GATE(MSENC, "msenc", "pc_msenc", U(27)), 295 GATE(CSUS, "sus_out", "clk_m", U(28)), 296 /* GATE(DEVD2_OUT, "devd2_out", "clk_m", U(29)), */ 297 /* GATE(DEVD1_OUT, "devd1_out", "clk_m", U(30)), */ 298 GATE(XUSB_DEV, "xusb_core_dev", "pc_xusb_core_dev", U(31)), 299 300 /* bank V -> 96-127 */ 301 /* GATE(CPUG, "cpug", "clk_m", V(0)), */ 302 /* GATE(CPULP, "cpuLP", "clk_m", V(1)), */ 303 GATE(MSELECT, "mselect", "pc_mselect", V(3)), 304 GATE(TSENSOR, "tsensor", "pc_tsensor", V(4)), 305 GATE(I2S3, "i2s3", "pc_i2s3", V(5)), 306 GATE(I2S4, "i2s4", "pc_i2s4", V(6)), 307 GATE(I2C4, "i2c4", "pc_i2c4", V(7)), 308 GATE(SBC5, "spi5", "pc_spi5", V(8)), 309 GATE(SBC6, "spi6", "pc_spi6", V(9)), 310 GATE(D_AUDIO, "audio", "pc_audio", V(10)), 311 GATE(APBIF, "apbif", "clk_m", V(11)), 312 GATE(DAM0, "dam0", "pc_dam0", V(12)), 313 GATE(DAM1, "dam1", "pc_dam1", V(13)), 314 GATE(DAM2, "dam2", "pc_dam2", V(14)), 315 GATE(HDA2CODEC_2X, "hda2codec_2x", "pc_hda2codec_2x", V(15)), 316 /* GATE(ATOMICS, "atomics", "clk_m", V(16)), */ 317 /* GATE(SPDIF_DOUBLER, "spdif_doubler", "clk_m", V(22)), */ 318 GATE(ACTMON, "actmon", "pc_actmon", V(23)), 319 GATE(EXTERN1, "extperiph1", "pc_extperiph1", V(24)), 320 GATE(EXTERN2, "extperiph2", "pc_extperiph2", V(25)), 321 GATE(EXTERN3, "extperiph3", "pc_extperiph3", V(26)), 322 GATE(SATA_OOB, "sata_oob", "pc_sata_oob", V(27)), 323 GATE(SATA, "sata", "pc_sata", V(28)), 324 GATE(HDA, "hda", "pc_hda", V(29)), 325 326 /* bank W -> 128-159*/ 327 GATE(HDA2HDMI, "hda2hdmi", "clk_m", W(0)), 328 GATE(SATA_COLD, "sata_cold", "clk_m", W(1)), /* Reset only */ 329 /* GATE(PCIERX0, "pcierx0", "clk_m", W(2)), */ 330 /* GATE(PCIERX1, "pcierx1", "clk_m", W(3)), */ 331 /* GATE(PCIERX2, "pcierx2", "clk_m", W(4)), */ 332 /* GATE(PCIERX3, "pcierx3", "clk_m", W(5)), */ 333 /* GATE(PCIERX4, "pcierx4", "clk_m", W(6)), */ 334 /* GATE(PCIERX5, "pcierx5", "clk_m", W(7)), */ 335 /* GATE(CEC, "cec", "clk_m", W(8)), */ 336 /* GATE(PCIE2_IOBIST, "pcie2_iobist", "clk_m", W(9)), */ 337 /* GATE(EMC_IOBIST, "emc_iobist", "clk_m", W(10)), */ 338 /* GATE(HDMI_IOBIST, "hdmi_iobist", "clk_m", W(11)), */ 339 /* GATE(SATA_IOBIST, "sata_iobist", "clk_m", W(12)), */ 340 /* GATE(MIPI_IOBIST, "mipi_iobist", "clk_m", W(13)), */ 341 GATE(XUSB_GATE, "xusb_gate", "clk_m", W(15)), 342 GATE(CILAB, "cilab", "pc_cilab", W(16)), 343 GATE(CILCD, "cilcd", "pc_cilcd", W(17)), 344 GATE(CILE, "cile", "pc_cile", W(18)), 345 GATE(DSIALP, "dsia_lp", "pc_dsia_lp", W(19)), 346 GATE(DSIBLP, "dsib_lp", "pc_dsib_lp", W(20)), 347 GATE(ENTROPY, "entropy", "pc_entropy", W(21)), 348 GATE(AMX, "amx", "pc_amx", W(25)), 349 GATE(ADX, "adx", "pc_adx", W(26)), 350 GATE(DFLL_REF, "dvfs_ref", "pc_dvfs_ref", W(27)), 351 GATE(DFLL_SOC, "dvfs_soc", "pc_dvfs_soc", W(27)), 352 GATE(XUSB_SS, "xusb_ss", "xusb_ss_mux", W(28)), 353 /* GATE(EMC_LATENCY, "emc_latency", "pc_emc_latency", W(29)), */ 354 355 /* bank X -> 160-191*/ 356 /* GATE(SPARE, "spare", "clk_m", X(0)), */ 357 /* GATE(CAM_MCLK, "CAM_MCLK", "clk_m", X(4)), */ 358 /* GATE(CAM_MCLK2, "CAM_MCLK2", "clk_m", X(5)), */ 359 GATE(I2C6, "i2c6", "pc_i2c6", X(6)), 360 GATE(VIM2_CLK, "vim2_clk", "clk_m", X(11)), 361 /* GATE(EMC_DLL, "emc_dll", "pc_emc_dll", X(14)), */ 362 GATE(HDMI_AUDIO, "hdmi_audio", "pc_hdmi_audio", X(16)), 363 GATE(CLK72MHZ, "clk72mhz", "pc_clk72mhz", X(17)), 364 GATE(VIC03, "vic", "pc_vic", X(18)), 365 GATE(ADX1, "adx1", "pc_adx1", X(20)), 366 GATE(DPAUX, "dpaux", "clk_m", X(21)), 367 GATE(SOR0_LVDS, "sor0", "pc_sor0", X(22)), 368 GATE(GPU, "gpu", "osc_div_clk", X(24)), 369 GATE(AMX1, "amx1", "pc_amx1", X(26)), 370 }; 371 372 /* Peripheral clock clock */ 373 #define DCF_HAVE_MUX 0x0100 /* Block with multipexor */ 374 #define DCF_HAVE_ENA 0x0200 /* Block with enable bit */ 375 #define DCF_HAVE_DIV 0x0400 /* Block with divider */ 376 377 /* Mark block with additional bits / functionality. */ 378 #define DCF_IS_MASK 0x00FF 379 #define DCF_IS_UART 0x0001 380 #define DCF_IS_VI 0x0002 381 #define DCF_IS_HOST1X 0x0003 382 #define DCF_IS_XUSB_SS 0x0004 383 #define DCF_IS_EMC_DLL 0x0005 384 #define DCF_IS_SATA 0x0006 385 #define DCF_IS_VIC 0x0007 386 #define DCF_IS_AUDIO 0x0008 387 #define DCF_IS_SOR0 0x0009 388 #define DCF_IS_EMC 0x000A 389 390 /* Basic pheripheral clock */ 391 #define PER_CLK(_id, cn, pl, r, diw, fiw, f) \ 392 { \ 393 .clkdef.id = _id, \ 394 .clkdef.name = cn, \ 395 .clkdef.parent_names = pl, \ 396 .clkdef.parent_cnt = nitems(pl), \ 397 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 398 .base_reg = r, \ 399 .div_width = diw, \ 400 .div_f_width = fiw, \ 401 .flags = f, \ 402 } 403 404 /* Mux with fractional 8.1 divider. */ 405 #define CLK_8_1(id, cn, pl, r, f) \ 406 PER_CLK(id, cn, pl, r, 8, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV) 407 408 /* Mux with fractional 16.1 divider. */ 409 #define CLK16_1(id, cn, pl, r, f) \ 410 PER_CLK(id, cn, pl, r, 16, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV) 411 /* Mux with integer 16bits divider. */ 412 #define CLK16_0(id, cn, pl, r, f) \ 413 PER_CLK(id, cn, pl, r, 16, 0, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV) 414 /* Mux wihout divider. */ 415 #define CLK_0_0(id, cn, pl, r, f) \ 416 PER_CLK(id, cn, pl, r, 0, 0, (f) | DCF_HAVE_MUX) 417 418 static struct periph_def periph_def[] = { 419 CLK_8_1(0, "pc_i2s1", mux_a_N_audio1_N_p_N_clkm, CLK_SOURCE_I2S1, DCF_HAVE_ENA), 420 CLK_8_1(0, "pc_i2s2", mux_a_N_audio2_N_p_N_clkm, CLK_SOURCE_I2S2, DCF_HAVE_ENA), 421 CLK_8_1(0, "pc_spdif_out", mux_a_N_audio_N_p_N_clkm, CLK_SOURCE_SPDIF_OUT, 0), 422 CLK_8_1(0, "pc_spdif_in", mux_p_c2_c_c3_m, CLK_SOURCE_SPDIF_IN, 0), 423 CLK_8_1(0, "pc_pwm", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_PWM, 0), 424 CLK_8_1(0, "pc_spi2", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI2, 0), 425 CLK_8_1(0, "pc_spi3", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI3, 0), 426 CLK16_0(0, "pc_i2c5", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C5, 0), 427 CLK16_0(0, "pc_i2c1", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C1, 0), 428 CLK_8_1(0, "pc_spi1", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI1, 0), 429 CLK_0_0(0, "pc_disp1", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_DISP1, 0), 430 CLK_0_0(0, "pc_disp2", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_DISP2, 0), 431 CLK_8_1(0, "pc_isp", mux_m_c_p_a_c2_c3_clkm_c4, CLK_SOURCE_ISP, 0), 432 CLK_8_1(0, "pc_vi", mux_m_c2_c_c3_p_N_a_c4, CLK_SOURCE_VI, DCF_IS_VI), 433 CLK_8_1(0, "pc_sdmmc1", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC1, 0), 434 CLK_8_1(0, "pc_sdmmc2", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC2, 0), 435 CLK_8_1(0, "pc_sdmmc4", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC4, 0), 436 CLK_8_1(0, "pc_vfir", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_VFIR, 0), 437 CLK_8_1(0, "pc_hsi", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HSI, 0), 438 CLK16_1(0, "pc_uarta", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTA, DCF_IS_UART), 439 CLK16_1(0, "pc_uartb", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTB, DCF_IS_UART), 440 CLK_8_1(0, "pc_host1x", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HOST1X, DCF_IS_HOST1X), 441 CLK_8_1(0, "pc_hdmi", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_HDMI, 0), 442 CLK16_0(0, "pc_i2c2", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C2, 0), 443 CLK_8_1(0, "pc_emc_2x", mux_m_c_p_clkm_mud_c2_c3_cud, CLK_SOURCE_EMC, DCF_IS_EMC), 444 CLK16_1(0, "pc_uartc", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTC, DCF_IS_UART), 445 CLK_8_1(0, "pc_vi_sensor", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR, 0), 446 CLK_8_1(0, "pc_spi4", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI4, 0), 447 CLK16_0(0, "pc_i2c3", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C3, 0), 448 CLK_8_1(0, "pc_sdmmc3", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC3, 0), 449 CLK16_1(0, "pc_uartd", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTD, DCF_IS_UART), 450 CLK_8_1(0, "pc_vde", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_VDE, 0), 451 CLK_8_1(0, "pc_owr", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_OWR, 0), 452 CLK_8_1(0, "pc_snor", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_NOR, 0), 453 CLK_8_1(0, "pc_csite", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_CSITE, 0), 454 CLK_8_1(0, "pc_i2s0", mux_a_N_audio0_N_p_N_clkm, CLK_SOURCE_I2S0, 0), 455 /* DTV xxx */ 456 CLK_8_1(0, "pc_msenc", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_MSENC, 0), 457 CLK_8_1(0, "pc_tsec", mux_p_c2_c_c3_m_a_clkm, CLK_SOURCE_TSEC, 0), 458 /* SPARE2 */ 459 460 CLK_8_1(0, "pc_mselect", mux_p_c2_c_c3_m_clks_clkm, CLK_SOURCE_MSELECT, 0), 461 CLK_8_1(0, "pc_tsensor", mux_p_c2_c_c3_clkm_N_clks, CLK_SOURCE_TSENSOR, 0), 462 CLK_8_1(0, "pc_i2s3", mux_a_N_audio3_N_p_N_clkm, CLK_SOURCE_I2S3, DCF_HAVE_ENA), 463 CLK_8_1(0, "pc_i2s4", mux_a_N_audio4_N_p_N_clkm, CLK_SOURCE_I2S4, DCF_HAVE_ENA), 464 CLK16_0(0, "pc_i2c4", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C4, 0), 465 CLK_8_1(0, "pc_spi5", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI5, 0), 466 CLK_8_1(0, "pc_spi6", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI6, 0), 467 CLK_8_1(0, "pc_audio", mux_sep_audio, CLK_SOURCE_AUDIO, DCF_IS_AUDIO), 468 CLK_8_1(0, "pc_dam0", mux_sep_audio, CLK_SOURCE_DAM0, DCF_IS_AUDIO), 469 CLK_8_1(0, "pc_dam1", mux_sep_audio, CLK_SOURCE_DAM1, DCF_IS_AUDIO), 470 CLK_8_1(0, "pc_dam2", mux_sep_audio, CLK_SOURCE_DAM2, DCF_IS_AUDIO), 471 CLK_8_1(0, "pc_hda2codec_2x", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HDA2CODEC_2X, 0), 472 CLK_8_1(0, "pc_actmon", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_ACTMON, 0), 473 CLK_8_1(0, "pc_extperiph1", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH1, 0), 474 CLK_8_1(0, "pc_extperiph2", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH2, 0), 475 CLK_8_1(0, "pc_extperiph3", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH3, 0), 476 CLK_8_1(0, "pc_i2c_slow", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_I2C_SLOW, 0), 477 /* SYS */ 478 CLK_8_1(0, "pc_sor0", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_SOR0, DCF_IS_SOR0), 479 CLK_8_1(0, "pc_sata_oob", mux_p_N_c_N_m_N_clkm, CLK_SOURCE_SATA_OOB, 0), 480 CLK_8_1(0, "pc_sata", mux_p_N_c_N_m_N_clkm, CLK_SOURCE_SATA, DCF_IS_SATA), 481 CLK_8_1(0, "pc_hda", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HDA, 0), 482 CLK_8_1(TEGRA124_CLK_XUSB_HOST_SRC, 483 "pc_xusb_core_host", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_CORE_HOST, 0), 484 CLK_8_1(TEGRA124_CLK_XUSB_FALCON_SRC, 485 "pc_xusb_falcon", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_FALCON, 0), 486 CLK_8_1(TEGRA124_CLK_XUSB_FS_SRC, 487 "pc_xusb_fs", mux_clkm_N_u48_N_p_N_u480, CLK_SOURCE_XUSB_FS, 0), 488 CLK_8_1(TEGRA124_CLK_XUSB_DEV_SRC, 489 "pc_xusb_core_dev", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_CORE_DEV, 0), 490 CLK_8_1(TEGRA124_CLK_XUSB_SS_SRC, 491 "pc_xusb_ss", mux_clkm_refe_clks_u480_c_c2_c3_oscdiv, CLK_SOURCE_XUSB_SS, DCF_IS_XUSB_SS), 492 CLK_8_1(0, "pc_cilab", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILAB, 0), 493 CLK_8_1(0, "pc_cilcd", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILCD, 0), 494 CLK_8_1(0, "pc_cile", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILE, 0), 495 CLK_8_1(0, "pc_dsia_lp", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_DSIA_LP, 0), 496 CLK_8_1(0, "pc_dsib_lp", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_DSIB_LP, 0), 497 CLK_8_1(0, "pc_entropy", mux_p_clkm_clks_E, CLK_SOURCE_ENTROPY, 0), 498 CLK_8_1(0, "pc_dvfs_ref", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_DVFS_REF, DCF_HAVE_ENA), 499 CLK_8_1(0, "pc_dvfs_soc", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_DVFS_SOC, DCF_HAVE_ENA), 500 CLK_8_1(0, "pc_traceclkin", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_TRACECLKIN, 0), 501 CLK_8_1(0, "pc_adx", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_ADX, DCF_HAVE_ENA), 502 CLK_8_1(0, "pc_amx", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_AMX, DCF_HAVE_ENA), 503 CLK_8_1(0, "pc_emc_latency", mux_m_c_p_clkm_mud_c2_c3, CLK_SOURCE_EMC_LATENCY, 0), 504 CLK_8_1(0, "pc_soc_therm", mux_m_c_p_a_c2_c3, CLK_SOURCE_SOC_THERM, 0), 505 CLK_8_1(0, "pc_vi_sensor2", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR2, 0), 506 CLK16_0(0, "pc_i2c6", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C6, 0), 507 CLK_8_1(0, "pc_emc_dll", mux_m_c_p_clkm_mud_c2_c3, CLK_SOURCE_EMC_DLL, DCF_IS_EMC_DLL), 508 CLK_8_1(0, "pc_hdmi_audio", mux_p_c_c2_clkm, CLK_SOURCE_HDMI_AUDIO, 0), 509 CLK_8_1(0, "pc_clk72mhz", mux_p_c_c2_clkm, CLK_SOURCE_CLK72MHZ, 0), 510 CLK_8_1(0, "pc_adx1", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_ADX1, DCF_HAVE_ENA), 511 CLK_8_1(0, "pc_amx1", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_AMX1, DCF_HAVE_ENA), 512 CLK_8_1(0, "pc_vic", mux_m_c_p_a_c2_c3_clkm, CLK_SOURCE_VIC, DCF_IS_VIC), 513 }; 514 515 static int periph_init(struct clknode *clk, device_t dev); 516 static int periph_recalc(struct clknode *clk, uint64_t *freq); 517 static int periph_set_freq(struct clknode *clk, uint64_t fin, 518 uint64_t *fout, int flags, int *stop); 519 static int periph_set_mux(struct clknode *clk, int idx); 520 521 struct periph_sc { 522 device_t clkdev; 523 uint32_t base_reg; 524 uint32_t div_shift; 525 uint32_t div_width; 526 uint32_t div_mask; 527 uint32_t div_f_width; 528 uint32_t div_f_mask; 529 uint32_t flags; 530 531 uint32_t divider; 532 int mux; 533 }; 534 535 static clknode_method_t periph_methods[] = { 536 /* Device interface */ 537 CLKNODEMETHOD(clknode_init, periph_init), 538 CLKNODEMETHOD(clknode_recalc_freq, periph_recalc), 539 CLKNODEMETHOD(clknode_set_freq, periph_set_freq), 540 CLKNODEMETHOD(clknode_set_mux, periph_set_mux), 541 CLKNODEMETHOD_END 542 }; 543 DEFINE_CLASS_1(tegra124_periph, tegra124_periph_class, periph_methods, 544 sizeof(struct periph_sc), clknode_class); 545 546 static int 547 periph_init(struct clknode *clk, device_t dev) 548 { 549 struct periph_sc *sc; 550 uint32_t reg; 551 sc = clknode_get_softc(clk); 552 553 DEVICE_LOCK(sc); 554 if (sc->flags & DCF_HAVE_ENA) 555 MD4(sc, sc->base_reg, PERLCK_ENA_MASK, PERLCK_ENA_MASK); 556 557 RD4(sc, sc->base_reg, ®); 558 DEVICE_UNLOCK(sc); 559 560 /* Stnadard mux. */ 561 if (sc->flags & DCF_HAVE_MUX) 562 sc->mux = (reg >> PERLCK_MUX_SHIFT) & PERLCK_MUX_MASK; 563 else 564 sc->mux = 0; 565 if (sc->flags & DCF_HAVE_DIV) 566 sc->divider = (reg & sc->div_mask) + 2; 567 else 568 sc->divider = 1; 569 if ((sc->flags & DCF_IS_MASK) == DCF_IS_UART) { 570 if (!(reg & PERLCK_UDIV_DIS)) 571 sc->divider = 2; 572 } 573 574 /* AUDIO MUX */ 575 if ((sc->flags & DCF_IS_MASK) == DCF_IS_AUDIO) { 576 if (!(reg & PERLCK_AMUX_DIS) && (sc->mux == 7)) { 577 sc->mux = 8 + 578 ((reg >> PERLCK_AMUX_SHIFT) & PERLCK_MUX_MASK); 579 } 580 } 581 clknode_init_parent_idx(clk, sc->mux); 582 return(0); 583 } 584 585 static int 586 periph_set_mux(struct clknode *clk, int idx) 587 { 588 struct periph_sc *sc; 589 uint32_t reg; 590 591 sc = clknode_get_softc(clk); 592 if (!(sc->flags & DCF_HAVE_MUX)) 593 return (ENXIO); 594 595 sc->mux = idx; 596 DEVICE_LOCK(sc); 597 RD4(sc, sc->base_reg, ®); 598 reg &= ~(PERLCK_MUX_MASK << PERLCK_MUX_SHIFT); 599 if ((sc->flags & DCF_IS_MASK) == DCF_IS_AUDIO) { 600 reg &= ~PERLCK_AMUX_DIS; 601 reg &= ~(PERLCK_MUX_MASK << PERLCK_AMUX_SHIFT); 602 603 if (idx <= 7) { 604 reg |= idx << PERLCK_MUX_SHIFT; 605 } else { 606 reg |= 7 << PERLCK_MUX_SHIFT; 607 reg |= (idx - 8) << PERLCK_AMUX_SHIFT; 608 } 609 } else { 610 reg |= idx << PERLCK_MUX_SHIFT; 611 } 612 WR4(sc, sc->base_reg, reg); 613 DEVICE_UNLOCK(sc); 614 615 return(0); 616 } 617 618 static int 619 periph_recalc(struct clknode *clk, uint64_t *freq) 620 { 621 struct periph_sc *sc; 622 uint32_t reg; 623 624 sc = clknode_get_softc(clk); 625 626 if (sc->flags & DCF_HAVE_DIV) { 627 DEVICE_LOCK(sc); 628 RD4(sc, sc->base_reg, ®); 629 DEVICE_UNLOCK(sc); 630 *freq = (*freq << sc->div_f_width) / sc->divider; 631 } 632 return (0); 633 } 634 635 static int 636 periph_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout, 637 int flags, int *stop) 638 { 639 struct periph_sc *sc; 640 uint64_t tmp, divider; 641 642 sc = clknode_get_softc(clk); 643 if (!(sc->flags & DCF_HAVE_DIV)) { 644 *stop = 0; 645 return (0); 646 } 647 648 tmp = fin << sc->div_f_width; 649 divider = tmp / *fout; 650 if ((tmp % *fout) != 0) 651 divider++; 652 653 if (divider < (1 << sc->div_f_width)) 654 divider = 1 << (sc->div_f_width - 1); 655 656 if (flags & CLK_SET_DRYRUN) { 657 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) && 658 (*fout != (tmp / divider))) 659 return (ERANGE); 660 } else { 661 DEVICE_LOCK(sc); 662 MD4(sc, sc->base_reg, sc->div_mask, 663 (divider - (1 << sc->div_f_width))); 664 DEVICE_UNLOCK(sc); 665 sc->divider = divider; 666 } 667 *fout = tmp / divider; 668 *stop = 1; 669 return (0); 670 } 671 672 static int 673 periph_register(struct clkdom *clkdom, struct periph_def *clkdef) 674 { 675 struct clknode *clk; 676 struct periph_sc *sc; 677 678 clk = clknode_create(clkdom, &tegra124_periph_class, &clkdef->clkdef); 679 if (clk == NULL) 680 return (1); 681 682 sc = clknode_get_softc(clk); 683 sc->clkdev = clknode_get_device(clk); 684 sc->base_reg = clkdef->base_reg; 685 sc->div_width = clkdef->div_width; 686 sc->div_mask = (1 <<clkdef->div_width) - 1; 687 sc->div_f_width = clkdef->div_f_width; 688 sc->div_f_mask = (1 <<clkdef->div_f_width) - 1; 689 sc->flags = clkdef->flags; 690 691 clknode_register(clkdom, clk); 692 return (0); 693 } 694 695 /* -------------------------------------------------------------------------- */ 696 static int pgate_init(struct clknode *clk, device_t dev); 697 static int pgate_set_gate(struct clknode *clk, bool enable); 698 static int pgate_get_gate(struct clknode *clk, bool *enableD); 699 700 struct pgate_sc { 701 device_t clkdev; 702 uint32_t idx; 703 uint32_t flags; 704 uint32_t enabled; 705 706 }; 707 708 static clknode_method_t pgate_methods[] = { 709 /* Device interface */ 710 CLKNODEMETHOD(clknode_init, pgate_init), 711 CLKNODEMETHOD(clknode_set_gate, pgate_set_gate), 712 CLKNODEMETHOD(clknode_get_gate, pgate_get_gate), 713 CLKNODEMETHOD_END 714 }; 715 DEFINE_CLASS_1(tegra124_pgate, tegra124_pgate_class, pgate_methods, 716 sizeof(struct pgate_sc), clknode_class); 717 718 static uint32_t 719 get_enable_reg(int idx) 720 { 721 KASSERT(idx / 32 < nitems(clk_enable_reg), 722 ("Invalid clock index for enable: %d", idx)); 723 return (clk_enable_reg[idx / 32]); 724 } 725 726 static uint32_t 727 get_reset_reg(int idx) 728 { 729 KASSERT(idx / 32 < nitems(clk_reset_reg), 730 ("Invalid clock index for reset: %d", idx)); 731 return (clk_reset_reg[idx / 32]); 732 } 733 734 static int 735 pgate_init(struct clknode *clk, device_t dev) 736 { 737 struct pgate_sc *sc; 738 uint32_t ena_reg, rst_reg, mask; 739 740 sc = clknode_get_softc(clk); 741 mask = 1 << (sc->idx % 32); 742 743 DEVICE_LOCK(sc); 744 RD4(sc, get_enable_reg(sc->idx), &ena_reg); 745 RD4(sc, get_reset_reg(sc->idx), &rst_reg); 746 DEVICE_UNLOCK(sc); 747 748 sc->enabled = ena_reg & mask ? 1 : 0; 749 clknode_init_parent_idx(clk, 0); 750 751 return(0); 752 } 753 754 static int 755 pgate_set_gate(struct clknode *clk, bool enable) 756 { 757 struct pgate_sc *sc; 758 uint32_t reg, mask, base_reg; 759 760 sc = clknode_get_softc(clk); 761 mask = 1 << (sc->idx % 32); 762 sc->enabled = enable; 763 base_reg = get_enable_reg(sc->idx); 764 765 DEVICE_LOCK(sc); 766 MD4(sc, base_reg, mask, enable ? mask : 0); 767 RD4(sc, base_reg, ®); 768 DEVICE_UNLOCK(sc); 769 770 DELAY(2); 771 return(0); 772 } 773 774 static int 775 pgate_get_gate(struct clknode *clk, bool *enabled) 776 { 777 struct pgate_sc *sc; 778 uint32_t reg, mask, base_reg; 779 780 sc = clknode_get_softc(clk); 781 mask = 1 << (sc->idx % 32); 782 base_reg = get_enable_reg(sc->idx); 783 784 DEVICE_LOCK(sc); 785 RD4(sc, base_reg, ®); 786 DEVICE_UNLOCK(sc); 787 *enabled = reg & mask ? true: false; 788 789 return(0); 790 } 791 int 792 tegra124_hwreset_by_idx(struct tegra124_car_softc *sc, intptr_t idx, bool reset) 793 { 794 uint32_t reg, mask, reset_reg; 795 796 mask = 1 << (idx % 32); 797 reset_reg = get_reset_reg(idx); 798 799 CLKDEV_DEVICE_LOCK(sc->dev); 800 CLKDEV_MODIFY_4(sc->dev, reset_reg, mask, reset ? mask : 0); 801 CLKDEV_READ_4(sc->dev, reset_reg, ®); 802 CLKDEV_DEVICE_UNLOCK(sc->dev); 803 804 return(0); 805 } 806 807 static int 808 pgate_register(struct clkdom *clkdom, struct pgate_def *clkdef) 809 { 810 struct clknode *clk; 811 struct pgate_sc *sc; 812 813 clk = clknode_create(clkdom, &tegra124_pgate_class, &clkdef->clkdef); 814 if (clk == NULL) 815 return (1); 816 817 sc = clknode_get_softc(clk); 818 sc->clkdev = clknode_get_device(clk); 819 sc->idx = clkdef->idx; 820 sc->flags = clkdef->flags; 821 822 clknode_register(clkdom, clk); 823 return (0); 824 } 825 826 void 827 tegra124_periph_clock(struct tegra124_car_softc *sc) 828 { 829 int i, rv; 830 831 for (i = 0; i < nitems(periph_def); i++) { 832 rv = periph_register(sc->clkdom, &periph_def[i]); 833 if (rv != 0) 834 panic("tegra124_periph_register failed"); 835 } 836 for (i = 0; i < nitems(pgate_def); i++) { 837 rv = pgate_register(sc->clkdom, &pgate_def[i]); 838 if (rv != 0) 839 panic("tegra124_pgate_register failed"); 840 } 841 842 } 843