1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Vybrid Family Synchronous Audio Interface (SAI) 31 * Chapter 51, Vybrid Reference Manual, Rev. 5, 07/2013 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/malloc.h> 40 #include <sys/rman.h> 41 #include <sys/timeet.h> 42 #include <sys/timetc.h> 43 #include <sys/watchdog.h> 44 45 #include <dev/sound/pcm/sound.h> 46 #include <dev/sound/chip.h> 47 #include <mixer_if.h> 48 49 #include <dev/ofw/openfirm.h> 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 53 #include <machine/bus.h> 54 #include <machine/cpu.h> 55 #include <machine/intr.h> 56 57 #include <arm/freescale/vybrid/vf_common.h> 58 #include <arm/freescale/vybrid/vf_dmamux.h> 59 #include <arm/freescale/vybrid/vf_edma.h> 60 61 #define I2S_TCSR 0x00 /* SAI Transmit Control */ 62 #define I2S_TCR1 0x04 /* SAI Transmit Configuration 1 */ 63 #define I2S_TCR2 0x08 /* SAI Transmit Configuration 2 */ 64 #define I2S_TCR3 0x0C /* SAI Transmit Configuration 3 */ 65 #define I2S_TCR4 0x10 /* SAI Transmit Configuration 4 */ 66 #define I2S_TCR5 0x14 /* SAI Transmit Configuration 5 */ 67 #define I2S_TDR0 0x20 /* SAI Transmit Data */ 68 #define I2S_TFR0 0x40 /* SAI Transmit FIFO */ 69 #define I2S_TMR 0x60 /* SAI Transmit Mask */ 70 #define I2S_RCSR 0x80 /* SAI Receive Control */ 71 #define I2S_RCR1 0x84 /* SAI Receive Configuration 1 */ 72 #define I2S_RCR2 0x88 /* SAI Receive Configuration 2 */ 73 #define I2S_RCR3 0x8C /* SAI Receive Configuration 3 */ 74 #define I2S_RCR4 0x90 /* SAI Receive Configuration 4 */ 75 #define I2S_RCR5 0x94 /* SAI Receive Configuration 5 */ 76 #define I2S_RDR0 0xA0 /* SAI Receive Data */ 77 #define I2S_RFR0 0xC0 /* SAI Receive FIFO */ 78 #define I2S_RMR 0xE0 /* SAI Receive Mask */ 79 80 #define TCR1_TFW_M 0x1f /* Transmit FIFO Watermark Mask */ 81 #define TCR1_TFW_S 0 /* Transmit FIFO Watermark Shift */ 82 #define TCR2_MSEL_M 0x3 /* MCLK Select Mask*/ 83 #define TCR2_MSEL_S 26 /* MCLK Select Shift*/ 84 #define TCR2_BCP (1 << 25) /* Bit Clock Polarity */ 85 #define TCR2_BCD (1 << 24) /* Bit Clock Direction */ 86 #define TCR3_TCE (1 << 16) /* Transmit Channel Enable */ 87 #define TCR4_FRSZ_M 0x1f /* Frame size Mask */ 88 #define TCR4_FRSZ_S 16 /* Frame size Shift */ 89 #define TCR4_SYWD_M 0x1f /* Sync Width Mask */ 90 #define TCR4_SYWD_S 8 /* Sync Width Shift */ 91 #define TCR4_MF (1 << 4) /* MSB First */ 92 #define TCR4_FSE (1 << 3) /* Frame Sync Early */ 93 #define TCR4_FSP (1 << 1) /* Frame Sync Polarity Low */ 94 #define TCR4_FSD (1 << 0) /* Frame Sync Direction Master */ 95 #define TCR5_FBT_M 0x1f /* First Bit Shifted */ 96 #define TCR5_FBT_S 8 /* First Bit Shifted */ 97 #define TCR5_W0W_M 0x1f /* Word 0 Width */ 98 #define TCR5_W0W_S 16 /* Word 0 Width */ 99 #define TCR5_WNW_M 0x1f /* Word N Width */ 100 #define TCR5_WNW_S 24 /* Word N Width */ 101 #define TCSR_TE (1 << 31) /* Transmitter Enable */ 102 #define TCSR_BCE (1 << 28) /* Bit Clock Enable */ 103 #define TCSR_FRDE (1 << 0) /* FIFO Request DMA Enable */ 104 105 #define SAI_NCHANNELS 1 106 107 static MALLOC_DEFINE(M_SAI, "sai", "sai audio"); 108 109 struct sai_rate { 110 uint32_t speed; 111 uint32_t div; /* Bit Clock Divide. Division value is (div + 1) * 2. */ 112 uint32_t mfi; /* PLL4 Multiplication Factor Integer */ 113 uint32_t mfn; /* PLL4 Multiplication Factor Numerator */ 114 uint32_t mfd; /* PLL4 Multiplication Factor Denominator */ 115 }; 116 117 /* 118 * Bit clock divider formula 119 * (div + 1) * 2 = MCLK/(nch * LRCLK * bits/1000000), 120 * where: 121 * MCLK - master clock 122 * nch - number of channels 123 * LRCLK - left right clock 124 * e.g. (div + 1) * 2 = 16.9344/(2 * 44100 * 24/1000000) 125 * 126 * Example for 96khz, 24bit, 18.432 Mhz mclk (192fs) 127 * { 96000, 1, 18, 40176000, 93000000 }, 128 */ 129 130 static struct sai_rate rate_map[] = { 131 { 44100, 7, 33, 80798400, 93000000 }, /* 33.8688 Mhz */ 132 { 96000, 3, 36, 80352000, 93000000 }, /* 36.864 Mhz */ 133 { 192000, 1, 36, 80352000, 93000000 }, /* 36.864 Mhz */ 134 { 0, 0 }, 135 }; 136 137 struct sc_info { 138 struct resource *res[2]; 139 bus_space_tag_t bst; 140 bus_space_handle_t bsh; 141 device_t dev; 142 struct mtx *lock; 143 uint32_t speed; 144 uint32_t period; 145 void *ih; 146 int pos; 147 int dma_size; 148 bus_dma_tag_t dma_tag; 149 bus_dmamap_t dma_map; 150 bus_addr_t buf_base_phys; 151 uint32_t *buf_base; 152 struct tcd_conf *tcd; 153 struct sai_rate *sr; 154 struct edma_softc *edma_sc; 155 int edma_chnum; 156 }; 157 158 /* Channel registers */ 159 struct sc_chinfo { 160 struct snd_dbuf *buffer; 161 struct pcm_channel *channel; 162 struct sc_pcminfo *parent; 163 164 /* Channel information */ 165 uint32_t dir; 166 uint32_t format; 167 168 /* Flags */ 169 uint32_t run; 170 }; 171 172 /* PCM device private data */ 173 struct sc_pcminfo { 174 device_t dev; 175 uint32_t (*ih) (struct sc_pcminfo *scp); 176 uint32_t chnum; 177 struct sc_chinfo chan[SAI_NCHANNELS]; 178 struct sc_info *sc; 179 }; 180 181 static struct resource_spec sai_spec[] = { 182 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 183 { SYS_RES_IRQ, 0, RF_ACTIVE }, 184 { -1, 0 } 185 }; 186 187 static int setup_dma(struct sc_pcminfo *scp); 188 static void setup_sai(struct sc_info *); 189 static void sai_configure_clock(struct sc_info *); 190 191 /* 192 * Mixer interface. 193 */ 194 195 static int 196 saimixer_init(struct snd_mixer *m) 197 { 198 struct sc_pcminfo *scp; 199 struct sc_info *sc; 200 int mask; 201 202 scp = mix_getdevinfo(m); 203 sc = scp->sc; 204 205 if (sc == NULL) 206 return -1; 207 208 mask = SOUND_MASK_PCM; 209 210 snd_mtxlock(sc->lock); 211 pcm_setflags(scp->dev, pcm_getflags(scp->dev) | SD_F_SOFTPCMVOL); 212 mix_setdevs(m, mask); 213 snd_mtxunlock(sc->lock); 214 215 return (0); 216 } 217 218 static int 219 saimixer_set(struct snd_mixer *m, unsigned dev, 220 unsigned left, unsigned right) 221 { 222 #if 0 223 struct sc_pcminfo *scp; 224 225 scp = mix_getdevinfo(m); 226 227 device_printf(scp->dev, "saimixer_set() %d %d\n", 228 left, right); 229 #endif 230 231 return (0); 232 } 233 234 static kobj_method_t saimixer_methods[] = { 235 KOBJMETHOD(mixer_init, saimixer_init), 236 KOBJMETHOD(mixer_set, saimixer_set), 237 KOBJMETHOD_END 238 }; 239 MIXER_DECLARE(saimixer); 240 241 /* 242 * Channel interface. 243 */ 244 245 static void * 246 saichan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 247 struct pcm_channel *c, int dir) 248 { 249 struct sc_pcminfo *scp; 250 struct sc_chinfo *ch; 251 struct sc_info *sc; 252 253 scp = (struct sc_pcminfo *)devinfo; 254 sc = scp->sc; 255 256 snd_mtxlock(sc->lock); 257 ch = &scp->chan[0]; 258 ch->dir = dir; 259 ch->run = 0; 260 ch->buffer = b; 261 ch->channel = c; 262 ch->parent = scp; 263 snd_mtxunlock(sc->lock); 264 265 if (sndbuf_setup(ch->buffer, sc->buf_base, sc->dma_size) != 0) { 266 device_printf(scp->dev, "Can't setup sndbuf.\n"); 267 return NULL; 268 } 269 270 return ch; 271 } 272 273 static int 274 saichan_free(kobj_t obj, void *data) 275 { 276 struct sc_chinfo *ch = data; 277 struct sc_pcminfo *scp = ch->parent; 278 struct sc_info *sc = scp->sc; 279 280 #if 0 281 device_printf(scp->dev, "saichan_free()\n"); 282 #endif 283 284 snd_mtxlock(sc->lock); 285 /* TODO: free channel buffer */ 286 snd_mtxunlock(sc->lock); 287 288 return (0); 289 } 290 291 static int 292 saichan_setformat(kobj_t obj, void *data, uint32_t format) 293 { 294 struct sc_chinfo *ch = data; 295 296 ch->format = format; 297 298 return (0); 299 } 300 301 static uint32_t 302 saichan_setspeed(kobj_t obj, void *data, uint32_t speed) 303 { 304 struct sc_pcminfo *scp; 305 struct sc_chinfo *ch; 306 struct sai_rate *sr; 307 struct sc_info *sc; 308 int threshold; 309 int i; 310 311 ch = data; 312 scp = ch->parent; 313 sc = scp->sc; 314 315 sr = NULL; 316 317 /* First look for equal frequency. */ 318 for (i = 0; rate_map[i].speed != 0; i++) { 319 if (rate_map[i].speed == speed) 320 sr = &rate_map[i]; 321 } 322 323 /* If no match, just find nearest. */ 324 if (sr == NULL) { 325 for (i = 0; rate_map[i].speed != 0; i++) { 326 sr = &rate_map[i]; 327 threshold = sr->speed + ((rate_map[i + 1].speed != 0) ? 328 ((rate_map[i + 1].speed - sr->speed) >> 1) : 0); 329 if (speed < threshold) 330 break; 331 } 332 } 333 334 sc->sr = sr; 335 336 sai_configure_clock(sc); 337 338 return (sr->speed); 339 } 340 341 static void 342 sai_configure_clock(struct sc_info *sc) 343 { 344 struct sai_rate *sr; 345 int reg; 346 347 sr = sc->sr; 348 349 /* 350 * Manual says that TCR/RCR registers must not be 351 * altered when TCSR[TE] is set. 352 * We ignore it since we have problem sometimes 353 * after re-enabling transmitter (DMA goes stall). 354 */ 355 356 reg = READ4(sc, I2S_TCR2); 357 reg &= ~(0xff << 0); 358 reg |= (sr->div << 0); 359 WRITE4(sc, I2S_TCR2, reg); 360 361 pll4_configure_output(sr->mfi, sr->mfn, sr->mfd); 362 } 363 364 static uint32_t 365 saichan_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 366 { 367 struct sc_chinfo *ch = data; 368 struct sc_pcminfo *scp = ch->parent; 369 struct sc_info *sc = scp->sc; 370 371 sndbuf_resize(ch->buffer, sc->dma_size / blocksize, blocksize); 372 373 sc->period = sndbuf_getblksz(ch->buffer); 374 return (sc->period); 375 } 376 377 uint32_t sai_dma_intr(void *arg, int chn); 378 uint32_t 379 sai_dma_intr(void *arg, int chn) 380 { 381 struct sc_pcminfo *scp; 382 struct sc_chinfo *ch; 383 struct sc_info *sc; 384 struct tcd_conf *tcd; 385 386 scp = arg; 387 ch = &scp->chan[0]; 388 389 sc = scp->sc; 390 tcd = sc->tcd; 391 392 sc->pos += (tcd->nbytes * tcd->nmajor); 393 if (sc->pos >= sc->dma_size) 394 sc->pos -= sc->dma_size; 395 396 if (ch->run) 397 chn_intr(ch->channel); 398 399 return (0); 400 } 401 402 static int 403 find_edma_controller(struct sc_info *sc) 404 { 405 struct edma_softc *edma_sc; 406 phandle_t node, edma_node; 407 int edma_src_transmit; 408 int edma_mux_group; 409 int edma_device_id; 410 device_t edma_dev; 411 int dts_value; 412 int len; 413 int i; 414 415 if ((node = ofw_bus_get_node(sc->dev)) == -1) 416 return (ENXIO); 417 418 if ((len = OF_getproplen(node, "edma-controller")) <= 0) 419 return (ENXIO); 420 if ((len = OF_getproplen(node, "edma-src-transmit")) <= 0) 421 return (ENXIO); 422 if ((len = OF_getproplen(node, "edma-mux-group")) <= 0) 423 return (ENXIO); 424 425 OF_getencprop(node, "edma-src-transmit", &dts_value, len); 426 edma_src_transmit = dts_value; 427 OF_getencprop(node, "edma-mux-group", &dts_value, len); 428 edma_mux_group = dts_value; 429 OF_getencprop(node, "edma-controller", &dts_value, len); 430 edma_node = OF_node_from_xref(dts_value); 431 432 if ((len = OF_getproplen(edma_node, "device-id")) <= 0) { 433 return (ENXIO); 434 } 435 436 OF_getencprop(edma_node, "device-id", &dts_value, len); 437 edma_device_id = dts_value; 438 439 edma_sc = NULL; 440 441 for (i = 0; i < EDMA_NUM_DEVICES; i++) { 442 edma_dev = devclass_get_device(devclass_find("edma"), i); 443 if (edma_dev) { 444 edma_sc = device_get_softc(edma_dev); 445 if (edma_sc->device_id == edma_device_id) { 446 /* found */ 447 break; 448 } 449 450 edma_sc = NULL; 451 } 452 } 453 454 if (edma_sc == NULL) { 455 device_printf(sc->dev, "no eDMA. can't operate\n"); 456 return (ENXIO); 457 } 458 459 sc->edma_sc = edma_sc; 460 461 sc->edma_chnum = edma_sc->channel_configure(edma_sc, edma_mux_group, 462 edma_src_transmit); 463 if (sc->edma_chnum < 0) { 464 /* cant setup eDMA */ 465 return (ENXIO); 466 } 467 468 return (0); 469 }; 470 471 static int 472 setup_dma(struct sc_pcminfo *scp) 473 { 474 struct tcd_conf *tcd; 475 struct sc_info *sc; 476 477 sc = scp->sc; 478 479 tcd = malloc(sizeof(struct tcd_conf), M_DEVBUF, M_WAITOK | M_ZERO); 480 tcd->channel = sc->edma_chnum; 481 tcd->ih = sai_dma_intr; 482 tcd->ih_user = scp; 483 tcd->saddr = sc->buf_base_phys; 484 tcd->daddr = rman_get_start(sc->res[0]) + I2S_TDR0; 485 486 /* 487 * Bytes to transfer per each minor loop. 488 * Hardware FIFO buffer size is 32x32bits. 489 */ 490 tcd->nbytes = 64; 491 492 tcd->nmajor = 512; 493 tcd->smod = 17; /* dma_size range */ 494 tcd->dmod = 0; 495 tcd->esg = 0; 496 tcd->soff = 0x4; 497 tcd->doff = 0; 498 tcd->ssize = 0x2; 499 tcd->dsize = 0x2; 500 tcd->slast = 0; 501 tcd->dlast_sga = 0; 502 503 sc->tcd = tcd; 504 505 sc->edma_sc->dma_setup(sc->edma_sc, sc->tcd); 506 507 return (0); 508 } 509 510 static int 511 saichan_trigger(kobj_t obj, void *data, int go) 512 { 513 struct sc_chinfo *ch = data; 514 struct sc_pcminfo *scp = ch->parent; 515 struct sc_info *sc = scp->sc; 516 517 snd_mtxlock(sc->lock); 518 519 switch (go) { 520 case PCMTRIG_START: 521 #if 0 522 device_printf(scp->dev, "trigger start\n"); 523 #endif 524 ch->run = 1; 525 break; 526 527 case PCMTRIG_STOP: 528 case PCMTRIG_ABORT: 529 #if 0 530 device_printf(scp->dev, "trigger stop or abort\n"); 531 #endif 532 ch->run = 0; 533 break; 534 } 535 536 snd_mtxunlock(sc->lock); 537 538 return (0); 539 } 540 541 static uint32_t 542 saichan_getptr(kobj_t obj, void *data) 543 { 544 struct sc_pcminfo *scp; 545 struct sc_chinfo *ch; 546 struct sc_info *sc; 547 548 ch = data; 549 scp = ch->parent; 550 sc = scp->sc; 551 552 return (sc->pos); 553 } 554 555 static uint32_t sai_pfmt[] = { 556 /* 557 * eDMA doesn't allow 24-bit coping, 558 * so we use 32. 559 */ 560 SND_FORMAT(AFMT_S32_LE, 2, 0), 561 0 562 }; 563 564 static struct pcmchan_caps sai_pcaps = {44100, 192000, sai_pfmt, 0}; 565 566 static struct pcmchan_caps * 567 saichan_getcaps(kobj_t obj, void *data) 568 { 569 570 return (&sai_pcaps); 571 } 572 573 static kobj_method_t saichan_methods[] = { 574 KOBJMETHOD(channel_init, saichan_init), 575 KOBJMETHOD(channel_free, saichan_free), 576 KOBJMETHOD(channel_setformat, saichan_setformat), 577 KOBJMETHOD(channel_setspeed, saichan_setspeed), 578 KOBJMETHOD(channel_setblocksize, saichan_setblocksize), 579 KOBJMETHOD(channel_trigger, saichan_trigger), 580 KOBJMETHOD(channel_getptr, saichan_getptr), 581 KOBJMETHOD(channel_getcaps, saichan_getcaps), 582 KOBJMETHOD_END 583 }; 584 CHANNEL_DECLARE(saichan); 585 586 static int 587 sai_probe(device_t dev) 588 { 589 590 if (!ofw_bus_status_okay(dev)) 591 return (ENXIO); 592 593 if (!ofw_bus_is_compatible(dev, "fsl,mvf600-sai")) 594 return (ENXIO); 595 596 device_set_desc(dev, "Vybrid Family Synchronous Audio Interface"); 597 return (BUS_PROBE_DEFAULT); 598 } 599 600 static void 601 sai_intr(void *arg) 602 { 603 struct sc_pcminfo *scp; 604 struct sc_info *sc; 605 606 scp = arg; 607 sc = scp->sc; 608 609 device_printf(sc->dev, "Error I2S_TCSR == 0x%08x\n", 610 READ4(sc, I2S_TCSR)); 611 } 612 613 static void 614 setup_sai(struct sc_info *sc) 615 { 616 int reg; 617 618 /* 619 * TCR/RCR registers must not be altered when TCSR[TE] is set. 620 */ 621 622 reg = READ4(sc, I2S_TCSR); 623 reg &= ~(TCSR_BCE | TCSR_TE | TCSR_FRDE); 624 WRITE4(sc, I2S_TCSR, reg); 625 626 reg = READ4(sc, I2S_TCR3); 627 reg &= ~(TCR3_TCE); 628 WRITE4(sc, I2S_TCR3, reg); 629 630 reg = (64 << TCR1_TFW_S); 631 WRITE4(sc, I2S_TCR1, reg); 632 633 reg = READ4(sc, I2S_TCR2); 634 reg &= ~(TCR2_MSEL_M << TCR2_MSEL_S); 635 reg |= (1 << TCR2_MSEL_S); 636 reg |= (TCR2_BCP | TCR2_BCD); 637 WRITE4(sc, I2S_TCR2, reg); 638 639 sai_configure_clock(sc); 640 641 reg = READ4(sc, I2S_TCR3); 642 reg |= (TCR3_TCE); 643 WRITE4(sc, I2S_TCR3, reg); 644 645 /* Configure to 32-bit I2S mode */ 646 reg = READ4(sc, I2S_TCR4); 647 reg &= ~(TCR4_FRSZ_M << TCR4_FRSZ_S); 648 reg |= (1 << TCR4_FRSZ_S); /* 2 words per frame */ 649 reg &= ~(TCR4_SYWD_M << TCR4_SYWD_S); 650 reg |= (23 << TCR4_SYWD_S); 651 reg |= (TCR4_MF | TCR4_FSE | TCR4_FSP | TCR4_FSD); 652 WRITE4(sc, I2S_TCR4, reg); 653 654 reg = READ4(sc, I2S_TCR5); 655 reg &= ~(TCR5_W0W_M << TCR5_W0W_S); 656 reg |= (23 << TCR5_W0W_S); 657 reg &= ~(TCR5_WNW_M << TCR5_WNW_S); 658 reg |= (23 << TCR5_WNW_S); 659 reg &= ~(TCR5_FBT_M << TCR5_FBT_S); 660 reg |= (31 << TCR5_FBT_S); 661 WRITE4(sc, I2S_TCR5, reg); 662 663 /* Enable transmitter */ 664 reg = READ4(sc, I2S_TCSR); 665 reg |= (TCSR_BCE | TCSR_TE | TCSR_FRDE); 666 reg |= (1 << 10); /* FEIE */ 667 WRITE4(sc, I2S_TCSR, reg); 668 } 669 670 static void 671 sai_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 672 { 673 bus_addr_t *addr; 674 675 if (err) 676 return; 677 678 addr = (bus_addr_t*)arg; 679 *addr = segs[0].ds_addr; 680 } 681 682 static int 683 sai_attach(device_t dev) 684 { 685 char status[SND_STATUSLEN]; 686 struct sc_pcminfo *scp; 687 struct sc_info *sc; 688 int err; 689 690 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 691 sc->dev = dev; 692 sc->sr = &rate_map[0]; 693 sc->pos = 0; 694 695 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "sai softc"); 696 if (sc->lock == NULL) { 697 device_printf(dev, "Cant create mtx\n"); 698 return (ENXIO); 699 } 700 701 if (bus_alloc_resources(dev, sai_spec, sc->res)) { 702 device_printf(dev, "could not allocate resources\n"); 703 return (ENXIO); 704 } 705 706 /* Memory interface */ 707 sc->bst = rman_get_bustag(sc->res[0]); 708 sc->bsh = rman_get_bushandle(sc->res[0]); 709 710 /* eDMA */ 711 if (find_edma_controller(sc)) { 712 device_printf(dev, "could not find active eDMA\n"); 713 return (ENXIO); 714 } 715 716 /* Setup PCM */ 717 scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_NOWAIT | M_ZERO); 718 scp->sc = sc; 719 scp->dev = dev; 720 721 /* DMA */ 722 sc->dma_size = 131072; 723 724 /* 725 * Must use dma_size boundary as modulo feature required. 726 * Modulo feature allows setup circular buffer. 727 */ 728 729 err = bus_dma_tag_create( 730 bus_get_dma_tag(sc->dev), 731 4, sc->dma_size, /* alignment, boundary */ 732 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 733 BUS_SPACE_MAXADDR, /* highaddr */ 734 NULL, NULL, /* filter, filterarg */ 735 sc->dma_size, 1, /* maxsize, nsegments */ 736 sc->dma_size, 0, /* maxsegsize, flags */ 737 NULL, NULL, /* lockfunc, lockarg */ 738 &sc->dma_tag); 739 740 err = bus_dmamem_alloc(sc->dma_tag, (void **)&sc->buf_base, 741 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->dma_map); 742 if (err) { 743 device_printf(dev, "cannot allocate framebuffer\n"); 744 return (ENXIO); 745 } 746 747 err = bus_dmamap_load(sc->dma_tag, sc->dma_map, sc->buf_base, 748 sc->dma_size, sai_dmamap_cb, &sc->buf_base_phys, BUS_DMA_NOWAIT); 749 if (err) { 750 device_printf(dev, "cannot load DMA map\n"); 751 return (ENXIO); 752 } 753 754 bzero(sc->buf_base, sc->dma_size); 755 756 /* Setup interrupt handler */ 757 err = bus_setup_intr(dev, sc->res[1], INTR_MPSAFE | INTR_TYPE_AV, 758 NULL, sai_intr, scp, &sc->ih); 759 if (err) { 760 device_printf(dev, "Unable to alloc interrupt resource.\n"); 761 return (ENXIO); 762 } 763 764 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 765 766 err = pcm_register(dev, scp, 1, 0); 767 if (err) { 768 device_printf(dev, "Can't register pcm.\n"); 769 return (ENXIO); 770 } 771 772 scp->chnum = 0; 773 pcm_addchan(dev, PCMDIR_PLAY, &saichan_class, scp); 774 scp->chnum++; 775 776 snprintf(status, SND_STATUSLEN, "at simplebus"); 777 pcm_setstatus(dev, status); 778 779 mixer_init(dev, &saimixer_class, scp); 780 781 setup_dma(scp); 782 setup_sai(sc); 783 784 return (0); 785 } 786 787 static device_method_t sai_pcm_methods[] = { 788 DEVMETHOD(device_probe, sai_probe), 789 DEVMETHOD(device_attach, sai_attach), 790 { 0, 0 } 791 }; 792 793 static driver_t sai_pcm_driver = { 794 "pcm", 795 sai_pcm_methods, 796 PCM_SOFTC_SIZE, 797 }; 798 799 DRIVER_MODULE(sai, simplebus, sai_pcm_driver, 0, 0); 800 MODULE_DEPEND(sai, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 801 MODULE_VERSION(sai, 1); 802