1 /*- 2 * Copyright (c) 2016 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Allwinner Consumer IR controller 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/rman.h> 40 #include <sys/sysctl.h> 41 #include <machine/bus.h> 42 43 #include <dev/ofw/openfirm.h> 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 #include <dev/extres/clk/clk.h> 47 #include <dev/extres/hwreset/hwreset.h> 48 49 #include <dev/evdev/input.h> 50 #include <dev/evdev/evdev.h> 51 52 #define READ(_sc, _r) bus_read_4((_sc)->res[0], (_r)) 53 #define WRITE(_sc, _r, _v) bus_write_4((_sc)->res[0], (_r), (_v)) 54 55 /* IR Control */ 56 #define AW_IR_CTL 0x00 57 /* Global Enable */ 58 #define AW_IR_CTL_GEN (1 << 0) 59 /* RX enable */ 60 #define AW_IR_CTL_RXEN (1 << 1) 61 /* CIR mode enable */ 62 #define AW_IR_CTL_MD (1 << 4) | (1 << 5) 63 64 /* RX Config Reg */ 65 #define AW_IR_RXCTL 0x10 66 /* Pulse Polarity Invert flag */ 67 #define AW_IR_RXCTL_RPPI (1 << 2) 68 69 /* RX Data */ 70 #define AW_IR_RXFIFO 0x20 71 72 /* RX Interrupt Control */ 73 #define AW_IR_RXINT 0x2C 74 /* RX FIFO Overflow */ 75 #define AW_IR_RXINT_ROI_EN (1 << 0) 76 /* RX Packet End */ 77 #define AW_IR_RXINT_RPEI_EN (1 << 1) 78 /* RX FIFO Data Available */ 79 #define AW_IR_RXINT_RAI_EN (1 << 4) 80 /* RX FIFO available byte level */ 81 #define AW_IR_RXINT_RAL(val) ((val) << 8) 82 83 /* RX Interrupt Status Reg */ 84 #define AW_IR_RXSTA 0x30 85 /* RX FIFO Get Available Counter */ 86 #define AW_IR_RXSTA_COUNTER(val) (((val) >> 8) & (sc->fifo_size * 2 - 1)) 87 /* Clear all interrupt status */ 88 #define AW_IR_RXSTA_CLEARALL 0xff 89 90 /* IR Sample Configure Reg */ 91 #define AW_IR_CIR 0x34 92 /* Filter Threshold = 8 * 21.3 = ~128us < 200us */ 93 #define AW_IR_RXFILT_VAL (((8) & 0x3f) << 2) 94 /* Idle Threshold = (2 + 1) * 128 * 42.7 = ~16.4ms > 9ms */ 95 #define AW_IR_RXIDLE_VAL (((2) & 0xff) << 8) 96 97 /* Bit 15 - value (pulse/space) */ 98 #define VAL_MASK 0x80 99 /* Bits 0:14 - sample duration */ 100 #define PERIOD_MASK 0x7f 101 102 /* Clock rate for IR0 or IR1 clock in CIR mode */ 103 #define AW_IR_BASE_CLK 3000000 104 /* Frequency sample 3MHz/64 = 46875Hz (21.3us) */ 105 #define AW_IR_SAMPLE_64 (0 << 0) 106 /* Frequency sample 3MHz/128 = 23437.5Hz (42.7us) */ 107 #define AW_IR_SAMPLE_128 (1 << 0) 108 109 #define AW_IR_ERROR_CODE 0xffffffff 110 #define AW_IR_REPEAT_CODE 0x0 111 112 /* 80 * 42.7 = ~3.4ms, Lead1(4.5ms) > AW_IR_L1_MIN */ 113 #define AW_IR_L1_MIN 80 114 /* 40 * 42.7 = ~1.7ms, Lead0(4.5ms) Lead0R(2.25ms) > AW_IR_L0_MIN */ 115 #define AW_IR_L0_MIN 40 116 /* 26 * 42.7 = ~1109us ~= 561 * 2, Pulse < AW_IR_PMAX */ 117 #define AW_IR_PMAX 26 118 /* 26 * 42.7 = ~1109us ~= 561 * 2, D1 > AW_IR_DMID, D0 <= AW_IR_DMID */ 119 #define AW_IR_DMID 26 120 /* 53 * 42.7 = ~2263us ~= 561 * 4, D < AW_IR_DMAX */ 121 #define AW_IR_DMAX 53 122 123 /* Active Thresholds */ 124 #define AW_IR_ACTIVE_T ((0 & 0xff) << 16) 125 #define AW_IR_ACTIVE_T_C ((1 & 0xff) << 23) 126 127 /* Code masks */ 128 #define CODE_MASK 0x00ff00ff 129 #define INV_CODE_MASK 0xff00ff00 130 #define VALID_CODE_MASK 0x00ff0000 131 132 #define A10_IR 1 133 #define A13_IR 2 134 135 #define AW_IR_RAW_BUF_SIZE 128 136 137 struct aw_ir_softc { 138 device_t dev; 139 struct resource *res[2]; 140 void * intrhand; 141 int fifo_size; 142 int dcnt; /* Packet Count */ 143 unsigned char buf[AW_IR_RAW_BUF_SIZE]; 144 struct evdev_dev *sc_evdev; 145 }; 146 147 static struct resource_spec aw_ir_spec[] = { 148 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 149 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 150 { -1, 0 } 151 }; 152 153 static struct ofw_compat_data compat_data[] = { 154 { "allwinner,sun4i-a10-ir", A10_IR }, 155 { "allwinner,sun5i-a13-ir", A13_IR }, 156 { NULL, 0 } 157 }; 158 159 static void 160 aw_ir_buf_reset(struct aw_ir_softc *sc) 161 { 162 163 sc->dcnt = 0; 164 } 165 166 static void 167 aw_ir_buf_write(struct aw_ir_softc *sc, unsigned char data) 168 { 169 170 if (sc->dcnt < AW_IR_RAW_BUF_SIZE) 171 sc->buf[sc->dcnt++] = data; 172 else 173 if (bootverbose) 174 device_printf(sc->dev, "IR RX Buffer Full!\n"); 175 } 176 177 static int 178 aw_ir_buf_full(struct aw_ir_softc *sc) 179 { 180 181 return (sc->dcnt >= AW_IR_RAW_BUF_SIZE); 182 } 183 184 static unsigned char 185 aw_ir_read_data(struct aw_ir_softc *sc) 186 { 187 188 return (unsigned char)(READ(sc, AW_IR_RXFIFO) & 0xff); 189 } 190 191 static unsigned long 192 aw_ir_decode_packets(struct aw_ir_softc *sc) 193 { 194 unsigned long len, code; 195 unsigned char val, last; 196 unsigned int active_delay; 197 int i, bitcount; 198 199 if (bootverbose) 200 device_printf(sc->dev, "sc->dcnt = %d\n", sc->dcnt); 201 202 /* Find Lead 1 (bit separator) */ 203 active_delay = (AW_IR_ACTIVE_T + 1) * (AW_IR_ACTIVE_T_C ? 128 : 1); 204 len = 0; 205 len += (active_delay >> 1); 206 if (bootverbose) 207 device_printf(sc->dev, "Initial len: %ld\n", len); 208 for (i = 0; i < sc->dcnt; i++) { 209 val = sc->buf[i]; 210 if (val & VAL_MASK) 211 len += val & PERIOD_MASK; 212 else { 213 if (len > AW_IR_L1_MIN) 214 break; 215 len = 0; 216 } 217 } 218 if (bootverbose) 219 device_printf(sc->dev, "len = %ld\n", len); 220 if ((val & VAL_MASK) || (len <= AW_IR_L1_MIN)) { 221 if (bootverbose) 222 device_printf(sc->dev, "Bit separator error\n"); 223 goto error_code; 224 } 225 226 /* Find Lead 0 (bit length) */ 227 len = 0; 228 for (; i < sc->dcnt; i++) { 229 val = sc->buf[i]; 230 if (val & VAL_MASK) { 231 if(len > AW_IR_L0_MIN) 232 break; 233 len = 0; 234 } else 235 len += val & PERIOD_MASK; 236 } 237 if ((!(val & VAL_MASK)) || (len <= AW_IR_L0_MIN)) { 238 if (bootverbose) 239 device_printf(sc->dev, "Bit length error\n"); 240 goto error_code; 241 } 242 243 /* Start decoding */ 244 code = 0; 245 bitcount = 0; 246 last = 1; 247 len = 0; 248 for (; i < sc->dcnt; i++) { 249 val = sc->buf[i]; 250 if (last) { 251 if (val & VAL_MASK) 252 len += val & PERIOD_MASK; 253 else { 254 if (len > AW_IR_PMAX) { 255 if (bootverbose) 256 device_printf(sc->dev, 257 "Pulse error\n"); 258 goto error_code; 259 } 260 last = 0; 261 len = val & PERIOD_MASK; 262 } 263 } else { 264 if (val & VAL_MASK) { 265 if (len > AW_IR_DMAX) { 266 if (bootverbose) 267 device_printf(sc->dev, 268 "Distant error\n"); 269 goto error_code; 270 } else { 271 if (len > AW_IR_DMID) { 272 /* Decode */ 273 code |= 1 << bitcount; 274 } 275 bitcount++; 276 if (bitcount == 32) 277 break; /* Finish decoding */ 278 } 279 last = 1; 280 len = val & PERIOD_MASK; 281 } else 282 len += val & PERIOD_MASK; 283 } 284 } 285 return (code); 286 287 error_code: 288 289 return (AW_IR_ERROR_CODE); 290 } 291 292 static int 293 aw_ir_validate_code(unsigned long code) 294 { 295 unsigned long v1, v2; 296 297 /* Don't check address */ 298 v1 = code & CODE_MASK; 299 v2 = (code & INV_CODE_MASK) >> 8; 300 301 if (((v1 ^ v2) & VALID_CODE_MASK) == VALID_CODE_MASK) 302 return (0); /* valid */ 303 else 304 return (1); /* invalid */ 305 } 306 307 static void 308 aw_ir_intr(void *arg) 309 { 310 struct aw_ir_softc *sc; 311 uint32_t val; 312 int i, dcnt; 313 unsigned long ir_code; 314 int stat; 315 316 sc = (struct aw_ir_softc *)arg; 317 318 /* Read RX interrupt status */ 319 val = READ(sc, AW_IR_RXSTA); 320 321 /* Clean all pending interrupt statuses */ 322 WRITE(sc, AW_IR_RXSTA, val | AW_IR_RXSTA_CLEARALL); 323 324 /* When Rx FIFO Data available or Packet end */ 325 if (val & (AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RPEI_EN)) { 326 /* Get available message count in RX FIFO */ 327 dcnt = AW_IR_RXSTA_COUNTER(val); 328 /* Read FIFO */ 329 for (i = 0; i < dcnt; i++) { 330 if (aw_ir_buf_full(sc)) { 331 if (bootverbose) 332 device_printf(sc->dev, 333 "raw buffer full\n"); 334 break; 335 } else 336 aw_ir_buf_write(sc, aw_ir_read_data(sc)); 337 } 338 } 339 340 if (val & AW_IR_RXINT_RPEI_EN) { 341 /* RX Packet end */ 342 if (bootverbose) 343 device_printf(sc->dev, "RX Packet end\n"); 344 ir_code = aw_ir_decode_packets(sc); 345 stat = aw_ir_validate_code(ir_code); 346 if (stat == 0) { 347 evdev_push_event(sc->sc_evdev, 348 EV_MSC, MSC_SCAN, ir_code); 349 evdev_sync(sc->sc_evdev); 350 } 351 if (bootverbose) { 352 device_printf(sc->dev, "Final IR code: %lx\n", 353 ir_code); 354 device_printf(sc->dev, "IR code status: %d\n", 355 stat); 356 } 357 sc->dcnt = 0; 358 } 359 if (val & AW_IR_RXINT_ROI_EN) { 360 /* RX FIFO overflow */ 361 if (bootverbose) 362 device_printf(sc->dev, "RX FIFO overflow\n"); 363 /* Flush raw buffer */ 364 aw_ir_buf_reset(sc); 365 } 366 } 367 368 static int 369 aw_ir_probe(device_t dev) 370 { 371 372 if (!ofw_bus_status_okay(dev)) 373 return (ENXIO); 374 375 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 376 return (ENXIO); 377 378 device_set_desc(dev, "Allwinner CIR controller"); 379 return (BUS_PROBE_DEFAULT); 380 } 381 382 static int 383 aw_ir_attach(device_t dev) 384 { 385 struct aw_ir_softc *sc; 386 hwreset_t rst_apb; 387 clk_t clk_ir, clk_gate; 388 int err; 389 uint32_t val = 0; 390 391 clk_ir = clk_gate = NULL; 392 rst_apb = NULL; 393 394 sc = device_get_softc(dev); 395 sc->dev = dev; 396 397 if (bus_alloc_resources(dev, aw_ir_spec, sc->res) != 0) { 398 device_printf(dev, "could not allocate memory resource\n"); 399 return (ENXIO); 400 } 401 402 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 403 case A10_IR: 404 sc->fifo_size = 16; 405 break; 406 case A13_IR: 407 sc->fifo_size = 64; 408 break; 409 } 410 411 /* De-assert reset */ 412 if (hwreset_get_by_ofw_name(dev, 0, "apb", &rst_apb) == 0) { 413 err = hwreset_deassert(rst_apb); 414 if (err != 0) { 415 device_printf(dev, "cannot de-assert reset\n"); 416 goto error; 417 } 418 } 419 420 /* Reset buffer */ 421 aw_ir_buf_reset(sc); 422 423 /* Get clocks and enable them */ 424 err = clk_get_by_ofw_name(dev, 0, "apb", &clk_gate); 425 if (err != 0) { 426 device_printf(dev, "Cannot get gate clock\n"); 427 goto error; 428 } 429 err = clk_get_by_ofw_name(dev, 0, "ir", &clk_ir); 430 if (err != 0) { 431 device_printf(dev, "Cannot get IR clock\n"); 432 goto error; 433 } 434 /* Set clock rate */ 435 err = clk_set_freq(clk_ir, AW_IR_BASE_CLK, 0); 436 if (err != 0) { 437 device_printf(dev, "cannot set IR clock rate\n"); 438 goto error; 439 } 440 /* Enable clocks */ 441 err = clk_enable(clk_gate); 442 if (err != 0) { 443 device_printf(dev, "Cannot enable clk gate\n"); 444 goto error; 445 } 446 err = clk_enable(clk_ir); 447 if (err != 0) { 448 device_printf(dev, "Cannot enable IR clock\n"); 449 goto error; 450 } 451 452 if (bus_setup_intr(dev, sc->res[1], 453 INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_ir_intr, sc, 454 &sc->intrhand)) { 455 bus_release_resources(dev, aw_ir_spec, sc->res); 456 device_printf(dev, "cannot setup interrupt handler\n"); 457 return (ENXIO); 458 } 459 460 /* Enable CIR Mode */ 461 WRITE(sc, AW_IR_CTL, AW_IR_CTL_MD); 462 463 /* 464 * Set clock sample, filter, idle thresholds. 465 * Frequency sample = 3MHz/128 = 23437.5Hz (42.7us) 466 */ 467 val = AW_IR_SAMPLE_128; 468 val |= (AW_IR_RXFILT_VAL | AW_IR_RXIDLE_VAL); 469 val |= (AW_IR_ACTIVE_T | AW_IR_ACTIVE_T_C); 470 WRITE(sc, AW_IR_CIR, val); 471 472 /* Invert Input Signal */ 473 WRITE(sc, AW_IR_RXCTL, AW_IR_RXCTL_RPPI); 474 475 /* Clear All RX Interrupt Status */ 476 WRITE(sc, AW_IR_RXSTA, AW_IR_RXSTA_CLEARALL); 477 478 /* 479 * Enable RX interrupt in case of overflow, packet end 480 * and FIFO available. 481 * RX FIFO Threshold = FIFO size / 2 482 */ 483 WRITE(sc, AW_IR_RXINT, AW_IR_RXINT_ROI_EN | AW_IR_RXINT_RPEI_EN | 484 AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RAL((sc->fifo_size >> 1) - 1)); 485 486 /* Enable IR Module */ 487 val = READ(sc, AW_IR_CTL); 488 WRITE(sc, AW_IR_CTL, val | AW_IR_CTL_GEN | AW_IR_CTL_RXEN); 489 490 sc->sc_evdev = evdev_alloc(); 491 evdev_set_name(sc->sc_evdev, device_get_desc(sc->dev)); 492 evdev_set_phys(sc->sc_evdev, device_get_nameunit(sc->dev)); 493 evdev_set_id(sc->sc_evdev, BUS_HOST, 0, 0, 0); 494 evdev_support_event(sc->sc_evdev, EV_SYN); 495 evdev_support_event(sc->sc_evdev, EV_MSC); 496 evdev_support_msc(sc->sc_evdev, MSC_SCAN); 497 498 err = evdev_register(sc->sc_evdev); 499 if (err) { 500 device_printf(dev, 501 "failed to register evdev: error=%d\n", err); 502 goto error; 503 } 504 505 return (0); 506 error: 507 if (clk_gate != NULL) 508 clk_release(clk_gate); 509 if (clk_ir != NULL) 510 clk_release(clk_ir); 511 if (rst_apb != NULL) 512 hwreset_release(rst_apb); 513 evdev_free(sc->sc_evdev); 514 sc->sc_evdev = NULL; /* Avoid double free */ 515 516 bus_release_resources(dev, aw_ir_spec, sc->res); 517 return (ENXIO); 518 } 519 520 static device_method_t aw_ir_methods[] = { 521 DEVMETHOD(device_probe, aw_ir_probe), 522 DEVMETHOD(device_attach, aw_ir_attach), 523 524 DEVMETHOD_END 525 }; 526 527 static driver_t aw_ir_driver = { 528 "aw_ir", 529 aw_ir_methods, 530 sizeof(struct aw_ir_softc), 531 }; 532 static devclass_t aw_ir_devclass; 533 534 DRIVER_MODULE(aw_ir, simplebus, aw_ir_driver, aw_ir_devclass, 0, 0); 535 MODULE_DEPEND(aw_ir, evdev, 1, 1, 1); 536