1 /*-
2 * Copyright (c) 2019 Leandro Lupori
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 #include <openfirm.h>
27 #include <stand.h>
28
29 #include <sys/endian.h>
30
31 /* #define CAS_DEBUG */
32 #ifdef CAS_DEBUG
33 #define DPRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__)
34 #else
35 #define DPRINTF(fmt, ...) do { ; } while (0)
36 #endif
37
38 /* PVR */
39 #define PVR_CPU_P8E 0x004b0000
40 #define PVR_CPU_P8NVL 0x004c0000
41 #define PVR_CPU_P8 0x004d0000
42 #define PVR_CPU_P9 0x004e0000
43 #define PVR_CPU_P10 0x00800000
44 #define PVR_CPU_P11 0x00820000
45 #define PVR_CPU_MASK 0xffff0000
46
47 #define PVR_ISA_207 0x0f000004
48 #define PVR_ISA_300 0x0f000005
49 #define PVR_ISA_31 0x0f000006
50 #define PVR_ISA_MASK 0xffffffff
51
52 /* loader version of kernel's CPU_MAXSIZE */
53 #define MAX_CPUS ((uint32_t)256u)
54
55 /* Option Vectors' settings */
56
57 /* length of ignored OV */
58 #define OV_IGN_LEN 0
59
60 /* byte 1 (of any OV) */
61 #define OV_IGN 0x80
62
63 /* Option Vector 5 */
64
65 /* byte 2 */
66 #define OV5_LPAR 0x80
67 #define OV5_SPLPAR 0x40
68 #define OV5_DRMEM 0x20
69 #define OV5_LP 0x10
70 #define OV5_ALPHA_PART 0x08
71 #define OV5_DMA_DELAY 0x04
72 #define OV5_DONATE_CPU 0x02
73 #define OV5_MSI 0x01
74
75 /* 9-12: max cpus */
76 #define OV5_MAX_CPUS(n) ((MAX_CPUS >> (3*8 - (n)*8)) & 0xff)
77
78 /* 13-14: LoPAPR Level */
79 #define LOPAPR_LEVEL 0x0101 /* 1.1 */
80 #define OV5_LOPAPR_LEVEL(n) ((LOPAPR_LEVEL >> (8 - (n)*8)) & 0xff)
81
82 /* byte 17: Platform Facilities */
83 #define OV5_RNG 0x80
84 #define OV5_COMP_ENG 0x40
85 #define OV5_ENC_ENG 0x20
86
87 /* byte 21: Sub-Processors */
88 #define OV5_NO_SUBPROCS 0
89 #define OV5_SUBPROCS 1
90
91 /* byte 23: interrupt controller */
92 #define OV5_INTC_XICS 0
93
94 /* byte 24: MMU */
95 #define OV5_MMU_INDEX 24
96 #define OV5_MMU_HPT 0
97 #define OV5_MMU_RADIX 0x40
98 #define OV5_MMU_EITHER 0x80
99 #define OV5_MMU_DYNAMIC 0xc0
100
101 /* byte 25: HPT MMU Extensions */
102 #define OV5_HPT_EXT_INDEX 25
103 #define OV5_HPT_GTSE 0x40
104
105 /* byte 26: Radix MMU Extensions */
106 #define OV5_RADIX_EXT_INDEX 26
107 #define OV5_RADIX_GTSE 0x40
108
109
110 struct pvr {
111 uint32_t mask;
112 uint32_t val;
113 };
114
115 struct opt_vec_ignore {
116 char data[2];
117 } __packed;
118
119 struct opt_vec4 {
120 char data[3];
121 } __packed;
122
123 struct opt_vec5 {
124 char data[27];
125 } __packed;
126
127 static struct ibm_arch_vec {
128 struct pvr pvr_list[10];
129 uint8_t num_opts;
130 struct opt_vec_ignore vec1;
131 struct opt_vec_ignore vec2;
132 struct opt_vec_ignore vec3;
133 struct opt_vec4 vec4;
134 struct opt_vec5 vec5;
135 } __packed ibm_arch_vec = {
136 /* pvr_list */ {
137 { htobe32(PVR_CPU_MASK), htobe32(PVR_CPU_P8) },
138 { htobe32(PVR_CPU_MASK), htobe32(PVR_CPU_P8E) },
139 { htobe32(PVR_CPU_MASK), htobe32(PVR_CPU_P8NVL) },
140 { htobe32(PVR_CPU_MASK), htobe32(PVR_CPU_P9) },
141 { htobe32(PVR_CPU_MASK), htobe32(PVR_CPU_P10) },
142 { htobe32(PVR_CPU_MASK), htobe32(PVR_CPU_P11) },
143 { htobe32(PVR_ISA_MASK), htobe32(PVR_ISA_207) },
144 { htobe32(PVR_ISA_MASK), htobe32(PVR_ISA_300) },
145 { htobe32(PVR_ISA_MASK), htobe32(PVR_ISA_31) },
146 { 0, 0xffffffffu } /* terminator */
147 },
148 4, /* num_opts (4 actually means 5 option vectors) */
149 { OV_IGN_LEN, OV_IGN }, /* OV1 */
150 { OV_IGN_LEN, OV_IGN }, /* OV2 */
151 { OV_IGN_LEN, OV_IGN }, /* OV3 */
152 /* OV4 (can't be ignored) */ {
153 sizeof(struct opt_vec4) - 2, /* length (n-2) */
154 0,
155 10 /* Minimum VP entitled capacity percentage * 100
156 * (if absent assume 10%) */
157 },
158 /* OV5 */ {
159 sizeof(struct opt_vec5) - 2, /* length (n-2) */
160 0, /* don't ignore */
161 OV5_LPAR | OV5_SPLPAR | OV5_LP | OV5_MSI,
162 0,
163 0, /* Cooperative Memory Over-commitment */
164 0, /* Associativity Information Option */
165 0, /* Binary Option Controls */
166 0, /* Reserved */
167 0, /* Reserved */
168 OV5_MAX_CPUS(0),
169 OV5_MAX_CPUS(1), /* 10 */
170 OV5_MAX_CPUS(2),
171 OV5_MAX_CPUS(3),
172 OV5_LOPAPR_LEVEL(0),
173 OV5_LOPAPR_LEVEL(1),
174 0, /* Reserved */
175 0, /* Reserved */
176 0, /* Platform Facilities */
177 0, /* Reserved */
178 0, /* Reserved */
179 0, /* Reserved */ /* 20 */
180 OV5_NO_SUBPROCS,
181 0, /* DRMEM_V2 */
182 OV5_INTC_XICS,
183 OV5_MMU_HPT,
184 0,
185 0
186 }
187 };
188
189 int
ppc64_cas(void)190 ppc64_cas(void)
191 {
192 phandle_t pkg;
193 ihandle_t inst;
194 cell_t err = 0;
195 uint8_t buf[16], idx, val;
196 int i, len, rc, radix_mmu;
197 const char *var;
198 char *ov5;
199
200 pkg = OF_finddevice("/chosen");
201 if (pkg == -1) {
202 printf("cas: couldn't find /chosen\n");
203 return (-1);
204 }
205
206 len = OF_getprop(pkg, "ibm,arch-vec-5-platform-support", buf,
207 sizeof(buf));
208 if (len == -1)
209 /* CAS not supported */
210 return (0);
211
212 radix_mmu = 0;
213 ov5 = ibm_arch_vec.vec5.data;
214 for (i = 0; i < len; i += 2) {
215 idx = buf[i];
216 val = buf[i + 1];
217 DPRINTF("idx 0x%02x val 0x%02x\n", idx, val);
218
219 switch (idx) {
220 case OV5_MMU_INDEX:
221 /*
222 * Note that testing for OV5_MMU_RADIX/OV5_MMU_EITHER
223 * also covers OV5_MMU_DYNAMIC.
224 */
225 if ((val & OV5_MMU_RADIX) || (val & OV5_MMU_EITHER))
226 radix_mmu = 1;
227 break;
228
229 case OV5_RADIX_EXT_INDEX:
230 if (val & OV5_RADIX_GTSE)
231 ov5[idx] = OV5_RADIX_GTSE;
232 break;
233
234 case OV5_HPT_EXT_INDEX:
235 default:
236 break;
237 }
238 }
239
240 if (!radix_mmu)
241 /*
242 * If radix is not supported, set radix_mmu to 0 to avoid
243 * the kernel trying to use it and panic.
244 */
245 setenv("radix_mmu", "0", 1);
246 else if ((var = getenv("radix_mmu")) != NULL && var[0] == '0')
247 radix_mmu = 0;
248 else
249 ov5[OV5_MMU_INDEX] = OV5_MMU_RADIX;
250
251 inst = OF_open("/");
252 if (inst == -1) {
253 printf("cas: failed to open / node\n");
254 return (-1);
255 }
256
257 DPRINTF("MMU 0x%02x RADIX_EXT 0x%02x\n",
258 ov5[OV5_MMU_INDEX], ov5[OV5_RADIX_EXT_INDEX]);
259 rc = OF_call_method("ibm,client-architecture-support",
260 inst, 1, 1, &ibm_arch_vec, &err);
261 if (rc != 0 || err) {
262 printf("cas: CAS method returned an error: rc %d err %jd\n",
263 rc, (intmax_t)err);
264 rc = -1;
265 }
266
267 OF_close(inst);
268 printf("cas: selected %s MMU\n", radix_mmu ? "radix" : "hash");
269 return (rc);
270 }
271