xref: /freebsd/share/man/man4/sume.4 (revision ba3c1f5972d7b90feb6e6da47905ff2757e0fe57)
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27.\" $FreeBSD$
28.\"
29.Dd August 30, 2020
30.Dt SUME 4
31.Os
32.Sh NAME
33.Nm sume
34.Nd "NetFPGA SUME 4x10Gb Ethernet driver"
35.Sh SYNOPSIS
36To compile this driver into the kernel, place the following lines
37in your kernel configuration file:
38.Bd -ragged -offset indent
39.Cd "device sume"
40.Ed
41.Pp
42Alternatively, to load the driver as a module at boot time, place
43the following line in
44.Xr loader.conf 5 :
45.Bd -literal -offset indent
46if_sume_load="YES"
47.Ed
48.Sh DESCRIPTION
49The
50.Nm
51driver provides support for NetFPGA SUME Virtex-7 FPGA Development Board
52with the reference NIC bitstream loaded onto it.
53The HDL design for the reference NIC project uses the RIFFA based DMA
54engine to communicate with the host machine over PCIe.
55Every packet is transmitted to / from the board via a single DMA
56transaction, taking up to two or three interrupts per one transaction
57which yields low performance.
58.Pp
59There is no support for Jumbo frames as the hardware is capable of
60dealing only with frames with maximum size of 1514 bytes.
61The hardware does not support multicast filtering, provides no checksums,
62and offers no other offloading.
63.Sh SEE ALSO
64.Xr arp 4 ,
65.Xr netgraph 4 ,
66.Xr netintro 4 ,
67.Xr ng_ether 4 ,
68.Xr vlan 4 ,
69.Xr ifconfig 8
70.Sh AUTHORS
71The Linux
72.Nm
73driver was originally written by
74.An -nosplit
75.An Bjoern A. Zeeb .
76The
77.Fx version and this manual page were written by
78.An Denis Salopek
79as a GSoC project.
80More information about the project can be found here:
81.Pa https://wiki.freebsd.org/SummerOfCode2020Projects/NetFPGA_SUME_Driver
82.Sh BUGS
83The reference NIC hardware design provides no mechanism for quiescing
84inbound traffic from interfaces configured as DOWN.
85All packets from administratively disabled interfaces are transferred to
86main memory, leaving the driver with the task of dropping such packets,
87thus consuming PCI bandwidth, interrupts and CPU cycles in vain.
88.Pp
89Pre-built FPGA bitstream from the NetFPGA project may not work correctly.
90At higher RX packet rates, the newly incoming packets can overwrite the
91ones in an internal FIFO so the packets would arrive in main memory
92corrupted, until a physical reset of the board.
93.Pp
94Occasionally, the driver can get stuck in a non-IDLE TX state due to
95a missed interrupt.
96The driver includes a watchdog function which monitors for such a
97condition and resets the board automatically.
98For more details, visit the NetFPGA SUME project site.
99