1 .\" $OpenBSD: hifn.4,v 1.32 2002/09/26 07:55:40 miod Exp $ 2 .\" 3 .\" Copyright (c) 2000 Theo de Raadt 4 .\" All rights reserved. 5 .\" 6 .\" Redistribution and use in source and binary forms, with or without 7 .\" modification, are permitted provided that the following conditions 8 .\" are met: 9 .\" 1. Redistributions of source code must retain the above copyright 10 .\" notice, this list of conditions and the following disclaimer. 11 .\" 2. Redistributions in binary form must reproduce the above copyright 12 .\" notice, this list of conditions and the following disclaimer in the 13 .\" documentation and/or other materials provided with the distribution. 14 .\" 15 .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 .\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 .\" WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 .\" DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 .\" INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 .\" (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 .\" SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 .\" STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 .\" ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 .\" POSSIBILITY OF SUCH DAMAGE. 26 .\" 27 .Dd July 29, 2020 28 .Dt HIFN 4 29 .Os 30 .Sh NAME 31 .Nm hifn 32 .Nd Hifn 7751/7951/7811/7955/7956 crypto accelerator 33 .Sh SYNOPSIS 34 To compile this driver into the kernel, 35 place the following lines in your 36 kernel configuration file: 37 .Bd -ragged -offset indent 38 .Cd "device crypto" 39 .Cd "device cryptodev" 40 .Cd "device hifn" 41 .Ed 42 .Pp 43 Alternatively, to load the driver as a 44 module at boot time, place the following line in 45 .Xr loader.conf 5 : 46 .Bd -literal -offset indent 47 hifn_load="YES" 48 .Ed 49 .Sh DESCRIPTION 50 The 51 .Nm 52 driver supports various cards containing the Hifn 7751, 7951, 53 7811, 7955, and 7956 chipsets. 54 .Pp 55 The 56 .Nm 57 driver registers itself to accelerate 58 AES (7955 and 7956 only), 59 SHA1, and SHA1-HMAC operations for 60 .Xr ipsec 4 61 and 62 .Xr crypto 4 . 63 .Pp 64 The Hifn 65 .Tn 7951 , 66 .Tn 7811 , 67 .Tn 7955 , 68 and 69 .Tn 7956 70 will also supply data to the kernel 71 .Xr random 4 72 subsystem. 73 .Sh HARDWARE 74 The 75 .Nm 76 driver supports various cards containing the Hifn 7751, 7951, 77 7811, 7955, and 7956 78 chipsets, such as: 79 .Bl -tag -width namenamenamena -offset indent 80 .It Invertex AEON 81 No longer being made. 82 Came as 128KB SRAM model, or 2MB DRAM model. 83 .It Hifn 7751 84 Reference board with 512KB SRAM. 85 .It PowerCrypt 86 Comes with 512KB SRAM. 87 .It XL-Crypt 88 Only board based on 7811 (which is faster than 7751 and has 89 a random number generator). 90 .It NetSec 7751 91 Supports the most IPsec sessions, with 1MB SRAM. 92 .It Soekris Engineering vpn1201 and vpn1211 93 See 94 .Pa http://www.soekris.com/ . 95 Contains a 7951 and supports symmetric and random number operations. 96 .It Soekris Engineering vpn1401 and vpn1411 97 See 98 .Pa http://www.soekris.com/ . 99 Contains a 7955 and supports symmetric and random number operations. 100 .El 101 .Sh SEE ALSO 102 .Xr crypto 4 , 103 .Xr intro 4 , 104 .Xr ipsec 4 , 105 .Xr random 4 , 106 .Xr crypto 7 , 107 .Xr crypto 9 108 .Sh HISTORY 109 The 110 .Nm 111 device driver appeared in 112 .Ox 2.7 . 113 The 114 .Nm 115 device driver was imported to 116 .Fx 5.0 . 117 .Sh CAVEATS 118 The Hifn 9751 shares the same PCI ID. 119 This chip is basically a 7751, but with the cryptographic functions missing. 120 Instead, the 9751 is only capable of doing compression. 121 Since we do not currently attempt to use any of these chips to do 122 compression, the 9751-based cards are not useful. 123 .Pp 124 Support for the 7955 and 7956 is incomplete; the asymmetric crypto 125 facilities are to be added and the performance is suboptimal. 126 .Sh BUGS 127 The 7751 chip starts out at initialization by only supporting compression. 128 A proprietary algorithm, which has been reverse engineered, is required to 129 unlock the cryptographic functionality of the chip. 130 It is possible for vendors to make boards which have a lock ID not known 131 to the driver, but all vendors currently just use the obvious ID which is 132 13 bytes of 0. 133