1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _FENV_H_ 32 #define _FENV_H_ 33 34 #include <sys/_types.h> 35 36 #ifndef __fenv_static 37 #define __fenv_static static 38 #endif 39 40 typedef __uint32_t fenv_t; 41 typedef __uint32_t fexcept_t; 42 43 /* Exception flags */ 44 #define FE_INEXACT 0x02000000 45 #define FE_DIVBYZERO 0x04000000 46 #define FE_UNDERFLOW 0x08000000 47 #define FE_OVERFLOW 0x10000000 48 #define FE_INVALID 0x20000000 /* all types of invalid FP ops */ 49 50 /* 51 * The PowerPC architecture has extra invalid flags that indicate the 52 * specific type of invalid operation occurred. These flags may be 53 * tested, set, and cleared---but not masked---separately. All of 54 * these bits are cleared when FE_INVALID is cleared, but only 55 * FE_VXSOFT is set when FE_INVALID is explicitly set in software. 56 */ 57 #define FE_VXCVI 0x00000100 /* invalid integer convert */ 58 #define FE_VXSQRT 0x00000200 /* square root of a negative */ 59 #define FE_VXSOFT 0x00000400 /* software-requested exception */ 60 #define FE_VXVC 0x00080000 /* ordered comparison involving NaN */ 61 #define FE_VXIMZ 0x00100000 /* inf * 0 */ 62 #define FE_VXZDZ 0x00200000 /* 0 / 0 */ 63 #define FE_VXIDI 0x00400000 /* inf / inf */ 64 #define FE_VXISI 0x00800000 /* inf - inf */ 65 #define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */ 66 #define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \ 67 FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \ 68 FE_VXSNAN | FE_INVALID) 69 #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ 70 FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW) 71 72 /* Rounding modes */ 73 #define FE_TONEAREST 0x0000 74 #define FE_TOWARDZERO 0x0001 75 #define FE_UPWARD 0x0002 76 #define FE_DOWNWARD 0x0003 77 #define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ 78 FE_UPWARD | FE_TOWARDZERO) 79 80 __BEGIN_DECLS 81 82 /* Default floating-point environment */ 83 extern const fenv_t __fe_dfl_env; 84 #define FE_DFL_ENV (&__fe_dfl_env) 85 86 /* We need to be able to map status flag positions to mask flag positions */ 87 #define _FPUSW_SHIFT 22 88 #define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ 89 FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT) 90 91 #ifndef _SOFT_FLOAT 92 #ifdef __SPE__ 93 #define __mffs(__env) __asm __volatile("mfspr %0, 512" : "=r" (*(__env))) 94 #define __mtfsf(__env) __asm __volatile("mtspr 512,%0" : : "r" (__env)) 95 #else 96 #define __mffs(__env) __asm __volatile("mffs %0" : "=f" (*(__env))) 97 #define __mtfsf(__env) __asm __volatile("mtfsf 255,%0" : : "f" (__env)) 98 #endif 99 #else 100 #define __mffs(__env) 101 #define __mtfsf(__env) 102 #endif 103 104 union __fpscr { 105 double __d; 106 struct { 107 #if _BYTE_ORDER == _LITTLE_ENDIAN 108 fenv_t __reg; 109 __uint32_t __junk; 110 #else 111 __uint32_t __junk; 112 fenv_t __reg; 113 #endif 114 } __bits; 115 }; 116 117 __fenv_static inline int 118 feclearexcept(int __excepts) 119 { 120 union __fpscr __r; 121 122 if (__excepts & FE_INVALID) 123 __excepts |= FE_ALL_INVALID; 124 __mffs(&__r.__d); 125 __r.__bits.__reg &= ~__excepts; 126 __mtfsf(__r.__d); 127 return (0); 128 } 129 130 __fenv_static inline int 131 fegetexceptflag(fexcept_t *__flagp, int __excepts) 132 { 133 union __fpscr __r; 134 135 __mffs(&__r.__d); 136 *__flagp = __r.__bits.__reg & __excepts; 137 return (0); 138 } 139 140 __fenv_static inline int 141 fesetexceptflag(const fexcept_t *__flagp, int __excepts) 142 { 143 union __fpscr __r; 144 145 if (__excepts & FE_INVALID) 146 __excepts |= FE_ALL_EXCEPT; 147 __mffs(&__r.__d); 148 __r.__bits.__reg &= ~__excepts; 149 __r.__bits.__reg |= *__flagp & __excepts; 150 __mtfsf(__r.__d); 151 return (0); 152 } 153 154 __fenv_static inline int 155 feraiseexcept(int __excepts) 156 { 157 union __fpscr __r; 158 159 if (__excepts & FE_INVALID) 160 __excepts |= FE_VXSOFT; 161 __mffs(&__r.__d); 162 __r.__bits.__reg |= __excepts; 163 __mtfsf(__r.__d); 164 return (0); 165 } 166 167 __fenv_static inline int 168 fetestexcept(int __excepts) 169 { 170 union __fpscr __r; 171 172 __mffs(&__r.__d); 173 return (__r.__bits.__reg & __excepts); 174 } 175 176 __fenv_static inline int 177 fegetround(void) 178 { 179 union __fpscr __r; 180 181 __mffs(&__r.__d); 182 return (__r.__bits.__reg & _ROUND_MASK); 183 } 184 185 __fenv_static inline int 186 fesetround(int __round) 187 { 188 union __fpscr __r; 189 190 if (__round & ~_ROUND_MASK) 191 return (-1); 192 __mffs(&__r.__d); 193 __r.__bits.__reg &= ~_ROUND_MASK; 194 __r.__bits.__reg |= __round; 195 __mtfsf(__r.__d); 196 return (0); 197 } 198 199 __fenv_static inline int 200 fegetenv(fenv_t *__envp) 201 { 202 union __fpscr __r; 203 204 __mffs(&__r.__d); 205 *__envp = __r.__bits.__reg; 206 return (0); 207 } 208 209 __fenv_static inline int 210 feholdexcept(fenv_t *__envp) 211 { 212 union __fpscr __r; 213 214 __mffs(&__r.__d); 215 *__envp = __r.__d; 216 __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK); 217 __mtfsf(__r.__d); 218 return (0); 219 } 220 221 __fenv_static inline int 222 fesetenv(const fenv_t *__envp) 223 { 224 union __fpscr __r; 225 226 __r.__bits.__reg = *__envp; 227 __mtfsf(__r.__d); 228 return (0); 229 } 230 231 __fenv_static inline int 232 feupdateenv(const fenv_t *__envp) 233 { 234 union __fpscr __r; 235 236 __mffs(&__r.__d); 237 __r.__bits.__reg &= FE_ALL_EXCEPT; 238 __r.__bits.__reg |= *__envp; 239 __mtfsf(__r.__d); 240 return (0); 241 } 242 243 #if __BSD_VISIBLE 244 245 /* We currently provide no external definitions of the functions below. */ 246 247 static inline int 248 feenableexcept(int __mask) 249 { 250 union __fpscr __r; 251 fenv_t __oldmask; 252 253 __mffs(&__r.__d); 254 __oldmask = __r.__bits.__reg; 255 __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT; 256 __mtfsf(__r.__d); 257 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 258 } 259 260 static inline int 261 fedisableexcept(int __mask) 262 { 263 union __fpscr __r; 264 fenv_t __oldmask; 265 266 __mffs(&__r.__d); 267 __oldmask = __r.__bits.__reg; 268 __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT); 269 __mtfsf(__r.__d); 270 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 271 } 272 273 static inline int 274 fegetexcept(void) 275 { 276 union __fpscr __r; 277 278 __mffs(&__r.__d); 279 return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT); 280 } 281 282 #endif /* __BSD_VISIBLE */ 283 284 __END_DECLS 285 286 #endif /* !_FENV_H_ */ 287