xref: /freebsd/lib/msun/powerpc/fenv.h (revision 5956d97f4b3204318ceb6aa9c77bd0bc6ea87a41)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  * $FreeBSD$
29  */
30 
31 #ifndef	_FENV_H_
32 #define	_FENV_H_
33 
34 #include <sys/_types.h>
35 #include <machine/endian.h>
36 
37 #ifndef	__fenv_static
38 #define	__fenv_static	static
39 #endif
40 
41 typedef	__uint32_t	fenv_t;
42 typedef	__uint32_t	fexcept_t;
43 
44 /* Exception flags */
45 #ifdef __SPE__
46 #define FE_OVERFLOW	0x00000100
47 #define FE_UNDERFLOW	0x00000200
48 #define FE_DIVBYZERO	0x00000400
49 #define FE_INVALID	0x00000800
50 #define FE_INEXACT	0x00001000
51 
52 #define	FE_ALL_INVALID	FE_INVALID
53 
54 #define	_FPUSW_SHIFT	6
55 #else
56 #define	FE_INEXACT	0x02000000
57 #define	FE_DIVBYZERO	0x04000000
58 #define	FE_UNDERFLOW	0x08000000
59 #define	FE_OVERFLOW	0x10000000
60 #define	FE_INVALID	0x20000000	/* all types of invalid FP ops */
61 
62 /*
63  * The PowerPC architecture has extra invalid flags that indicate the
64  * specific type of invalid operation occurred.  These flags may be
65  * tested, set, and cleared---but not masked---separately.  All of
66  * these bits are cleared when FE_INVALID is cleared, but only
67  * FE_VXSOFT is set when FE_INVALID is explicitly set in software.
68  */
69 #define	FE_VXCVI	0x00000100	/* invalid integer convert */
70 #define	FE_VXSQRT	0x00000200	/* square root of a negative */
71 #define	FE_VXSOFT	0x00000400	/* software-requested exception */
72 #define	FE_VXVC		0x00080000	/* ordered comparison involving NaN */
73 #define	FE_VXIMZ	0x00100000	/* inf * 0 */
74 #define	FE_VXZDZ	0x00200000	/* 0 / 0 */
75 #define	FE_VXIDI	0x00400000	/* inf / inf */
76 #define	FE_VXISI	0x00800000	/* inf - inf */
77 #define	FE_VXSNAN	0x01000000	/* operation on a signalling NaN */
78 #define	FE_ALL_INVALID	(FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \
79 			 FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \
80 			 FE_VXSNAN | FE_INVALID)
81 
82 #define	_FPUSW_SHIFT	22
83 #endif
84 #define	FE_ALL_EXCEPT	(FE_DIVBYZERO | FE_INEXACT | \
85 			 FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
86 
87 /* Rounding modes */
88 #define	FE_TONEAREST	0x0000
89 #define	FE_TOWARDZERO	0x0001
90 #define	FE_UPWARD	0x0002
91 #define	FE_DOWNWARD	0x0003
92 #define	_ROUND_MASK	(FE_TONEAREST | FE_DOWNWARD | \
93 			 FE_UPWARD | FE_TOWARDZERO)
94 
95 __BEGIN_DECLS
96 
97 /* Default floating-point environment */
98 extern const fenv_t	__fe_dfl_env;
99 #define	FE_DFL_ENV	(&__fe_dfl_env)
100 
101 /* We need to be able to map status flag positions to mask flag positions */
102 #define	_ENABLE_MASK	((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \
103 			 FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT)
104 
105 #ifndef _SOFT_FLOAT
106 #ifdef __SPE__
107 #define	__mffs(__env) \
108 	__asm __volatile("mfspr %0, 512" : "=r" ((__env)->__bits.__reg))
109 #define	__mtfsf(__env) \
110 	__asm __volatile("mtspr 512,%0;isync" :: "r" ((__env).__bits.__reg))
111 #else
112 #define	__mffs(__env) \
113 	__asm __volatile("mffs %0" : "=f" ((__env)->__d))
114 #define	__mtfsf(__env) \
115 	__asm __volatile("mtfsf 255,%0" :: "f" ((__env).__d))
116 #endif
117 #else
118 #define	__mffs(__env)
119 #define	__mtfsf(__env)
120 #endif
121 
122 union __fpscr {
123 	double __d;
124 	struct {
125 #if _BYTE_ORDER == _LITTLE_ENDIAN
126 		fenv_t __reg;
127 		__uint32_t __junk;
128 #else
129 		__uint32_t __junk;
130 		fenv_t __reg;
131 #endif
132 	} __bits;
133 };
134 
135 __fenv_static inline int
136 feclearexcept(int __excepts)
137 {
138 	union __fpscr __r;
139 
140 	if (__excepts & FE_INVALID)
141 		__excepts |= FE_ALL_INVALID;
142 	__mffs(&__r);
143 	__r.__bits.__reg &= ~__excepts;
144 	__mtfsf(__r);
145 	return (0);
146 }
147 
148 __fenv_static inline int
149 fegetexceptflag(fexcept_t *__flagp, int __excepts)
150 {
151 	union __fpscr __r;
152 
153 	__mffs(&__r);
154 	*__flagp = __r.__bits.__reg & __excepts;
155 	return (0);
156 }
157 
158 __fenv_static inline int
159 fesetexceptflag(const fexcept_t *__flagp, int __excepts)
160 {
161 	union __fpscr __r;
162 
163 	if (__excepts & FE_INVALID)
164 		__excepts |= FE_ALL_INVALID;
165 	__mffs(&__r);
166 	__r.__bits.__reg &= ~__excepts;
167 	__r.__bits.__reg |= *__flagp & __excepts;
168 	__mtfsf(__r);
169 	return (0);
170 }
171 
172 #ifdef __SPE__
173 extern int	feraiseexcept(int __excepts);
174 #else
175 __fenv_static inline int
176 feraiseexcept(int __excepts)
177 {
178 	union __fpscr __r;
179 
180 	if (__excepts & FE_INVALID)
181 		__excepts |= FE_VXSOFT;
182 	__mffs(&__r);
183 	__r.__bits.__reg |= __excepts;
184 	__mtfsf(__r);
185 	return (0);
186 }
187 #endif
188 
189 __fenv_static inline int
190 fetestexcept(int __excepts)
191 {
192 	union __fpscr __r;
193 
194 	__mffs(&__r);
195 	return (__r.__bits.__reg & __excepts);
196 }
197 
198 __fenv_static inline int
199 fegetround(void)
200 {
201 	union __fpscr __r;
202 
203 	__mffs(&__r);
204 	return (__r.__bits.__reg & _ROUND_MASK);
205 }
206 
207 __fenv_static inline int
208 fesetround(int __round)
209 {
210 	union __fpscr __r;
211 
212 	if (__round & ~_ROUND_MASK)
213 		return (-1);
214 	__mffs(&__r);
215 	__r.__bits.__reg &= ~_ROUND_MASK;
216 	__r.__bits.__reg |= __round;
217 	__mtfsf(__r);
218 	return (0);
219 }
220 
221 __fenv_static inline int
222 fegetenv(fenv_t *__envp)
223 {
224 	union __fpscr __r;
225 
226 	__mffs(&__r);
227 	*__envp = __r.__bits.__reg;
228 	return (0);
229 }
230 
231 __fenv_static inline int
232 feholdexcept(fenv_t *__envp)
233 {
234 	union __fpscr __r;
235 
236 	__mffs(&__r);
237 	*__envp = __r.__bits.__reg;
238 	__r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
239 	__mtfsf(__r);
240 	return (0);
241 }
242 
243 __fenv_static inline int
244 fesetenv(const fenv_t *__envp)
245 {
246 	union __fpscr __r;
247 
248 	__r.__bits.__reg = *__envp;
249 	__mtfsf(__r);
250 	return (0);
251 }
252 
253 __fenv_static inline int
254 feupdateenv(const fenv_t *__envp)
255 {
256 	union __fpscr __r;
257 
258 	__mffs(&__r);
259 	__r.__bits.__reg &= FE_ALL_EXCEPT;
260 	__r.__bits.__reg |= *__envp;
261 	__mtfsf(__r);
262 	return (0);
263 }
264 
265 #if __BSD_VISIBLE
266 
267 __fenv_static inline int
268 feenableexcept(int __mask)
269 {
270 	union __fpscr __r;
271 	fenv_t __oldmask;
272 
273 	__mffs(&__r);
274 	__oldmask = __r.__bits.__reg;
275 	__r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT;
276 	__mtfsf(__r);
277 	return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
278 }
279 
280 __fenv_static inline int
281 fedisableexcept(int __mask)
282 {
283 	union __fpscr __r;
284 	fenv_t __oldmask;
285 
286 	__mffs(&__r);
287 	__oldmask = __r.__bits.__reg;
288 	__r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT);
289 	__mtfsf(__r);
290 	return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
291 }
292 
293 /* We currently provide no external definition of fegetexcept(). */
294 static inline int
295 fegetexcept(void)
296 {
297 	union __fpscr __r;
298 
299 	__mffs(&__r);
300 	return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT);
301 }
302 
303 #endif /* __BSD_VISIBLE */
304 
305 __END_DECLS
306 
307 #endif	/* !_FENV_H_ */
308