1=pod 2 3=head1 NAME 4 5OPENSSL_armcap - the Arm processor capabilities vector 6 7=head1 SYNOPSIS 8 9 env OPENSSL_armcap=... <application> 10 11=head1 DESCRIPTION 12 13libcrypto supports a range of Arm instruction set extensions. These 14extensions are represented by bits in the Arm processor capabilities vector. 15When libcrypto initializes, it stores the results returned by Arm CPU 16capabilities detection logic in the Arm processor capabilities vector. The 17CPU capabilities detection methods are OS-dependent, using a combination of 18information gathered by the kernel during boot, and probe functions that attempt 19to execute instructions and trap illegal instruction signals with a signal 20handler. 21 22To override the set of extensions available to an application, set the 23B<OPENSSL_armcap> environment variable before starting the application. The 24environment variable is assigned a numerical value that denotes the bits in 25the Arm processor capabilities vector. The arm_arch.h header file defines 26the possible values, which are explained in detail below. 27 28Multiple extensions are enabled by logically OR-ing the values that represent 29the desired extensions. 30 31B<Notes>: Attempting to executing an instruction from an extension that the 32target CPU does not support will result in an illegal instruction exception 33(SIGILL). 34 35Please note that not all possible values in the Arm processor capabilities 36vector are actual processor capabilities. Some values represent OpenSSL 37performance preferences for some implementations which only make sense on 38specific CPUs. 39 40The following extensions are defined: 41 42=over 4 43 44=item 0x0001 45 46Name: B<ARMV7_NEON> 47 48Meaning: Indicates support for the Armv7 Neon SIMD extensions on the processor. 49 50Effect: Enables various Armv7 Neon SIMD implementations. 51 52=item 0x00002 53 54Name: B<ARMV7_TICK> 55 56Meaning: Indicates support for the Armv7 system timer on the processor. 57 58Effect: This is used as a seed for some random number generators. 59 60=item 0x00004 61 62Name: B<ARMV8_AES> 63 64Meaning: Indicates support for the Armv8.0 AES hardware-acceleration extensions 65on the processor. 66 67Effect: Enables various Armv8.0 AES hardware-accelerated implementations. 68 69=item 0x00008 70 71Name: B<ARMV8_SHA1> 72 73Meaning: Indicates support for the Armv8.0 SHA1 hardware-acceleration extensions 74on the processor. 75 76Effect: Enables various Armv8.0 SHA1 hardware-accelerated implementations. 77 78=item 0x00010 79 80Name: B<ARMV8_SHA256> 81 82Meaning: Indicates support for the Armv8.0 SHA256 hardware-acceleration 83extensions on the processor. 84 85Effect: Enables various Armv8.0 SHA256 hardware-accelerated implementations. 86 87=item 0x00020 88 89Name: B<ARMV8_PMULL> 90 91Meaning: Indicates support for the Armv8.0 polynomial multiplication 92hardware-acceleration extensions on the processor. 93 94Effect: Used to hardware-accelerate polynomial multiplication, for example in 95AES-GCM. 96 97=item 0x00040 98 99Name: B<ARMV8_SHA512> 100 101Meaning: Indicates support for the Armv8.2 SHA512 hardware-acceleration 102extensions on the processor. 103 104Effect: Enables Armv8.2 SHA512 hardware-accelerated implementations. 105 106=item 0x00080 107 108Name: B<ARMV8_CPUID> 109 110Meaning: Indicates support for the Armv8.0 hardware identification extensions on 111the processor. 112 113Effect: Allows implementations to change their behaviour, dependant on the 114processor platform in order to achieve better performance. 115 116=item 0x00100 117 118Name: B<ARMV8_RNG> 119 120Meaning: Indicates support for the Armv8.5 hardware random number generation 121extensions on the processor. 122 123Effect: Enables hardware random number generation on supported AArch64 124processors. 125 126=item 0x00200 127 128Name: B<ARMV8_SM3> 129 130Meaning: Indicates support for the Armv8.2 SM3 hardware-acceleration extensions 131on the processor. 132 133Effect: Enables Armv8.2 SM3 hardware-accelerated implementations. 134 135=item 0x00400 136 137Name: B<ARMV8_SM4> 138 139Meaning: Indicates support for the Armv8.2 SM4 hardware-acceleration extensions 140on the processor. 141 142Effect: Enables Armv8.2 SM4 hardware-accelerated implementations. 143 144=item 0x00800 145 146Name: B<ARMV8_SHA3> 147 148Meaning: Indicates support for the Armv8.2 SHA3 hardware-acceleration extensions 149on the processor. 150 151Effect: Enables SHA3 hardware-accelerated implementations (see also 152ARMV8_HAVE_SHA3_AND_WORTH_USING). 153 154=item 0x01000 155 156Name: B<ARMV8_UNROLL8_EOR3> 157 158Meaning: Indicates support for the Arm EOR3 instruction, which is a part of the 159Armv8.2 SHA3 extensions, and enables 8x Loop unrolling in the AES-CTR 160implementation. 161 162Effect: Enables the 8x loop unrolling utilising EOR3 implementation of AES-CTR 163on platforms that support the SHA3 extension and have enough vector bandwidth. 164 165=item 0x02000 166 167Name: B<ARMV8_SVE> 168 169Meaning: Indicates support for the Armv8.2 SVE hardware extension on the 170processor. 171 172Effect: Enables various Armv8.2 SVE implementations. 173 174=item 0x04000 175 176Name: B<ARMV9_SVE2> 177 178Meaning: Indicates support for the Armv9.0 SVE2 hardware extension on the 179processor. 180 181Effect: Enables various Armv9.0 SVE2 implementations. 182 183=item 0x08000 184 185Name: B<ARMV8_HAVE_SHA3_AND_WORTH_USING> 186 187Meaning: Indicates support for the Armv8.2 SHA3 hardware-acceleration extensions 188on the processor, and that the hardware bandwidth is sufficient for it to be 189worth using. 190 191Effect: On certain Apple platforms, although the SHA3 extension is supported, it 192is actually slower than other implementations. This flag disables the 193hardware-accelerated SHA3 implementations on these platforms. 194 195=item 0x10000 196 197Name: B<ARMV8_UNROLL12_EOR3> 198 199Meaning: Indicates support for the Arm EOR3 instruction, which is a part of the 200Armv8.2 SHA3 extensions, and enables 12x loop unrolling in the AES-CTR 201implementation. 202 203Effect: Enables the 12x loop unrolling utilising EOR3 implementation of AES-CTR 204on platforms that support the extension and have enough vector bandwidth. 205 206=item 0x20000 207 208Name: B<ARMV9_SVE2_POLY1305> 209 210Meaning: Indicates support for the Armv9.0 SVE2 hardware extension, and enables 211its use in the Poly1305 implementation. 212 213Effect: Enables the Armv9.0 SVE2 Poly1305 implementation if SVE2 is enabled, the 214vector length is greater than 128 bits, and the vector length is a power of 2. 215 216=back 217 218=head1 RETURN VALUES 219 220Not available. 221 222=head1 EXAMPLES 223 224Check currently detected capabilities: 225 226 $ openssl info -cpusettings 227 OPENSSL_armcap=0x987d 228 229The detected capabilities in the above example indicate that ARMV7_NEON, 230ARMV8_AES, ARMV8_SHA1, ARMV8_SHA256, ARMV8_PMULL, ARMV8_SHA512, ARMV8_SHA3, 231ARMV8_UNROLL8_EOR3, and ARMV8_HAVE_SHA3_AND_WORTH_USING are enabled. 232 233Disable all instruction set extensions: 234 235 export OPENSSL_armcap=0x00 236 237=head1 COPYRIGHT 238 239Copyright 2026 The OpenSSL Project Authors. All Rights Reserved. 240 241Licensed under the Apache License 2.0 (the "License"). You may not use 242this file except in compliance with the License. You can obtain a copy 243in the file LICENSE in the source distribution or at 244L<https://www.openssl.org/source/license.html>. 245 246=cut 247