1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2015 - 2022 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 /*$FreeBSD$*/ 35 36 #ifndef IRDMA_DEFS_H 37 #define IRDMA_DEFS_H 38 39 #define IRDMA_BYTE_0 0 40 #define IRDMA_BYTE_8 8 41 #define IRDMA_BYTE_16 16 42 #define IRDMA_BYTE_24 24 43 #define IRDMA_BYTE_32 32 44 #define IRDMA_BYTE_40 40 45 #define IRDMA_BYTE_48 48 46 #define IRDMA_BYTE_56 56 47 #define IRDMA_BYTE_64 64 48 #define IRDMA_BYTE_72 72 49 #define IRDMA_BYTE_80 80 50 #define IRDMA_BYTE_88 88 51 #define IRDMA_BYTE_96 96 52 #define IRDMA_BYTE_104 104 53 #define IRDMA_BYTE_112 112 54 #define IRDMA_BYTE_120 120 55 #define IRDMA_BYTE_128 128 56 #define IRDMA_BYTE_136 136 57 #define IRDMA_BYTE_144 144 58 #define IRDMA_BYTE_152 152 59 #define IRDMA_BYTE_160 160 60 #define IRDMA_BYTE_168 168 61 #define IRDMA_BYTE_176 176 62 #define IRDMA_BYTE_184 184 63 #define IRDMA_BYTE_192 192 64 #define IRDMA_BYTE_200 200 65 #define IRDMA_BYTE_208 208 66 #define IRDMA_BYTE_216 216 67 68 #define IRDMA_QP_TYPE_IWARP 1 69 #define IRDMA_QP_TYPE_UDA 2 70 #define IRDMA_QP_TYPE_ROCE_RC 3 71 #define IRDMA_QP_TYPE_ROCE_UD 4 72 73 #define IRDMA_HW_PAGE_SIZE 4096 74 #define IRDMA_HW_PAGE_SHIFT 12 75 #define IRDMA_CQE_QTYPE_RQ 0 76 #define IRDMA_CQE_QTYPE_SQ 1 77 78 #define IRDMA_QP_WQE_MIN_SIZE 32 79 #define IRDMA_QP_WQE_MAX_SIZE 256 80 #define IRDMA_QP_WQE_MIN_QUANTA 1 81 #define IRDMA_MAX_RQ_WQE_SHIFT_GEN1 2 82 #define IRDMA_MAX_RQ_WQE_SHIFT_GEN2 3 83 84 #define IRDMA_SQ_RSVD 258 85 #define IRDMA_RQ_RSVD 1 86 87 #define IRDMA_FEATURE_RTS_AE BIT_ULL(0) 88 #define IRDMA_FEATURE_CQ_RESIZE BIT_ULL(1) 89 #define IRDMA_FEATURE_RELAX_RQ_ORDER BIT_ULL(2) 90 #define IRDMA_FEATURE_64_BYTE_CQE BIT_ULL(5) 91 92 #define IRDMAQP_OP_RDMA_WRITE 0x00 93 #define IRDMAQP_OP_RDMA_READ 0x01 94 #define IRDMAQP_OP_RDMA_SEND 0x03 95 #define IRDMAQP_OP_RDMA_SEND_INV 0x04 96 #define IRDMAQP_OP_RDMA_SEND_SOL_EVENT 0x05 97 #define IRDMAQP_OP_RDMA_SEND_SOL_EVENT_INV 0x06 98 #define IRDMAQP_OP_BIND_MW 0x08 99 #define IRDMAQP_OP_FAST_REGISTER 0x09 100 #define IRDMAQP_OP_LOCAL_INVALIDATE 0x0a 101 #define IRDMAQP_OP_RDMA_READ_LOC_INV 0x0b 102 #define IRDMAQP_OP_NOP 0x0c 103 104 #ifndef LS_64_1 105 #define LS_64_1(val, bits) ((u64)(uintptr_t)(val) << (bits)) 106 #define RS_64_1(val, bits) ((u64)(uintptr_t)(val) >> (bits)) 107 #define LS_32_1(val, bits) ((u32)((val) << (bits))) 108 #define RS_32_1(val, bits) ((u32)((val) >> (bits))) 109 #endif 110 #ifndef GENMASK_ULL 111 #define GENMASK_ULL(high, low) ((0xFFFFFFFFFFFFFFFFULL >> (64ULL - ((high) - (low) + 1ULL))) << (low)) 112 #endif /* GENMASK_ULL */ 113 #ifndef GENMASK 114 #define GENMASK(high, low) ((0xFFFFFFFFUL >> (32UL - ((high) - (low) + 1UL))) << (low)) 115 #endif /* GENMASK */ 116 #ifndef FIELD_PREP 117 #define FIELD_PREP(mask, val) (((u64)(val) << mask##_S) & (mask)) 118 #define FIELD_GET(mask, val) (((val) & mask) >> mask##_S) 119 #endif /* FIELD_PREP */ 120 121 #define IRDMA_CQPHC_QPCTX_S 0 122 #define IRDMA_CQPHC_QPCTX GENMASK_ULL(63, 0) 123 #define IRDMA_QP_DBSA_HW_SQ_TAIL_S 0 124 #define IRDMA_QP_DBSA_HW_SQ_TAIL GENMASK_ULL(14, 0) 125 #define IRDMA_CQ_DBSA_CQEIDX_S 0 126 #define IRDMA_CQ_DBSA_CQEIDX GENMASK_ULL(19, 0) 127 #define IRDMA_CQ_DBSA_SW_CQ_SELECT_S 0 128 #define IRDMA_CQ_DBSA_SW_CQ_SELECT GENMASK_ULL(13, 0) 129 #define IRDMA_CQ_DBSA_ARM_NEXT_S 14 130 #define IRDMA_CQ_DBSA_ARM_NEXT BIT_ULL(14) 131 #define IRDMA_CQ_DBSA_ARM_NEXT_SE_S 15 132 #define IRDMA_CQ_DBSA_ARM_NEXT_SE BIT_ULL(15) 133 #define IRDMA_CQ_DBSA_ARM_SEQ_NUM_S 16 134 #define IRDMA_CQ_DBSA_ARM_SEQ_NUM GENMASK_ULL(17, 16) 135 136 /* CQP and iWARP Completion Queue */ 137 #define IRDMA_CQ_QPCTX_S IRDMA_CQPHC_QPCTX_S 138 #define IRDMA_CQ_QPCTX IRDMA_CQPHC_QPCTX 139 140 #define IRDMA_CQ_MINERR_S 0 141 #define IRDMA_CQ_MINERR GENMASK_ULL(15, 0) 142 #define IRDMA_CQ_MAJERR_S 16 143 #define IRDMA_CQ_MAJERR GENMASK_ULL(31, 16) 144 #define IRDMA_CQ_WQEIDX_S 32 145 #define IRDMA_CQ_WQEIDX GENMASK_ULL(46, 32) 146 #define IRDMA_CQ_EXTCQE_S 50 147 #define IRDMA_CQ_EXTCQE BIT_ULL(50) 148 #define IRDMA_OOO_CMPL_S 54 149 #define IRDMA_OOO_CMPL BIT_ULL(54) 150 #define IRDMA_CQ_ERROR_S 55 151 #define IRDMA_CQ_ERROR BIT_ULL(55) 152 #define IRDMA_CQ_SQ_S 62 153 #define IRDMA_CQ_SQ BIT_ULL(62) 154 155 #define IRDMA_CQ_VALID_S 63 156 #define IRDMA_CQ_VALID BIT_ULL(63) 157 #define IRDMA_CQ_IMMVALID BIT_ULL(62) 158 #define IRDMA_CQ_UDSMACVALID_S 61 159 #define IRDMA_CQ_UDSMACVALID BIT_ULL(61) 160 #define IRDMA_CQ_UDVLANVALID_S 60 161 #define IRDMA_CQ_UDVLANVALID BIT_ULL(60) 162 #define IRDMA_CQ_UDSMAC_S 0 163 #define IRDMA_CQ_UDSMAC GENMASK_ULL(47, 0) 164 #define IRDMA_CQ_UDVLAN_S 48 165 #define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48) 166 167 #define IRDMA_CQ_IMMDATA_S 0 168 #define IRDMA_CQ_IMMVALID_S 62 169 #define IRDMA_CQ_IMMDATA GENMASK_ULL(125, 62) 170 #define IRDMA_CQ_IMMDATALOW32_S 0 171 #define IRDMA_CQ_IMMDATALOW32 GENMASK_ULL(31, 0) 172 #define IRDMA_CQ_IMMDATAUP32_S 32 173 #define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32) 174 #define IRDMACQ_PAYLDLEN_S 0 175 #define IRDMACQ_PAYLDLEN GENMASK_ULL(31, 0) 176 #define IRDMACQ_TCPSQN_ROCEPSN_RTT_TS_S 32 177 #define IRDMACQ_TCPSQN_ROCEPSN_RTT_TS GENMASK_ULL(63, 32) 178 #define IRDMACQ_INVSTAG_S 0 179 #define IRDMACQ_INVSTAG GENMASK_ULL(31, 0) 180 #define IRDMACQ_QPID_S 32 181 #define IRDMACQ_QPID GENMASK_ULL(55, 32) 182 183 #define IRDMACQ_UDSRCQPN_S 0 184 #define IRDMACQ_UDSRCQPN GENMASK_ULL(31, 0) 185 #define IRDMACQ_PSHDROP_S 51 186 #define IRDMACQ_PSHDROP BIT_ULL(51) 187 #define IRDMACQ_STAG_S 53 188 #define IRDMACQ_STAG BIT_ULL(53) 189 #define IRDMACQ_IPV4_S 53 190 #define IRDMACQ_IPV4 BIT_ULL(53) 191 #define IRDMACQ_SOEVENT_S 54 192 #define IRDMACQ_SOEVENT BIT_ULL(54) 193 #define IRDMACQ_OP_S 56 194 #define IRDMACQ_OP GENMASK_ULL(61, 56) 195 196 /* Manage Push Page - MPP */ 197 #define IRDMA_INVALID_PUSH_PAGE_INDEX_GEN_1 0xffff 198 #define IRDMA_INVALID_PUSH_PAGE_INDEX 0xffffffff 199 200 #define IRDMAQPSQ_OPCODE_S 32 201 #define IRDMAQPSQ_OPCODE GENMASK_ULL(37, 32) 202 #define IRDMAQPSQ_COPY_HOST_PBL_S 43 203 #define IRDMAQPSQ_COPY_HOST_PBL BIT_ULL(43) 204 #define IRDMAQPSQ_ADDFRAGCNT_S 38 205 #define IRDMAQPSQ_ADDFRAGCNT GENMASK_ULL(41, 38) 206 #define IRDMAQPSQ_PUSHWQE_S 56 207 #define IRDMAQPSQ_PUSHWQE BIT_ULL(56) 208 #define IRDMAQPSQ_STREAMMODE_S 58 209 #define IRDMAQPSQ_STREAMMODE BIT_ULL(58) 210 #define IRDMAQPSQ_WAITFORRCVPDU_S 59 211 #define IRDMAQPSQ_WAITFORRCVPDU BIT_ULL(59) 212 #define IRDMAQPSQ_READFENCE_S 60 213 #define IRDMAQPSQ_READFENCE BIT_ULL(60) 214 #define IRDMAQPSQ_LOCALFENCE_S 61 215 #define IRDMAQPSQ_LOCALFENCE BIT_ULL(61) 216 #define IRDMAQPSQ_UDPHEADER_S 61 217 #define IRDMAQPSQ_UDPHEADER BIT_ULL(61) 218 #define IRDMAQPSQ_L4LEN_S 42 219 #define IRDMAQPSQ_L4LEN GENMASK_ULL(45, 42) 220 #define IRDMAQPSQ_SIGCOMPL_S 62 221 #define IRDMAQPSQ_SIGCOMPL BIT_ULL(62) 222 #define IRDMAQPSQ_VALID_S 63 223 #define IRDMAQPSQ_VALID BIT_ULL(63) 224 225 #define IRDMAQPSQ_FRAG_TO_S IRDMA_CQPHC_QPCTX_S 226 #define IRDMAQPSQ_FRAG_TO IRDMA_CQPHC_QPCTX 227 #define IRDMAQPSQ_FRAG_VALID_S 63 228 #define IRDMAQPSQ_FRAG_VALID BIT_ULL(63) 229 #define IRDMAQPSQ_FRAG_LEN_S 32 230 #define IRDMAQPSQ_FRAG_LEN GENMASK_ULL(62, 32) 231 #define IRDMAQPSQ_FRAG_STAG_S 0 232 #define IRDMAQPSQ_FRAG_STAG GENMASK_ULL(31, 0) 233 #define IRDMAQPSQ_GEN1_FRAG_LEN_S 0 234 #define IRDMAQPSQ_GEN1_FRAG_LEN GENMASK_ULL(31, 0) 235 #define IRDMAQPSQ_GEN1_FRAG_STAG_S 32 236 #define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32) 237 #define IRDMAQPSQ_REMSTAGINV_S 0 238 #define IRDMAQPSQ_REMSTAGINV GENMASK_ULL(31, 0) 239 #define IRDMAQPSQ_DESTQKEY_S 0 240 #define IRDMAQPSQ_DESTQKEY GENMASK_ULL(31, 0) 241 #define IRDMAQPSQ_DESTQPN_S 32 242 #define IRDMAQPSQ_DESTQPN GENMASK_ULL(55, 32) 243 #define IRDMAQPSQ_AHID_S 0 244 #define IRDMAQPSQ_AHID GENMASK_ULL(16, 0) 245 #define IRDMAQPSQ_INLINEDATAFLAG_S 57 246 #define IRDMAQPSQ_INLINEDATAFLAG BIT_ULL(57) 247 248 #define IRDMA_INLINE_VALID_S 7 249 #define IRDMAQPSQ_INLINEDATALEN_S 48 250 #define IRDMAQPSQ_INLINEDATALEN GENMASK_ULL(55, 48) 251 #define IRDMAQPSQ_IMMDATAFLAG_S 47 252 #define IRDMAQPSQ_IMMDATAFLAG BIT_ULL(47) 253 #define IRDMAQPSQ_REPORTRTT_S 46 254 #define IRDMAQPSQ_REPORTRTT BIT_ULL(46) 255 256 #define IRDMAQPSQ_IMMDATA_S 0 257 #define IRDMAQPSQ_IMMDATA GENMASK_ULL(63, 0) 258 #define IRDMAQPSQ_REMSTAG_S 0 259 #define IRDMAQPSQ_REMSTAG GENMASK_ULL(31, 0) 260 261 #define IRDMAQPSQ_REMTO_S IRDMA_CQPHC_QPCTX_S 262 #define IRDMAQPSQ_REMTO IRDMA_CQPHC_QPCTX 263 264 #define IRDMAQPSQ_STAGRIGHTS_S 48 265 #define IRDMAQPSQ_STAGRIGHTS GENMASK_ULL(52, 48) 266 #define IRDMAQPSQ_VABASEDTO_S 53 267 #define IRDMAQPSQ_VABASEDTO BIT_ULL(53) 268 #define IRDMAQPSQ_MEMWINDOWTYPE_S 54 269 #define IRDMAQPSQ_MEMWINDOWTYPE BIT_ULL(54) 270 271 #define IRDMAQPSQ_MWLEN_S IRDMA_CQPHC_QPCTX_S 272 #define IRDMAQPSQ_MWLEN IRDMA_CQPHC_QPCTX 273 #define IRDMAQPSQ_PARENTMRSTAG_S 32 274 #define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32) 275 #define IRDMAQPSQ_MWSTAG_S 0 276 #define IRDMAQPSQ_MWSTAG GENMASK_ULL(31, 0) 277 278 #define IRDMAQPSQ_BASEVA_TO_FBO_S IRDMA_CQPHC_QPCTX_S 279 #define IRDMAQPSQ_BASEVA_TO_FBO IRDMA_CQPHC_QPCTX 280 281 #define IRDMAQPSQ_LOCSTAG_S 0 282 #define IRDMAQPSQ_LOCSTAG GENMASK_ULL(31, 0) 283 284 /* iwarp QP RQ WQE common fields */ 285 #define IRDMAQPRQ_ADDFRAGCNT_S IRDMAQPSQ_ADDFRAGCNT_S 286 #define IRDMAQPRQ_ADDFRAGCNT IRDMAQPSQ_ADDFRAGCNT 287 288 #define IRDMAQPRQ_VALID_S IRDMAQPSQ_VALID_S 289 #define IRDMAQPRQ_VALID IRDMAQPSQ_VALID 290 291 #define IRDMAQPRQ_COMPLCTX_S IRDMA_CQPHC_QPCTX_S 292 #define IRDMAQPRQ_COMPLCTX IRDMA_CQPHC_QPCTX 293 294 #define IRDMAQPRQ_FRAG_LEN_S IRDMAQPSQ_FRAG_LEN_S 295 #define IRDMAQPRQ_FRAG_LEN IRDMAQPSQ_FRAG_LEN 296 297 #define IRDMAQPRQ_STAG_S IRDMAQPSQ_FRAG_STAG_S 298 #define IRDMAQPRQ_STAG IRDMAQPSQ_FRAG_STAG 299 300 #define IRDMAQPRQ_TO_S IRDMAQPSQ_FRAG_TO_S 301 #define IRDMAQPRQ_TO IRDMAQPSQ_FRAG_TO 302 303 #define IRDMAPFINT_OICR_HMC_ERR_M BIT(26) 304 #define IRDMAPFINT_OICR_PE_PUSH_M BIT(27) 305 #define IRDMAPFINT_OICR_PE_CRITERR_M BIT(28) 306 307 #define IRDMA_GET_CURRENT_CQ_ELEM(_cq) \ 308 ( \ 309 (_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \ 310 ) 311 #define IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(_cq) \ 312 ( \ 313 ((struct irdma_extended_cqe *) \ 314 ((_cq)->cq_base))[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \ 315 ) 316 317 #define IRDMA_RING_INIT(_ring, _size) \ 318 { \ 319 (_ring).head = 0; \ 320 (_ring).tail = 0; \ 321 (_ring).size = (_size); \ 322 } 323 #define IRDMA_RING_SIZE(_ring) ((_ring).size) 324 #define IRDMA_RING_CURRENT_HEAD(_ring) ((_ring).head) 325 #define IRDMA_RING_CURRENT_TAIL(_ring) ((_ring).tail) 326 327 #define IRDMA_RING_MOVE_HEAD(_ring, _retcode) \ 328 { \ 329 register u32 size; \ 330 size = (_ring).size; \ 331 if (!IRDMA_RING_FULL_ERR(_ring)) { \ 332 (_ring).head = ((_ring).head + 1) % size; \ 333 (_retcode) = 0; \ 334 } else { \ 335 (_retcode) = ENOSPC; \ 336 } \ 337 } 338 #define IRDMA_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \ 339 { \ 340 register u32 size; \ 341 size = (_ring).size; \ 342 if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < size) { \ 343 (_ring).head = ((_ring).head + (_count)) % size; \ 344 (_retcode) = 0; \ 345 } else { \ 346 (_retcode) = ENOSPC; \ 347 } \ 348 } 349 #define IRDMA_SQ_RING_MOVE_HEAD(_ring, _retcode) \ 350 { \ 351 register u32 size; \ 352 size = (_ring).size; \ 353 if (!IRDMA_SQ_RING_FULL_ERR(_ring)) { \ 354 (_ring).head = ((_ring).head + 1) % size; \ 355 (_retcode) = 0; \ 356 } else { \ 357 (_retcode) = ENOSPC; \ 358 } \ 359 } 360 #define IRDMA_SQ_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \ 361 { \ 362 register u32 size; \ 363 size = (_ring).size; \ 364 if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \ 365 (_ring).head = ((_ring).head + (_count)) % size; \ 366 (_retcode) = 0; \ 367 } else { \ 368 (_retcode) = ENOSPC; \ 369 } \ 370 } 371 #define IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(_ring, _count) \ 372 (_ring).head = ((_ring).head + (_count)) % (_ring).size 373 374 #define IRDMA_RING_MOVE_TAIL(_ring) \ 375 (_ring).tail = ((_ring).tail + 1) % (_ring).size 376 377 #define IRDMA_RING_MOVE_HEAD_NOCHECK(_ring) \ 378 (_ring).head = ((_ring).head + 1) % (_ring).size 379 380 #define IRDMA_RING_MOVE_TAIL_BY_COUNT(_ring, _count) \ 381 (_ring).tail = ((_ring).tail + (_count)) % (_ring).size 382 383 #define IRDMA_RING_SET_TAIL(_ring, _pos) \ 384 (_ring).tail = (_pos) % (_ring).size 385 386 #define IRDMA_RING_FULL_ERR(_ring) \ 387 ( \ 388 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 1)) \ 389 ) 390 391 #define IRDMA_ERR_RING_FULL2(_ring) \ 392 ( \ 393 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 2)) \ 394 ) 395 396 #define IRDMA_ERR_RING_FULL3(_ring) \ 397 ( \ 398 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 3)) \ 399 ) 400 401 #define IRDMA_SQ_RING_FULL_ERR(_ring) \ 402 ( \ 403 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 257)) \ 404 ) 405 406 #define IRDMA_ERR_SQ_RING_FULL2(_ring) \ 407 ( \ 408 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 258)) \ 409 ) 410 #define IRDMA_ERR_SQ_RING_FULL3(_ring) \ 411 ( \ 412 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 259)) \ 413 ) 414 #define IRDMA_RING_MORE_WORK(_ring) \ 415 ( \ 416 (IRDMA_RING_USED_QUANTA(_ring) != 0) \ 417 ) 418 419 #define IRDMA_RING_USED_QUANTA(_ring) \ 420 ( \ 421 (((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \ 422 ) 423 424 #define IRDMA_RING_FREE_QUANTA(_ring) \ 425 ( \ 426 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 1) \ 427 ) 428 429 #define IRDMA_SQ_RING_FREE_QUANTA(_ring) \ 430 ( \ 431 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 257) \ 432 ) 433 434 #define IRDMA_ATOMIC_RING_MOVE_HEAD(_ring, index, _retcode) \ 435 { \ 436 index = IRDMA_RING_CURRENT_HEAD(_ring); \ 437 IRDMA_RING_MOVE_HEAD(_ring, _retcode); \ 438 } 439 440 enum irdma_protocol_used { 441 IRDMA_ANY_PROTOCOL = 0, 442 IRDMA_IWARP_PROTOCOL_ONLY = 1, 443 IRDMA_ROCE_PROTOCOL_ONLY = 2, 444 }; 445 446 enum irdma_qp_wqe_size { 447 IRDMA_WQE_SIZE_32 = 32, 448 IRDMA_WQE_SIZE_64 = 64, 449 IRDMA_WQE_SIZE_96 = 96, 450 IRDMA_WQE_SIZE_128 = 128, 451 IRDMA_WQE_SIZE_256 = 256, 452 }; 453 454 /** 455 * set_64bit_val - set 64 bit value to hw wqe 456 * @wqe_words: wqe addr to write 457 * @byte_index: index in wqe 458 * @val: value to write 459 **/ 460 static inline void set_64bit_val(__le64 *wqe_words, u32 byte_index, u64 val) 461 { 462 wqe_words[byte_index >> 3] = htole64(val); 463 } 464 465 /** 466 * set_32bit_val - set 32 bit value to hw wqe 467 * @wqe_words: wqe addr to write 468 * @byte_index: index in wqe 469 * @val: value to write 470 **/ 471 static inline void set_32bit_val(__le32 *wqe_words, u32 byte_index, u32 val) 472 { 473 wqe_words[byte_index >> 2] = htole32(val); 474 } 475 476 /** 477 * get_64bit_val - read 64 bit value from wqe 478 * @wqe_words: wqe addr 479 * @byte_index: index to read from 480 * @val: read value 481 **/ 482 static inline void get_64bit_val(__le64 *wqe_words, u32 byte_index, u64 *val) 483 { 484 *val = le64toh(wqe_words[byte_index >> 3]); 485 } 486 487 /** 488 * get_32bit_val - read 32 bit value from wqe 489 * @wqe_words: wqe addr 490 * @byte_index: index to reaad from 491 * @val: return 32 bit value 492 **/ 493 static inline void get_32bit_val(__le32 *wqe_words, u32 byte_index, u32 *val) 494 { 495 *val = le32toh(wqe_words[byte_index >> 2]); 496 } 497 #endif /* IRDMA_DEFS_H */ 498