1 /*-
2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
3 *
4 * Copyright (c) 2015 - 2023 Intel Corporation
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenFabrics.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #ifndef IRDMA_DEFS_H
36 #define IRDMA_DEFS_H
37
38 #define IRDMA_BYTE_0 0
39 #define IRDMA_BYTE_8 8
40 #define IRDMA_BYTE_16 16
41 #define IRDMA_BYTE_24 24
42 #define IRDMA_BYTE_32 32
43 #define IRDMA_BYTE_40 40
44 #define IRDMA_BYTE_48 48
45 #define IRDMA_BYTE_56 56
46 #define IRDMA_BYTE_64 64
47 #define IRDMA_BYTE_72 72
48 #define IRDMA_BYTE_80 80
49 #define IRDMA_BYTE_88 88
50 #define IRDMA_BYTE_96 96
51 #define IRDMA_BYTE_104 104
52 #define IRDMA_BYTE_112 112
53 #define IRDMA_BYTE_120 120
54 #define IRDMA_BYTE_128 128
55 #define IRDMA_BYTE_136 136
56 #define IRDMA_BYTE_144 144
57 #define IRDMA_BYTE_152 152
58 #define IRDMA_BYTE_160 160
59 #define IRDMA_BYTE_168 168
60 #define IRDMA_BYTE_176 176
61 #define IRDMA_BYTE_184 184
62 #define IRDMA_BYTE_192 192
63 #define IRDMA_BYTE_200 200
64 #define IRDMA_BYTE_208 208
65 #define IRDMA_BYTE_216 216
66
67 #define IRDMA_QP_TYPE_IWARP 1
68 #define IRDMA_QP_TYPE_UDA 2
69 #define IRDMA_QP_TYPE_ROCE_RC 3
70 #define IRDMA_QP_TYPE_ROCE_UD 4
71
72 #define IRDMA_HW_PAGE_SIZE 4096
73 #define IRDMA_HW_PAGE_SHIFT 12
74 #define IRDMA_CQE_QTYPE_RQ 0
75 #define IRDMA_CQE_QTYPE_SQ 1
76
77 #define IRDMA_QP_SW_MIN_WQSIZE 8 /* in WRs*/
78 #define IRDMA_QP_WQE_MIN_SIZE 32
79 #define IRDMA_QP_WQE_MAX_SIZE 256
80 #define IRDMA_QP_WQE_MIN_QUANTA 1
81 #define IRDMA_MAX_RQ_WQE_SHIFT_GEN1 2
82 #define IRDMA_MAX_RQ_WQE_SHIFT_GEN2 3
83
84 #define IRDMA_SQ_RSVD 258
85 #define IRDMA_RQ_RSVD 1
86
87 #define IRDMA_FEATURE_RTS_AE BIT_ULL(0)
88 #define IRDMA_FEATURE_CQ_RESIZE BIT_ULL(1)
89 #define IRDMA_FEATURE_RELAX_RQ_ORDER BIT_ULL(2)
90 #define IRDMA_FEATURE_64_BYTE_CQE BIT_ULL(5)
91
92 #define IRDMAQP_OP_RDMA_WRITE 0x00
93 #define IRDMAQP_OP_RDMA_READ 0x01
94 #define IRDMAQP_OP_RDMA_SEND 0x03
95 #define IRDMAQP_OP_RDMA_SEND_INV 0x04
96 #define IRDMAQP_OP_RDMA_SEND_SOL_EVENT 0x05
97 #define IRDMAQP_OP_RDMA_SEND_SOL_EVENT_INV 0x06
98 #define IRDMAQP_OP_BIND_MW 0x08
99 #define IRDMAQP_OP_FAST_REGISTER 0x09
100 #define IRDMAQP_OP_LOCAL_INVALIDATE 0x0a
101 #define IRDMAQP_OP_RDMA_READ_LOC_INV 0x0b
102 #define IRDMAQP_OP_NOP 0x0c
103
104 #ifndef LS_64_1
105 #define LS_64_1(val, bits) ((u64)(uintptr_t)(val) << (bits))
106 #define RS_64_1(val, bits) ((u64)(uintptr_t)(val) >> (bits))
107 #define LS_32_1(val, bits) ((u32)((val) << (bits)))
108 #define RS_32_1(val, bits) ((u32)((val) >> (bits)))
109 #endif
110 #ifndef GENMASK_ULL
111 #define GENMASK_ULL(high, low) ((0xFFFFFFFFFFFFFFFFULL >> (64ULL - ((high) - (low) + 1ULL))) << (low))
112 #endif /* GENMASK_ULL */
113 #ifndef GENMASK
114 #define GENMASK(high, low) ((0xFFFFFFFFUL >> (32UL - ((high) - (low) + 1UL))) << (low))
115 #endif /* GENMASK */
116 #ifndef FIELD_PREP
117 #define FIELD_PREP(mask, val) (((u64)(val) << mask##_S) & (mask))
118 #define FIELD_GET(mask, val) (((val) & mask) >> mask##_S)
119 #endif /* FIELD_PREP */
120
121 #define IRDMA_CQPHC_QPCTX_S 0
122 #define IRDMA_CQPHC_QPCTX GENMASK_ULL(63, 0)
123 #define IRDMA_QP_DBSA_HW_SQ_TAIL_S 0
124 #define IRDMA_QP_DBSA_HW_SQ_TAIL GENMASK_ULL(14, 0)
125 #define IRDMA_CQ_DBSA_CQEIDX_S 0
126 #define IRDMA_CQ_DBSA_CQEIDX GENMASK_ULL(19, 0)
127 #define IRDMA_CQ_DBSA_SW_CQ_SELECT_S 0
128 #define IRDMA_CQ_DBSA_SW_CQ_SELECT GENMASK_ULL(13, 0)
129 #define IRDMA_CQ_DBSA_ARM_NEXT_S 14
130 #define IRDMA_CQ_DBSA_ARM_NEXT BIT_ULL(14)
131 #define IRDMA_CQ_DBSA_ARM_NEXT_SE_S 15
132 #define IRDMA_CQ_DBSA_ARM_NEXT_SE BIT_ULL(15)
133 #define IRDMA_CQ_DBSA_ARM_SEQ_NUM_S 16
134 #define IRDMA_CQ_DBSA_ARM_SEQ_NUM GENMASK_ULL(17, 16)
135
136 /* CQP and iWARP Completion Queue */
137 #define IRDMA_CQ_QPCTX_S IRDMA_CQPHC_QPCTX_S
138 #define IRDMA_CQ_QPCTX IRDMA_CQPHC_QPCTX
139
140 #define IRDMA_CQ_MINERR_S 0
141 #define IRDMA_CQ_MINERR GENMASK_ULL(15, 0)
142 #define IRDMA_CQ_MAJERR_S 16
143 #define IRDMA_CQ_MAJERR GENMASK_ULL(31, 16)
144 #define IRDMA_CQ_WQEIDX_S 32
145 #define IRDMA_CQ_WQEIDX GENMASK_ULL(46, 32)
146 #define IRDMA_CQ_EXTCQE_S 50
147 #define IRDMA_CQ_EXTCQE BIT_ULL(50)
148 #define IRDMA_OOO_CMPL_S 54
149 #define IRDMA_OOO_CMPL BIT_ULL(54)
150 #define IRDMA_CQ_ERROR_S 55
151 #define IRDMA_CQ_ERROR BIT_ULL(55)
152 #define IRDMA_CQ_SQ_S 62
153 #define IRDMA_CQ_SQ BIT_ULL(62)
154
155 #define IRDMA_CQ_VALID_S 63
156 #define IRDMA_CQ_VALID BIT_ULL(63)
157 #define IRDMA_CQ_IMMVALID BIT_ULL(62)
158 #define IRDMA_CQ_UDSMACVALID_S 61
159 #define IRDMA_CQ_UDSMACVALID BIT_ULL(61)
160 #define IRDMA_CQ_UDVLANVALID_S 60
161 #define IRDMA_CQ_UDVLANVALID BIT_ULL(60)
162 #define IRDMA_CQ_UDSMAC_S 0
163 #define IRDMA_CQ_UDSMAC GENMASK_ULL(47, 0)
164 #define IRDMA_CQ_UDVLAN_S 48
165 #define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48)
166
167 #define IRDMA_CQ_IMMDATA_S 0
168 #define IRDMA_CQ_IMMVALID_S 62
169 #define IRDMA_CQ_IMMDATA GENMASK_ULL(125, 62)
170 #define IRDMA_CQ_IMMDATALOW32_S 0
171 #define IRDMA_CQ_IMMDATALOW32 GENMASK_ULL(31, 0)
172 #define IRDMA_CQ_IMMDATAUP32_S 32
173 #define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32)
174 #define IRDMACQ_PAYLDLEN_S 0
175 #define IRDMACQ_PAYLDLEN GENMASK_ULL(31, 0)
176 #define IRDMACQ_TCPSQN_ROCEPSN_RTT_TS_S 32
177 #define IRDMACQ_TCPSQN_ROCEPSN_RTT_TS GENMASK_ULL(63, 32)
178 #define IRDMACQ_INVSTAG_S 0
179 #define IRDMACQ_INVSTAG GENMASK_ULL(31, 0)
180 #define IRDMACQ_QPID_S 32
181 #define IRDMACQ_QPID GENMASK_ULL(55, 32)
182
183 #define IRDMACQ_UDSRCQPN_S 0
184 #define IRDMACQ_UDSRCQPN GENMASK_ULL(31, 0)
185 #define IRDMACQ_PSHDROP_S 51
186 #define IRDMACQ_PSHDROP BIT_ULL(51)
187 #define IRDMACQ_STAG_S 53
188 #define IRDMACQ_STAG BIT_ULL(53)
189 #define IRDMACQ_IPV4_S 53
190 #define IRDMACQ_IPV4 BIT_ULL(53)
191 #define IRDMACQ_SOEVENT_S 54
192 #define IRDMACQ_SOEVENT BIT_ULL(54)
193 #define IRDMACQ_OP_S 56
194 #define IRDMACQ_OP GENMASK_ULL(61, 56)
195
196 /* Manage Push Page - MPP */
197 #define IRDMA_INVALID_PUSH_PAGE_INDEX_GEN_1 0xffff
198 #define IRDMA_INVALID_PUSH_PAGE_INDEX 0xffffffff
199
200 #define IRDMAQPSQ_OPCODE_S 32
201 #define IRDMAQPSQ_OPCODE GENMASK_ULL(37, 32)
202 #define IRDMAQPSQ_COPY_HOST_PBL_S 43
203 #define IRDMAQPSQ_COPY_HOST_PBL BIT_ULL(43)
204 #define IRDMAQPSQ_ADDFRAGCNT_S 38
205 #define IRDMAQPSQ_ADDFRAGCNT GENMASK_ULL(41, 38)
206 #define IRDMAQPSQ_PUSHWQE_S 56
207 #define IRDMAQPSQ_PUSHWQE BIT_ULL(56)
208 #define IRDMAQPSQ_STREAMMODE_S 58
209 #define IRDMAQPSQ_STREAMMODE BIT_ULL(58)
210 #define IRDMAQPSQ_WAITFORRCVPDU_S 59
211 #define IRDMAQPSQ_WAITFORRCVPDU BIT_ULL(59)
212 #define IRDMAQPSQ_READFENCE_S 60
213 #define IRDMAQPSQ_READFENCE BIT_ULL(60)
214 #define IRDMAQPSQ_LOCALFENCE_S 61
215 #define IRDMAQPSQ_LOCALFENCE BIT_ULL(61)
216 #define IRDMAQPSQ_UDPHEADER_S 61
217 #define IRDMAQPSQ_UDPHEADER BIT_ULL(61)
218 #define IRDMAQPSQ_L4LEN_S 42
219 #define IRDMAQPSQ_L4LEN GENMASK_ULL(45, 42)
220 #define IRDMAQPSQ_SIGCOMPL_S 62
221 #define IRDMAQPSQ_SIGCOMPL BIT_ULL(62)
222 #define IRDMAQPSQ_VALID_S 63
223 #define IRDMAQPSQ_VALID BIT_ULL(63)
224
225 #define IRDMAQPSQ_FRAG_TO_S IRDMA_CQPHC_QPCTX_S
226 #define IRDMAQPSQ_FRAG_TO IRDMA_CQPHC_QPCTX
227 #define IRDMAQPSQ_FRAG_VALID_S 63
228 #define IRDMAQPSQ_FRAG_VALID BIT_ULL(63)
229 #define IRDMAQPSQ_FRAG_LEN_S 32
230 #define IRDMAQPSQ_FRAG_LEN GENMASK_ULL(62, 32)
231 #define IRDMAQPSQ_FRAG_STAG_S 0
232 #define IRDMAQPSQ_FRAG_STAG GENMASK_ULL(31, 0)
233 #define IRDMAQPSQ_GEN1_FRAG_LEN_S 0
234 #define IRDMAQPSQ_GEN1_FRAG_LEN GENMASK_ULL(31, 0)
235 #define IRDMAQPSQ_GEN1_FRAG_STAG_S 32
236 #define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32)
237 #define IRDMAQPSQ_REMSTAGINV_S 0
238 #define IRDMAQPSQ_REMSTAGINV GENMASK_ULL(31, 0)
239 #define IRDMAQPSQ_DESTQKEY_S 0
240 #define IRDMAQPSQ_DESTQKEY GENMASK_ULL(31, 0)
241 #define IRDMAQPSQ_DESTQPN_S 32
242 #define IRDMAQPSQ_DESTQPN GENMASK_ULL(55, 32)
243 #define IRDMAQPSQ_AHID_S 0
244 #define IRDMAQPSQ_AHID GENMASK_ULL(16, 0)
245 #define IRDMAQPSQ_INLINEDATAFLAG_S 57
246 #define IRDMAQPSQ_INLINEDATAFLAG BIT_ULL(57)
247
248 #define IRDMA_INLINE_VALID_S 7
249 #define IRDMAQPSQ_INLINEDATALEN_S 48
250 #define IRDMAQPSQ_INLINEDATALEN GENMASK_ULL(55, 48)
251 #define IRDMAQPSQ_IMMDATAFLAG_S 47
252 #define IRDMAQPSQ_IMMDATAFLAG BIT_ULL(47)
253 #define IRDMAQPSQ_REPORTRTT_S 46
254 #define IRDMAQPSQ_REPORTRTT BIT_ULL(46)
255
256 #define IRDMAQPSQ_IMMDATA_S 0
257 #define IRDMAQPSQ_IMMDATA GENMASK_ULL(63, 0)
258 #define IRDMAQPSQ_REMSTAG_S 0
259 #define IRDMAQPSQ_REMSTAG GENMASK_ULL(31, 0)
260
261 #define IRDMAQPSQ_REMTO_S IRDMA_CQPHC_QPCTX_S
262 #define IRDMAQPSQ_REMTO IRDMA_CQPHC_QPCTX
263
264 #define IRDMAQPSQ_STAGRIGHTS_S 48
265 #define IRDMAQPSQ_STAGRIGHTS GENMASK_ULL(52, 48)
266 #define IRDMAQPSQ_VABASEDTO_S 53
267 #define IRDMAQPSQ_VABASEDTO BIT_ULL(53)
268 #define IRDMAQPSQ_MEMWINDOWTYPE_S 54
269 #define IRDMAQPSQ_MEMWINDOWTYPE BIT_ULL(54)
270
271 #define IRDMAQPSQ_MWLEN_S IRDMA_CQPHC_QPCTX_S
272 #define IRDMAQPSQ_MWLEN IRDMA_CQPHC_QPCTX
273 #define IRDMAQPSQ_PARENTMRSTAG_S 32
274 #define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32)
275 #define IRDMAQPSQ_MWSTAG_S 0
276 #define IRDMAQPSQ_MWSTAG GENMASK_ULL(31, 0)
277
278 #define IRDMAQPSQ_BASEVA_TO_FBO_S IRDMA_CQPHC_QPCTX_S
279 #define IRDMAQPSQ_BASEVA_TO_FBO IRDMA_CQPHC_QPCTX
280
281 #define IRDMAQPSQ_LOCSTAG_S 0
282 #define IRDMAQPSQ_LOCSTAG GENMASK_ULL(31, 0)
283
284 /* iwarp QP RQ WQE common fields */
285 #define IRDMAQPRQ_ADDFRAGCNT_S IRDMAQPSQ_ADDFRAGCNT_S
286 #define IRDMAQPRQ_ADDFRAGCNT IRDMAQPSQ_ADDFRAGCNT
287
288 #define IRDMAQPRQ_VALID_S IRDMAQPSQ_VALID_S
289 #define IRDMAQPRQ_VALID IRDMAQPSQ_VALID
290
291 #define IRDMAQPRQ_COMPLCTX_S IRDMA_CQPHC_QPCTX_S
292 #define IRDMAQPRQ_COMPLCTX IRDMA_CQPHC_QPCTX
293
294 #define IRDMAQPRQ_FRAG_LEN_S IRDMAQPSQ_FRAG_LEN_S
295 #define IRDMAQPRQ_FRAG_LEN IRDMAQPSQ_FRAG_LEN
296
297 #define IRDMAQPRQ_STAG_S IRDMAQPSQ_FRAG_STAG_S
298 #define IRDMAQPRQ_STAG IRDMAQPSQ_FRAG_STAG
299
300 #define IRDMAQPRQ_TO_S IRDMAQPSQ_FRAG_TO_S
301 #define IRDMAQPRQ_TO IRDMAQPSQ_FRAG_TO
302
303 #define IRDMAPFINT_OICR_HMC_ERR_M BIT(26)
304 #define IRDMAPFINT_OICR_PE_PUSH_M BIT(27)
305 #define IRDMAPFINT_OICR_PE_CRITERR_M BIT(28)
306
307 #define IRDMA_GET_RING_OFFSET(_ring, _i) \
308 ( \
309 ((_ring).head + (_i)) % (_ring).size \
310 )
311
312 #define IRDMA_GET_CQ_ELEM_AT_OFFSET(_cq, _i, _cqe) \
313 { \
314 __u32 offset; \
315 offset = IRDMA_GET_RING_OFFSET((_cq)->cq_ring, _i); \
316 (_cqe) = (_cq)->cq_base[offset].buf; \
317 }
318 #define IRDMA_GET_CURRENT_CQ_ELEM(_cq) \
319 ( \
320 (_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
321 )
322 #define IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(_cq) \
323 ( \
324 ((struct irdma_extended_cqe *) \
325 ((_cq)->cq_base))[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
326 )
327
328 #define IRDMA_RING_INIT(_ring, _size) \
329 { \
330 (_ring).head = 0; \
331 (_ring).tail = 0; \
332 (_ring).size = (_size); \
333 }
334 #define IRDMA_RING_SIZE(_ring) ((_ring).size)
335 #define IRDMA_RING_CURRENT_HEAD(_ring) ((_ring).head)
336 #define IRDMA_RING_CURRENT_TAIL(_ring) ((_ring).tail)
337
338 #define IRDMA_RING_MOVE_HEAD(_ring, _retcode) \
339 { \
340 u32 size; \
341 size = (_ring).size; \
342 if (!IRDMA_RING_FULL_ERR(_ring)) { \
343 (_ring).head = ((_ring).head + 1) % size; \
344 (_retcode) = 0; \
345 } else { \
346 (_retcode) = ENOSPC; \
347 } \
348 }
349 #define IRDMA_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \
350 { \
351 u32 size; \
352 size = (_ring).size; \
353 if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < size) { \
354 (_ring).head = ((_ring).head + (_count)) % size; \
355 (_retcode) = 0; \
356 } else { \
357 (_retcode) = ENOSPC; \
358 } \
359 }
360 #define IRDMA_SQ_RING_MOVE_HEAD(_ring, _retcode) \
361 { \
362 u32 size; \
363 size = (_ring).size; \
364 if (!IRDMA_SQ_RING_FULL_ERR(_ring)) { \
365 (_ring).head = ((_ring).head + 1) % size; \
366 (_retcode) = 0; \
367 } else { \
368 (_retcode) = ENOSPC; \
369 } \
370 }
371 #define IRDMA_SQ_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \
372 { \
373 u32 size; \
374 size = (_ring).size; \
375 if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \
376 (_ring).head = ((_ring).head + (_count)) % size; \
377 (_retcode) = 0; \
378 } else { \
379 (_retcode) = ENOSPC; \
380 } \
381 }
382 #define IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(_ring, _count) \
383 (_ring).head = ((_ring).head + (_count)) % (_ring).size
384
385 #define IRDMA_RING_MOVE_TAIL(_ring) \
386 (_ring).tail = ((_ring).tail + 1) % (_ring).size
387
388 #define IRDMA_RING_MOVE_HEAD_NOCHECK(_ring) \
389 (_ring).head = ((_ring).head + 1) % (_ring).size
390
391 #define IRDMA_RING_MOVE_TAIL_BY_COUNT(_ring, _count) \
392 (_ring).tail = ((_ring).tail + (_count)) % (_ring).size
393
394 #define IRDMA_RING_SET_TAIL(_ring, _pos) \
395 (_ring).tail = (_pos) % (_ring).size
396
397 #define IRDMA_RING_FULL_ERR(_ring) \
398 ( \
399 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 1)) \
400 )
401
402 #define IRDMA_ERR_RING_FULL2(_ring) \
403 ( \
404 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 2)) \
405 )
406
407 #define IRDMA_ERR_RING_FULL3(_ring) \
408 ( \
409 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 3)) \
410 )
411
412 #define IRDMA_SQ_RING_FULL_ERR(_ring) \
413 ( \
414 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 257)) \
415 )
416
417 #define IRDMA_ERR_SQ_RING_FULL2(_ring) \
418 ( \
419 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 258)) \
420 )
421 #define IRDMA_ERR_SQ_RING_FULL3(_ring) \
422 ( \
423 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 259)) \
424 )
425 #define IRDMA_RING_MORE_WORK(_ring) \
426 ( \
427 (IRDMA_RING_USED_QUANTA(_ring) != 0) \
428 )
429
430 #define IRDMA_RING_USED_QUANTA(_ring) \
431 ( \
432 (((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \
433 )
434
435 #define IRDMA_RING_FREE_QUANTA(_ring) \
436 ( \
437 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 1) \
438 )
439
440 #define IRDMA_SQ_RING_FREE_QUANTA(_ring) \
441 ( \
442 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 257) \
443 )
444
445 #define IRDMA_ATOMIC_RING_MOVE_HEAD(_ring, index, _retcode) \
446 { \
447 index = IRDMA_RING_CURRENT_HEAD(_ring); \
448 IRDMA_RING_MOVE_HEAD(_ring, _retcode); \
449 }
450
451 enum irdma_qp_wqe_size {
452 IRDMA_WQE_SIZE_32 = 32,
453 IRDMA_WQE_SIZE_64 = 64,
454 IRDMA_WQE_SIZE_96 = 96,
455 IRDMA_WQE_SIZE_128 = 128,
456 IRDMA_WQE_SIZE_256 = 256,
457 };
458
459 /**
460 * set_64bit_val - set 64 bit value to hw wqe
461 * @wqe_words: wqe addr to write
462 * @byte_index: index in wqe
463 * @val: value to write
464 **/
set_64bit_val(__le64 * wqe_words,u32 byte_index,u64 val)465 static inline void set_64bit_val(__le64 *wqe_words, u32 byte_index, u64 val)
466 {
467 wqe_words[byte_index >> 3] = htole64(val);
468 }
469
470 /**
471 * set_32bit_val - set 32 bit value to hw wqe
472 * @wqe_words: wqe addr to write
473 * @byte_index: index in wqe
474 * @val: value to write
475 **/
set_32bit_val(__le32 * wqe_words,u32 byte_index,u32 val)476 static inline void set_32bit_val(__le32 *wqe_words, u32 byte_index, u32 val)
477 {
478 wqe_words[byte_index >> 2] = htole32(val);
479 }
480
481 /**
482 * get_64bit_val - read 64 bit value from wqe
483 * @wqe_words: wqe addr
484 * @byte_index: index to read from
485 * @val: read value
486 **/
get_64bit_val(__le64 * wqe_words,u32 byte_index,u64 * val)487 static inline void get_64bit_val(__le64 *wqe_words, u32 byte_index, u64 *val)
488 {
489 *val = le64toh(wqe_words[byte_index >> 3]);
490 }
491
492 /**
493 * get_32bit_val - read 32 bit value from wqe
494 * @wqe_words: wqe addr
495 * @byte_index: index to reaad from
496 * @val: return 32 bit value
497 **/
get_32bit_val(__le32 * wqe_words,u32 byte_index,u32 * val)498 static inline void get_32bit_val(__le32 *wqe_words, u32 byte_index, u32 *val)
499 {
500 *val = le32toh(wqe_words[byte_index >> 2]);
501 }
502 #endif /* IRDMA_DEFS_H */
503