xref: /freebsd/contrib/ofed/libirdma/irdma_defs.h (revision e6bfd18d21b225af6a0ed67ceeaf1293b7b9eba5)
1 /*-
2  * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
3  *
4  * Copyright (c) 2015 - 2022 Intel Corporation
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenFabrics.org BSD license below:
11  *
12  *   Redistribution and use in source and binary forms, with or
13  *   without modification, are permitted provided that the following
14  *   conditions are met:
15  *
16  *    - Redistributions of source code must retain the above
17  *	copyright notice, this list of conditions and the following
18  *	disclaimer.
19  *
20  *    - Redistributions in binary form must reproduce the above
21  *	copyright notice, this list of conditions and the following
22  *	disclaimer in the documentation and/or other materials
23  *	provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  */
34 /*$FreeBSD$*/
35 
36 #ifndef IRDMA_DEFS_H
37 #define IRDMA_DEFS_H
38 
39 #define IRDMA_BYTE_0		0
40 #define IRDMA_BYTE_8		8
41 #define IRDMA_BYTE_16		16
42 #define IRDMA_BYTE_24		24
43 #define IRDMA_BYTE_32		32
44 #define IRDMA_BYTE_40		40
45 #define IRDMA_BYTE_48		48
46 #define IRDMA_BYTE_56		56
47 #define IRDMA_BYTE_64		64
48 #define IRDMA_BYTE_72		72
49 #define IRDMA_BYTE_80		80
50 #define IRDMA_BYTE_88		88
51 #define IRDMA_BYTE_96		96
52 #define IRDMA_BYTE_104		104
53 #define IRDMA_BYTE_112		112
54 #define IRDMA_BYTE_120		120
55 #define IRDMA_BYTE_128		128
56 #define IRDMA_BYTE_136		136
57 #define IRDMA_BYTE_144		144
58 #define IRDMA_BYTE_152		152
59 #define IRDMA_BYTE_160		160
60 #define IRDMA_BYTE_168		168
61 #define IRDMA_BYTE_176		176
62 #define IRDMA_BYTE_184		184
63 #define IRDMA_BYTE_192		192
64 #define IRDMA_BYTE_200		200
65 #define IRDMA_BYTE_208		208
66 #define IRDMA_BYTE_216		216
67 
68 #define IRDMA_QP_TYPE_IWARP	1
69 #define IRDMA_QP_TYPE_UDA	2
70 #define IRDMA_QP_TYPE_ROCE_RC	3
71 #define IRDMA_QP_TYPE_ROCE_UD	4
72 
73 #define IRDMA_HW_PAGE_SIZE	4096
74 #define IRDMA_HW_PAGE_SHIFT	12
75 #define IRDMA_CQE_QTYPE_RQ	0
76 #define IRDMA_CQE_QTYPE_SQ	1
77 
78 #define IRDMA_QP_SW_MIN_WQSIZE	8 /* in WRs*/
79 #define IRDMA_QP_WQE_MIN_SIZE	32
80 #define IRDMA_QP_WQE_MAX_SIZE	256
81 #define IRDMA_QP_WQE_MIN_QUANTA 1
82 #define IRDMA_MAX_RQ_WQE_SHIFT_GEN1 2
83 #define IRDMA_MAX_RQ_WQE_SHIFT_GEN2 3
84 
85 #define IRDMA_SQ_RSVD	258
86 #define IRDMA_RQ_RSVD	1
87 
88 #define IRDMA_FEATURE_RTS_AE			BIT_ULL(0)
89 #define IRDMA_FEATURE_CQ_RESIZE			BIT_ULL(1)
90 #define IRDMA_FEATURE_RELAX_RQ_ORDER		BIT_ULL(2)
91 #define IRDMA_FEATURE_64_BYTE_CQE		BIT_ULL(5)
92 
93 #define IRDMAQP_OP_RDMA_WRITE			0x00
94 #define IRDMAQP_OP_RDMA_READ			0x01
95 #define IRDMAQP_OP_RDMA_SEND			0x03
96 #define IRDMAQP_OP_RDMA_SEND_INV		0x04
97 #define IRDMAQP_OP_RDMA_SEND_SOL_EVENT		0x05
98 #define IRDMAQP_OP_RDMA_SEND_SOL_EVENT_INV	0x06
99 #define IRDMAQP_OP_BIND_MW			0x08
100 #define IRDMAQP_OP_FAST_REGISTER		0x09
101 #define IRDMAQP_OP_LOCAL_INVALIDATE		0x0a
102 #define IRDMAQP_OP_RDMA_READ_LOC_INV		0x0b
103 #define IRDMAQP_OP_NOP				0x0c
104 
105 #ifndef LS_64_1
106 #define LS_64_1(val, bits)	((u64)(uintptr_t)(val) << (bits))
107 #define RS_64_1(val, bits)	((u64)(uintptr_t)(val) >> (bits))
108 #define LS_32_1(val, bits)	((u32)((val) << (bits)))
109 #define RS_32_1(val, bits)	((u32)((val) >> (bits)))
110 #endif
111 #ifndef GENMASK_ULL
112 #define GENMASK_ULL(high, low)	((0xFFFFFFFFFFFFFFFFULL >> (64ULL - ((high) - (low) + 1ULL))) << (low))
113 #endif /* GENMASK_ULL */
114 #ifndef GENMASK
115 #define GENMASK(high, low)	((0xFFFFFFFFUL >> (32UL - ((high) - (low) + 1UL))) << (low))
116 #endif /* GENMASK */
117 #ifndef FIELD_PREP
118 #define FIELD_PREP(mask, val)	(((u64)(val) << mask##_S) & (mask))
119 #define FIELD_GET(mask, val)	(((val) & mask) >> mask##_S)
120 #endif /* FIELD_PREP */
121 
122 #define IRDMA_CQPHC_QPCTX_S 0
123 #define IRDMA_CQPHC_QPCTX GENMASK_ULL(63, 0)
124 #define IRDMA_QP_DBSA_HW_SQ_TAIL_S 0
125 #define IRDMA_QP_DBSA_HW_SQ_TAIL GENMASK_ULL(14, 0)
126 #define IRDMA_CQ_DBSA_CQEIDX_S 0
127 #define IRDMA_CQ_DBSA_CQEIDX GENMASK_ULL(19, 0)
128 #define IRDMA_CQ_DBSA_SW_CQ_SELECT_S 0
129 #define IRDMA_CQ_DBSA_SW_CQ_SELECT GENMASK_ULL(13, 0)
130 #define IRDMA_CQ_DBSA_ARM_NEXT_S 14
131 #define IRDMA_CQ_DBSA_ARM_NEXT BIT_ULL(14)
132 #define IRDMA_CQ_DBSA_ARM_NEXT_SE_S 15
133 #define IRDMA_CQ_DBSA_ARM_NEXT_SE BIT_ULL(15)
134 #define IRDMA_CQ_DBSA_ARM_SEQ_NUM_S 16
135 #define IRDMA_CQ_DBSA_ARM_SEQ_NUM GENMASK_ULL(17, 16)
136 
137 /* CQP and iWARP Completion Queue */
138 #define IRDMA_CQ_QPCTX_S IRDMA_CQPHC_QPCTX_S
139 #define IRDMA_CQ_QPCTX IRDMA_CQPHC_QPCTX
140 
141 #define IRDMA_CQ_MINERR_S 0
142 #define IRDMA_CQ_MINERR GENMASK_ULL(15, 0)
143 #define IRDMA_CQ_MAJERR_S 16
144 #define IRDMA_CQ_MAJERR GENMASK_ULL(31, 16)
145 #define IRDMA_CQ_WQEIDX_S 32
146 #define IRDMA_CQ_WQEIDX GENMASK_ULL(46, 32)
147 #define IRDMA_CQ_EXTCQE_S 50
148 #define IRDMA_CQ_EXTCQE BIT_ULL(50)
149 #define IRDMA_OOO_CMPL_S 54
150 #define IRDMA_OOO_CMPL BIT_ULL(54)
151 #define IRDMA_CQ_ERROR_S 55
152 #define IRDMA_CQ_ERROR BIT_ULL(55)
153 #define IRDMA_CQ_SQ_S 62
154 #define IRDMA_CQ_SQ BIT_ULL(62)
155 
156 #define IRDMA_CQ_VALID_S 63
157 #define IRDMA_CQ_VALID BIT_ULL(63)
158 #define IRDMA_CQ_IMMVALID BIT_ULL(62)
159 #define IRDMA_CQ_UDSMACVALID_S 61
160 #define IRDMA_CQ_UDSMACVALID BIT_ULL(61)
161 #define IRDMA_CQ_UDVLANVALID_S 60
162 #define IRDMA_CQ_UDVLANVALID BIT_ULL(60)
163 #define IRDMA_CQ_UDSMAC_S 0
164 #define IRDMA_CQ_UDSMAC GENMASK_ULL(47, 0)
165 #define IRDMA_CQ_UDVLAN_S 48
166 #define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48)
167 
168 #define IRDMA_CQ_IMMDATA_S 0
169 #define IRDMA_CQ_IMMVALID_S 62
170 #define IRDMA_CQ_IMMDATA GENMASK_ULL(125, 62)
171 #define IRDMA_CQ_IMMDATALOW32_S 0
172 #define IRDMA_CQ_IMMDATALOW32 GENMASK_ULL(31, 0)
173 #define IRDMA_CQ_IMMDATAUP32_S 32
174 #define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32)
175 #define IRDMACQ_PAYLDLEN_S 0
176 #define IRDMACQ_PAYLDLEN GENMASK_ULL(31, 0)
177 #define IRDMACQ_TCPSQN_ROCEPSN_RTT_TS_S 32
178 #define IRDMACQ_TCPSQN_ROCEPSN_RTT_TS GENMASK_ULL(63, 32)
179 #define IRDMACQ_INVSTAG_S 0
180 #define IRDMACQ_INVSTAG GENMASK_ULL(31, 0)
181 #define IRDMACQ_QPID_S 32
182 #define IRDMACQ_QPID GENMASK_ULL(55, 32)
183 
184 #define IRDMACQ_UDSRCQPN_S 0
185 #define IRDMACQ_UDSRCQPN GENMASK_ULL(31, 0)
186 #define IRDMACQ_PSHDROP_S 51
187 #define IRDMACQ_PSHDROP BIT_ULL(51)
188 #define IRDMACQ_STAG_S 53
189 #define IRDMACQ_STAG BIT_ULL(53)
190 #define IRDMACQ_IPV4_S 53
191 #define IRDMACQ_IPV4 BIT_ULL(53)
192 #define IRDMACQ_SOEVENT_S 54
193 #define IRDMACQ_SOEVENT BIT_ULL(54)
194 #define IRDMACQ_OP_S 56
195 #define IRDMACQ_OP GENMASK_ULL(61, 56)
196 
197 /* Manage Push Page - MPP */
198 #define IRDMA_INVALID_PUSH_PAGE_INDEX_GEN_1 0xffff
199 #define IRDMA_INVALID_PUSH_PAGE_INDEX 0xffffffff
200 
201 #define IRDMAQPSQ_OPCODE_S 32
202 #define IRDMAQPSQ_OPCODE GENMASK_ULL(37, 32)
203 #define IRDMAQPSQ_COPY_HOST_PBL_S 43
204 #define IRDMAQPSQ_COPY_HOST_PBL BIT_ULL(43)
205 #define IRDMAQPSQ_ADDFRAGCNT_S 38
206 #define IRDMAQPSQ_ADDFRAGCNT GENMASK_ULL(41, 38)
207 #define IRDMAQPSQ_PUSHWQE_S 56
208 #define IRDMAQPSQ_PUSHWQE BIT_ULL(56)
209 #define IRDMAQPSQ_STREAMMODE_S 58
210 #define IRDMAQPSQ_STREAMMODE BIT_ULL(58)
211 #define IRDMAQPSQ_WAITFORRCVPDU_S 59
212 #define IRDMAQPSQ_WAITFORRCVPDU BIT_ULL(59)
213 #define IRDMAQPSQ_READFENCE_S 60
214 #define IRDMAQPSQ_READFENCE BIT_ULL(60)
215 #define IRDMAQPSQ_LOCALFENCE_S 61
216 #define IRDMAQPSQ_LOCALFENCE BIT_ULL(61)
217 #define IRDMAQPSQ_UDPHEADER_S 61
218 #define IRDMAQPSQ_UDPHEADER BIT_ULL(61)
219 #define IRDMAQPSQ_L4LEN_S 42
220 #define IRDMAQPSQ_L4LEN GENMASK_ULL(45, 42)
221 #define IRDMAQPSQ_SIGCOMPL_S 62
222 #define IRDMAQPSQ_SIGCOMPL BIT_ULL(62)
223 #define IRDMAQPSQ_VALID_S 63
224 #define IRDMAQPSQ_VALID BIT_ULL(63)
225 
226 #define IRDMAQPSQ_FRAG_TO_S IRDMA_CQPHC_QPCTX_S
227 #define IRDMAQPSQ_FRAG_TO IRDMA_CQPHC_QPCTX
228 #define IRDMAQPSQ_FRAG_VALID_S 63
229 #define IRDMAQPSQ_FRAG_VALID BIT_ULL(63)
230 #define IRDMAQPSQ_FRAG_LEN_S 32
231 #define IRDMAQPSQ_FRAG_LEN GENMASK_ULL(62, 32)
232 #define IRDMAQPSQ_FRAG_STAG_S 0
233 #define IRDMAQPSQ_FRAG_STAG GENMASK_ULL(31, 0)
234 #define IRDMAQPSQ_GEN1_FRAG_LEN_S 0
235 #define IRDMAQPSQ_GEN1_FRAG_LEN GENMASK_ULL(31, 0)
236 #define IRDMAQPSQ_GEN1_FRAG_STAG_S 32
237 #define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32)
238 #define IRDMAQPSQ_REMSTAGINV_S 0
239 #define IRDMAQPSQ_REMSTAGINV GENMASK_ULL(31, 0)
240 #define IRDMAQPSQ_DESTQKEY_S 0
241 #define IRDMAQPSQ_DESTQKEY GENMASK_ULL(31, 0)
242 #define IRDMAQPSQ_DESTQPN_S 32
243 #define IRDMAQPSQ_DESTQPN GENMASK_ULL(55, 32)
244 #define IRDMAQPSQ_AHID_S 0
245 #define IRDMAQPSQ_AHID GENMASK_ULL(16, 0)
246 #define IRDMAQPSQ_INLINEDATAFLAG_S 57
247 #define IRDMAQPSQ_INLINEDATAFLAG BIT_ULL(57)
248 
249 #define IRDMA_INLINE_VALID_S 7
250 #define IRDMAQPSQ_INLINEDATALEN_S 48
251 #define IRDMAQPSQ_INLINEDATALEN GENMASK_ULL(55, 48)
252 #define IRDMAQPSQ_IMMDATAFLAG_S 47
253 #define IRDMAQPSQ_IMMDATAFLAG BIT_ULL(47)
254 #define IRDMAQPSQ_REPORTRTT_S 46
255 #define IRDMAQPSQ_REPORTRTT BIT_ULL(46)
256 
257 #define IRDMAQPSQ_IMMDATA_S 0
258 #define IRDMAQPSQ_IMMDATA GENMASK_ULL(63, 0)
259 #define IRDMAQPSQ_REMSTAG_S 0
260 #define IRDMAQPSQ_REMSTAG GENMASK_ULL(31, 0)
261 
262 #define IRDMAQPSQ_REMTO_S IRDMA_CQPHC_QPCTX_S
263 #define IRDMAQPSQ_REMTO IRDMA_CQPHC_QPCTX
264 
265 #define IRDMAQPSQ_STAGRIGHTS_S 48
266 #define IRDMAQPSQ_STAGRIGHTS GENMASK_ULL(52, 48)
267 #define IRDMAQPSQ_VABASEDTO_S 53
268 #define IRDMAQPSQ_VABASEDTO BIT_ULL(53)
269 #define IRDMAQPSQ_MEMWINDOWTYPE_S 54
270 #define IRDMAQPSQ_MEMWINDOWTYPE BIT_ULL(54)
271 
272 #define IRDMAQPSQ_MWLEN_S IRDMA_CQPHC_QPCTX_S
273 #define IRDMAQPSQ_MWLEN IRDMA_CQPHC_QPCTX
274 #define IRDMAQPSQ_PARENTMRSTAG_S 32
275 #define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32)
276 #define IRDMAQPSQ_MWSTAG_S 0
277 #define IRDMAQPSQ_MWSTAG GENMASK_ULL(31, 0)
278 
279 #define IRDMAQPSQ_BASEVA_TO_FBO_S IRDMA_CQPHC_QPCTX_S
280 #define IRDMAQPSQ_BASEVA_TO_FBO IRDMA_CQPHC_QPCTX
281 
282 #define IRDMAQPSQ_LOCSTAG_S 0
283 #define IRDMAQPSQ_LOCSTAG GENMASK_ULL(31, 0)
284 
285 /* iwarp QP RQ WQE common fields */
286 #define IRDMAQPRQ_ADDFRAGCNT_S IRDMAQPSQ_ADDFRAGCNT_S
287 #define IRDMAQPRQ_ADDFRAGCNT IRDMAQPSQ_ADDFRAGCNT
288 
289 #define IRDMAQPRQ_VALID_S IRDMAQPSQ_VALID_S
290 #define IRDMAQPRQ_VALID IRDMAQPSQ_VALID
291 
292 #define IRDMAQPRQ_COMPLCTX_S IRDMA_CQPHC_QPCTX_S
293 #define IRDMAQPRQ_COMPLCTX IRDMA_CQPHC_QPCTX
294 
295 #define IRDMAQPRQ_FRAG_LEN_S IRDMAQPSQ_FRAG_LEN_S
296 #define IRDMAQPRQ_FRAG_LEN IRDMAQPSQ_FRAG_LEN
297 
298 #define IRDMAQPRQ_STAG_S IRDMAQPSQ_FRAG_STAG_S
299 #define IRDMAQPRQ_STAG IRDMAQPSQ_FRAG_STAG
300 
301 #define IRDMAQPRQ_TO_S IRDMAQPSQ_FRAG_TO_S
302 #define IRDMAQPRQ_TO IRDMAQPSQ_FRAG_TO
303 
304 #define IRDMAPFINT_OICR_HMC_ERR_M BIT(26)
305 #define IRDMAPFINT_OICR_PE_PUSH_M BIT(27)
306 #define IRDMAPFINT_OICR_PE_CRITERR_M BIT(28)
307 
308 #define IRDMA_GET_RING_OFFSET(_ring, _i) \
309 	( \
310 		((_ring).head + (_i)) % (_ring).size \
311 	)
312 
313 #define IRDMA_GET_CQ_ELEM_AT_OFFSET(_cq, _i, _cqe) \
314 	{ \
315 		register __u32 offset; \
316 		offset = IRDMA_GET_RING_OFFSET((_cq)->cq_ring, _i); \
317 		(_cqe) = (_cq)->cq_base[offset].buf; \
318 	}
319 #define IRDMA_GET_CURRENT_CQ_ELEM(_cq) \
320 	( \
321 		(_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf  \
322 	)
323 #define IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(_cq) \
324 	( \
325 		((struct irdma_extended_cqe *) \
326 		((_cq)->cq_base))[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
327 	)
328 
329 #define IRDMA_RING_INIT(_ring, _size) \
330 	{ \
331 		(_ring).head = 0; \
332 		(_ring).tail = 0; \
333 		(_ring).size = (_size); \
334 	}
335 #define IRDMA_RING_SIZE(_ring) ((_ring).size)
336 #define IRDMA_RING_CURRENT_HEAD(_ring) ((_ring).head)
337 #define IRDMA_RING_CURRENT_TAIL(_ring) ((_ring).tail)
338 
339 #define IRDMA_RING_MOVE_HEAD(_ring, _retcode) \
340 	{ \
341 		register u32 size; \
342 		size = (_ring).size;  \
343 		if (!IRDMA_RING_FULL_ERR(_ring)) { \
344 			(_ring).head = ((_ring).head + 1) % size; \
345 			(_retcode) = 0; \
346 		} else { \
347 			(_retcode) = ENOSPC; \
348 		} \
349 	}
350 #define IRDMA_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \
351 	{ \
352 		register u32 size; \
353 		size = (_ring).size; \
354 		if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < size) { \
355 			(_ring).head = ((_ring).head + (_count)) % size; \
356 			(_retcode) = 0; \
357 		} else { \
358 			(_retcode) = ENOSPC; \
359 		} \
360 	}
361 #define IRDMA_SQ_RING_MOVE_HEAD(_ring, _retcode) \
362 	{ \
363 		register u32 size; \
364 		size = (_ring).size;  \
365 		if (!IRDMA_SQ_RING_FULL_ERR(_ring)) { \
366 			(_ring).head = ((_ring).head + 1) % size; \
367 			(_retcode) = 0; \
368 		} else { \
369 			(_retcode) = ENOSPC; \
370 		} \
371 	}
372 #define IRDMA_SQ_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \
373 	{ \
374 		register u32 size; \
375 		size = (_ring).size; \
376 		if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \
377 			(_ring).head = ((_ring).head + (_count)) % size; \
378 			(_retcode) = 0; \
379 		} else { \
380 			(_retcode) = ENOSPC; \
381 		} \
382 	}
383 #define IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(_ring, _count) \
384 	(_ring).head = ((_ring).head + (_count)) % (_ring).size
385 
386 #define IRDMA_RING_MOVE_TAIL(_ring) \
387 	(_ring).tail = ((_ring).tail + 1) % (_ring).size
388 
389 #define IRDMA_RING_MOVE_HEAD_NOCHECK(_ring) \
390 	(_ring).head = ((_ring).head + 1) % (_ring).size
391 
392 #define IRDMA_RING_MOVE_TAIL_BY_COUNT(_ring, _count) \
393 	(_ring).tail = ((_ring).tail + (_count)) % (_ring).size
394 
395 #define IRDMA_RING_SET_TAIL(_ring, _pos) \
396 	(_ring).tail = (_pos) % (_ring).size
397 
398 #define IRDMA_RING_FULL_ERR(_ring) \
399 	( \
400 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 1))  \
401 	)
402 
403 #define IRDMA_ERR_RING_FULL2(_ring) \
404 	( \
405 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 2))  \
406 	)
407 
408 #define IRDMA_ERR_RING_FULL3(_ring) \
409 	( \
410 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 3))  \
411 	)
412 
413 #define IRDMA_SQ_RING_FULL_ERR(_ring) \
414 	( \
415 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 257))  \
416 	)
417 
418 #define IRDMA_ERR_SQ_RING_FULL2(_ring) \
419 	( \
420 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 258))  \
421 	)
422 #define IRDMA_ERR_SQ_RING_FULL3(_ring) \
423 	( \
424 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 259))  \
425 	)
426 #define IRDMA_RING_MORE_WORK(_ring) \
427 	( \
428 		(IRDMA_RING_USED_QUANTA(_ring) != 0) \
429 	)
430 
431 #define IRDMA_RING_USED_QUANTA(_ring) \
432 	( \
433 		(((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \
434 	)
435 
436 #define IRDMA_RING_FREE_QUANTA(_ring) \
437 	( \
438 		((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 1) \
439 	)
440 
441 #define IRDMA_SQ_RING_FREE_QUANTA(_ring) \
442 	( \
443 		((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 257) \
444 	)
445 
446 #define IRDMA_ATOMIC_RING_MOVE_HEAD(_ring, index, _retcode) \
447 	{ \
448 		index = IRDMA_RING_CURRENT_HEAD(_ring); \
449 		IRDMA_RING_MOVE_HEAD(_ring, _retcode); \
450 	}
451 
452 enum irdma_qp_wqe_size {
453 	IRDMA_WQE_SIZE_32  = 32,
454 	IRDMA_WQE_SIZE_64  = 64,
455 	IRDMA_WQE_SIZE_96  = 96,
456 	IRDMA_WQE_SIZE_128 = 128,
457 	IRDMA_WQE_SIZE_256 = 256,
458 };
459 
460 /**
461  * set_64bit_val - set 64 bit value to hw wqe
462  * @wqe_words: wqe addr to write
463  * @byte_index: index in wqe
464  * @val: value to write
465  **/
466 static inline void set_64bit_val(__le64 *wqe_words, u32 byte_index, u64 val)
467 {
468 	wqe_words[byte_index >> 3] = htole64(val);
469 }
470 
471 /**
472  * set_32bit_val - set 32 bit value to hw wqe
473  * @wqe_words: wqe addr to write
474  * @byte_index: index in wqe
475  * @val: value to write
476  **/
477 static inline void set_32bit_val(__le32 *wqe_words, u32 byte_index, u32 val)
478 {
479 	wqe_words[byte_index >> 2] = htole32(val);
480 }
481 
482 /**
483  * get_64bit_val - read 64 bit value from wqe
484  * @wqe_words: wqe addr
485  * @byte_index: index to read from
486  * @val: read value
487  **/
488 static inline void get_64bit_val(__le64 *wqe_words, u32 byte_index, u64 *val)
489 {
490 	*val = le64toh(wqe_words[byte_index >> 3]);
491 }
492 
493 /**
494  * get_32bit_val - read 32 bit value from wqe
495  * @wqe_words: wqe addr
496  * @byte_index: index to reaad from
497  * @val: return 32 bit value
498  **/
499 static inline void get_32bit_val(__le32 *wqe_words, u32 byte_index, u32 *val)
500 {
501 	*val = le32toh(wqe_words[byte_index >> 2]);
502 }
503 #endif /* IRDMA_DEFS_H */
504