xref: /freebsd/contrib/ofed/libirdma/irdma_defs.h (revision 643ac419fafba89f5adda0e0ea75b538727453fb)
1 /*-
2  * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
3  *
4  * Copyright (c) 2015 - 2021 Intel Corporation
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenFabrics.org BSD license below:
11  *
12  *   Redistribution and use in source and binary forms, with or
13  *   without modification, are permitted provided that the following
14  *   conditions are met:
15  *
16  *    - Redistributions of source code must retain the above
17  *	copyright notice, this list of conditions and the following
18  *	disclaimer.
19  *
20  *    - Redistributions in binary form must reproduce the above
21  *	copyright notice, this list of conditions and the following
22  *	disclaimer in the documentation and/or other materials
23  *	provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  */
34 /*$FreeBSD$*/
35 
36 #ifndef IRDMA_DEFS_H
37 #define IRDMA_DEFS_H
38 
39 #define IRDMA_BYTE_0		0
40 #define IRDMA_BYTE_8		8
41 #define IRDMA_BYTE_16		16
42 #define IRDMA_BYTE_24		24
43 #define IRDMA_BYTE_32		32
44 #define IRDMA_BYTE_40		40
45 #define IRDMA_BYTE_48		48
46 #define IRDMA_BYTE_56		56
47 #define IRDMA_BYTE_64		64
48 #define IRDMA_BYTE_72		72
49 #define IRDMA_BYTE_80		80
50 #define IRDMA_BYTE_88		88
51 #define IRDMA_BYTE_96		96
52 #define IRDMA_BYTE_104		104
53 #define IRDMA_BYTE_112		112
54 #define IRDMA_BYTE_120		120
55 #define IRDMA_BYTE_128		128
56 #define IRDMA_BYTE_136		136
57 #define IRDMA_BYTE_144		144
58 #define IRDMA_BYTE_152		152
59 #define IRDMA_BYTE_160		160
60 #define IRDMA_BYTE_168		168
61 #define IRDMA_BYTE_176		176
62 #define IRDMA_BYTE_184		184
63 #define IRDMA_BYTE_192		192
64 #define IRDMA_BYTE_200		200
65 #define IRDMA_BYTE_208		208
66 #define IRDMA_BYTE_216		216
67 
68 #define IRDMA_QP_TYPE_IWARP	1
69 #define IRDMA_QP_TYPE_UDA	2
70 #define IRDMA_QP_TYPE_ROCE_RC	3
71 #define IRDMA_QP_TYPE_ROCE_UD	4
72 
73 #define IRDMA_HW_PAGE_SIZE	4096
74 #define IRDMA_HW_PAGE_SHIFT	12
75 #define IRDMA_CQE_QTYPE_RQ	0
76 #define IRDMA_CQE_QTYPE_SQ	1
77 
78 #define IRDMA_QP_SW_MIN_WQSIZE	8u /* in WRs*/
79 #define IRDMA_QP_WQE_MIN_SIZE	32
80 #define IRDMA_QP_WQE_MAX_SIZE	256
81 #define IRDMA_QP_WQE_MIN_QUANTA 1
82 #define IRDMA_MAX_RQ_WQE_SHIFT_GEN1 2
83 #define IRDMA_MAX_RQ_WQE_SHIFT_GEN2 3
84 
85 #define IRDMA_SQ_RSVD	258
86 #define IRDMA_RQ_RSVD	1
87 
88 #define IRDMA_FEATURE_RTS_AE			1ULL
89 #define IRDMA_FEATURE_CQ_RESIZE			2ULL
90 #define IRDMA_FEATURE_RELAX_RQ_ORDER		4ULL
91 #define IRDMAQP_OP_RDMA_WRITE			0x00
92 #define IRDMAQP_OP_RDMA_READ			0x01
93 #define IRDMAQP_OP_RDMA_SEND			0x03
94 #define IRDMAQP_OP_RDMA_SEND_INV		0x04
95 #define IRDMAQP_OP_RDMA_SEND_SOL_EVENT		0x05
96 #define IRDMAQP_OP_RDMA_SEND_SOL_EVENT_INV	0x06
97 #define IRDMAQP_OP_BIND_MW			0x08
98 #define IRDMAQP_OP_FAST_REGISTER		0x09
99 #define IRDMAQP_OP_LOCAL_INVALIDATE		0x0a
100 #define IRDMAQP_OP_RDMA_READ_LOC_INV		0x0b
101 #define IRDMAQP_OP_NOP				0x0c
102 
103 #ifndef LS_64_1
104 #define LS_64_1(val, bits)	((u64)(uintptr_t)(val) << (bits))
105 #define RS_64_1(val, bits)	((u64)(uintptr_t)(val) >> (bits))
106 #define LS_32_1(val, bits)	((u32)((val) << (bits)))
107 #define RS_32_1(val, bits)	((u32)((val) >> (bits)))
108 #endif
109 #define LS_64(val, field)	(((u64)(val) << field ## _S) & (field ## _M))
110 #define RS_64(val, field)	((u64)((val) & field ## _M) >> field ## _S)
111 #define LS_32(val, field)	(((val) << field ## _S) & (field ## _M))
112 #define RS_32(val, field)	(((val) & field ## _M) >> field ## _S)
113 
114 #define IRDMA_CQPHC_QPCTX_S 0
115 #define IRDMA_CQPHC_QPCTX_M \
116 	(0xffffffffffffffffULL << IRDMA_CQPHC_QPCTX_S)
117 
118 /* iWARP QP Doorbell shadow area */
119 #define IRDMA_QP_DBSA_HW_SQ_TAIL_S 0
120 #define IRDMA_QP_DBSA_HW_SQ_TAIL_M \
121 	(0x7fffULL << IRDMA_QP_DBSA_HW_SQ_TAIL_S)
122 
123 /* Completion Queue Doorbell shadow area */
124 #define IRDMA_CQ_DBSA_CQEIDX_S 0
125 #define IRDMA_CQ_DBSA_CQEIDX_M (0xfffffULL << IRDMA_CQ_DBSA_CQEIDX_S)
126 
127 #define IRDMA_CQ_DBSA_SW_CQ_SELECT_S 0
128 #define IRDMA_CQ_DBSA_SW_CQ_SELECT_M \
129 	(0x3fffULL << IRDMA_CQ_DBSA_SW_CQ_SELECT_S)
130 
131 #define IRDMA_CQ_DBSA_ARM_NEXT_S 14
132 #define IRDMA_CQ_DBSA_ARM_NEXT_M BIT_ULL(IRDMA_CQ_DBSA_ARM_NEXT_S)
133 
134 #define IRDMA_CQ_DBSA_ARM_NEXT_SE_S 15
135 #define IRDMA_CQ_DBSA_ARM_NEXT_SE_M BIT_ULL(IRDMA_CQ_DBSA_ARM_NEXT_SE_S)
136 
137 #define IRDMA_CQ_DBSA_ARM_SEQ_NUM_S 16
138 #define IRDMA_CQ_DBSA_ARM_SEQ_NUM_M \
139 	(0x3ULL << IRDMA_CQ_DBSA_ARM_SEQ_NUM_S)
140 
141 /* CQP and iWARP Completion Queue */
142 #define IRDMA_CQ_QPCTX_S IRDMA_CQPHC_QPCTX_S
143 #define IRDMA_CQ_QPCTX_M IRDMA_CQPHC_QPCTX_M
144 
145 #define IRDMA_CQ_MINERR_S 0
146 #define IRDMA_CQ_MINERR_M (0xffffULL << IRDMA_CQ_MINERR_S)
147 
148 #define IRDMA_CQ_MAJERR_S 16
149 #define IRDMA_CQ_MAJERR_M (0xffffULL << IRDMA_CQ_MAJERR_S)
150 
151 #define IRDMA_CQ_WQEIDX_S 32
152 #define IRDMA_CQ_WQEIDX_M (0x7fffULL << IRDMA_CQ_WQEIDX_S)
153 
154 #define IRDMA_CQ_EXTCQE_S 50
155 #define IRDMA_CQ_EXTCQE_M BIT_ULL(IRDMA_CQ_EXTCQE_S)
156 
157 #define IRDMA_OOO_CMPL_S 54
158 #define IRDMA_OOO_CMPL_M BIT_ULL(IRDMA_OOO_CMPL_S)
159 
160 #define IRDMA_CQ_ERROR_S 55
161 #define IRDMA_CQ_ERROR_M BIT_ULL(IRDMA_CQ_ERROR_S)
162 
163 #define IRDMA_CQ_SQ_S 62
164 #define IRDMA_CQ_SQ_M BIT_ULL(IRDMA_CQ_SQ_S)
165 
166 #define IRDMA_CQ_VALID_S 63
167 #define IRDMA_CQ_VALID_M BIT_ULL(IRDMA_CQ_VALID_S)
168 
169 #define IRDMA_CQ_IMMVALID_S 62
170 #define IRDMA_CQ_IMMVALID_M BIT_ULL(IRDMA_CQ_IMMVALID_S)
171 
172 #define IRDMA_CQ_UDSMACVALID_S 61
173 #define IRDMA_CQ_UDSMACVALID_M BIT_ULL(IRDMA_CQ_UDSMACVALID_S)
174 
175 #define IRDMA_CQ_UDVLANVALID_S 60
176 #define IRDMA_CQ_UDVLANVALID_M BIT_ULL(IRDMA_CQ_UDVLANVALID_S)
177 
178 #define IRDMA_CQ_UDSMAC_S 0
179 #define IRDMA_CQ_UDSMAC_M (0xffffffffffffULL << IRDMA_CQ_UDSMAC_S)
180 
181 #define IRDMA_CQ_UDVLAN_S 48
182 #define IRDMA_CQ_UDVLAN_M (0xffffULL << IRDMA_CQ_UDVLAN_S)
183 
184 #define IRDMA_CQ_IMMDATA_S 0
185 #define IRDMA_CQ_IMMDATA_M (0xffffffffffffffffULL << IRDMA_CQ_IMMVALID_S)
186 
187 #define IRDMA_CQ_IMMDATALOW32_S 0
188 #define IRDMA_CQ_IMMDATALOW32_M (0xffffffffULL << IRDMA_CQ_IMMDATALOW32_S)
189 
190 #define IRDMA_CQ_IMMDATAUP32_S 32
191 #define IRDMA_CQ_IMMDATAUP32_M (0xffffffffULL << IRDMA_CQ_IMMDATAUP32_S)
192 
193 #define IRDMACQ_PAYLDLEN_S 0
194 #define IRDMACQ_PAYLDLEN_M (0xffffffffULL << IRDMACQ_PAYLDLEN_S)
195 
196 #define IRDMACQ_TCPSEQNUMRTT_S 32
197 #define IRDMACQ_TCPSEQNUMRTT_M (0xffffffffULL << IRDMACQ_TCPSEQNUMRTT_S)
198 
199 #define IRDMACQ_INVSTAG_S 0
200 #define IRDMACQ_INVSTAG_M (0xffffffffULL << IRDMACQ_INVSTAG_S)
201 
202 #define IRDMACQ_QPID_S 32
203 #define IRDMACQ_QPID_M (0xffffffULL << IRDMACQ_QPID_S)
204 
205 #define IRDMACQ_UDSRCQPN_S 0
206 #define IRDMACQ_UDSRCQPN_M (0xffffffffULL << IRDMACQ_UDSRCQPN_S)
207 
208 #define IRDMACQ_PSHDROP_S 51
209 #define IRDMACQ_PSHDROP_M BIT_ULL(IRDMACQ_PSHDROP_S)
210 
211 #define IRDMACQ_STAG_S 53
212 #define IRDMACQ_STAG_M BIT_ULL(IRDMACQ_STAG_S)
213 
214 #define IRDMACQ_IPV4_S 53
215 #define IRDMACQ_IPV4_M BIT_ULL(IRDMACQ_IPV4_S)
216 
217 #define IRDMACQ_SOEVENT_S 54
218 #define IRDMACQ_SOEVENT_M BIT_ULL(IRDMACQ_SOEVENT_S)
219 
220 #define IRDMACQ_OP_S 56
221 #define IRDMACQ_OP_M (0x3fULL << IRDMACQ_OP_S)
222 
223 /* Manage Push Page - MPP */
224 #define IRDMA_INVALID_PUSH_PAGE_INDEX_GEN_1 0xffff
225 #define IRDMA_INVALID_PUSH_PAGE_INDEX 0xffffffff
226 
227 /* iwarp QP SQ WQE common fields */
228 #define IRDMAQPSQ_OPCODE_S 32
229 #define IRDMAQPSQ_OPCODE_M (0x3fULL << IRDMAQPSQ_OPCODE_S)
230 
231 #define IRDMAQPSQ_COPY_HOST_PBL_S 43
232 #define IRDMAQPSQ_COPY_HOST_PBL_M BIT_ULL(IRDMAQPSQ_COPY_HOST_PBL_S)
233 
234 #define IRDMAQPSQ_ADDFRAGCNT_S 38
235 #define IRDMAQPSQ_ADDFRAGCNT_M (0xfULL << IRDMAQPSQ_ADDFRAGCNT_S)
236 
237 #define IRDMAQPSQ_PUSHWQE_S 56
238 #define IRDMAQPSQ_PUSHWQE_M BIT_ULL(IRDMAQPSQ_PUSHWQE_S)
239 
240 #define IRDMAQPSQ_STREAMMODE_S 58
241 #define IRDMAQPSQ_STREAMMODE_M BIT_ULL(IRDMAQPSQ_STREAMMODE_S)
242 
243 #define IRDMAQPSQ_WAITFORRCVPDU_S 59
244 #define IRDMAQPSQ_WAITFORRCVPDU_M BIT_ULL(IRDMAQPSQ_WAITFORRCVPDU_S)
245 
246 #define IRDMAQPSQ_READFENCE_S 60
247 #define IRDMAQPSQ_READFENCE_M BIT_ULL(IRDMAQPSQ_READFENCE_S)
248 
249 #define IRDMAQPSQ_LOCALFENCE_S 61
250 #define IRDMAQPSQ_LOCALFENCE_M BIT_ULL(IRDMAQPSQ_LOCALFENCE_S)
251 
252 #define IRDMAQPSQ_UDPHEADER_S 61
253 #define IRDMAQPSQ_UDPHEADER_M BIT_ULL(IRDMAQPSQ_UDPHEADER_S)
254 
255 #define IRDMAQPSQ_L4LEN_S 42
256 #define IRDMAQPSQ_L4LEN_M ((u64)0xF << IRDMAQPSQ_L4LEN_S)
257 
258 #define IRDMAQPSQ_SIGCOMPL_S 62
259 #define IRDMAQPSQ_SIGCOMPL_M BIT_ULL(IRDMAQPSQ_SIGCOMPL_S)
260 
261 #define IRDMAQPSQ_VALID_S 63
262 #define IRDMAQPSQ_VALID_M BIT_ULL(IRDMAQPSQ_VALID_S)
263 
264 #define IRDMAQPSQ_FRAG_TO_S IRDMA_CQPHC_QPCTX_S
265 #define IRDMAQPSQ_FRAG_TO_M IRDMA_CQPHC_QPCTX_M
266 
267 #define IRDMAQPSQ_FRAG_VALID_S 63
268 #define IRDMAQPSQ_FRAG_VALID_M BIT_ULL(IRDMAQPSQ_FRAG_VALID_S)
269 
270 #define IRDMAQPSQ_FRAG_LEN_S 32
271 #define IRDMAQPSQ_FRAG_LEN_M (0x7fffffffULL << IRDMAQPSQ_FRAG_LEN_S)
272 
273 #define IRDMAQPSQ_FRAG_STAG_S 0
274 #define IRDMAQPSQ_FRAG_STAG_M (0xffffffffULL << IRDMAQPSQ_FRAG_STAG_S)
275 
276 #define IRDMAQPSQ_GEN1_FRAG_LEN_S 0
277 #define IRDMAQPSQ_GEN1_FRAG_LEN_M (0xffffffffULL << IRDMAQPSQ_GEN1_FRAG_LEN_S)
278 
279 #define IRDMAQPSQ_GEN1_FRAG_STAG_S 32
280 #define IRDMAQPSQ_GEN1_FRAG_STAG_M (0xffffffffULL << IRDMAQPSQ_GEN1_FRAG_STAG_S)
281 
282 #define IRDMAQPSQ_REMSTAGINV_S 0
283 #define IRDMAQPSQ_REMSTAGINV_M (0xffffffffULL << IRDMAQPSQ_REMSTAGINV_S)
284 
285 #define IRDMAQPSQ_DESTQKEY_S 0
286 #define IRDMAQPSQ_DESTQKEY_M (0xffffffffULL << IRDMAQPSQ_DESTQKEY_S)
287 
288 #define IRDMAQPSQ_DESTQPN_S 32
289 #define IRDMAQPSQ_DESTQPN_M (0x00ffffffULL << IRDMAQPSQ_DESTQPN_S)
290 
291 #define IRDMAQPSQ_AHID_S 0
292 #define IRDMAQPSQ_AHID_M (0x0001ffffULL << IRDMAQPSQ_AHID_S)
293 
294 #define IRDMAQPSQ_INLINEDATAFLAG_S 57
295 #define IRDMAQPSQ_INLINEDATAFLAG_M BIT_ULL(IRDMAQPSQ_INLINEDATAFLAG_S)
296 
297 #define IRDMA_INLINE_VALID_S 7
298 
299 #define IRDMAQPSQ_INLINEDATALEN_S 48
300 #define IRDMAQPSQ_INLINEDATALEN_M \
301 	(0xffULL << IRDMAQPSQ_INLINEDATALEN_S)
302 #define IRDMAQPSQ_IMMDATAFLAG_S 47
303 #define IRDMAQPSQ_IMMDATAFLAG_M \
304 	BIT_ULL(IRDMAQPSQ_IMMDATAFLAG_S)
305 #define IRDMAQPSQ_REPORTRTT_S 46
306 #define IRDMAQPSQ_REPORTRTT_M \
307 	BIT_ULL(IRDMAQPSQ_REPORTRTT_S)
308 
309 #define IRDMAQPSQ_IMMDATA_S 0
310 #define IRDMAQPSQ_IMMDATA_M \
311 	(0xffffffffffffffffULL << IRDMAQPSQ_IMMDATA_S)
312 
313 /* rdma write */
314 #define IRDMAQPSQ_REMSTAG_S 0
315 #define IRDMAQPSQ_REMSTAG_M (0xffffffffULL << IRDMAQPSQ_REMSTAG_S)
316 
317 #define IRDMAQPSQ_REMTO_S IRDMA_CQPHC_QPCTX_S
318 #define IRDMAQPSQ_REMTO_M IRDMA_CQPHC_QPCTX_M
319 
320 /* memory window */
321 #define IRDMAQPSQ_STAGRIGHTS_S 48
322 #define IRDMAQPSQ_STAGRIGHTS_M (0x1fULL << IRDMAQPSQ_STAGRIGHTS_S)
323 
324 #define IRDMAQPSQ_VABASEDTO_S 53
325 #define IRDMAQPSQ_VABASEDTO_M BIT_ULL(IRDMAQPSQ_VABASEDTO_S)
326 
327 #define IRDMAQPSQ_MEMWINDOWTYPE_S 54
328 #define IRDMAQPSQ_MEMWINDOWTYPE_M BIT_ULL(IRDMAQPSQ_MEMWINDOWTYPE_S)
329 
330 #define IRDMAQPSQ_MWLEN_S IRDMA_CQPHC_QPCTX_S
331 #define IRDMAQPSQ_MWLEN_M IRDMA_CQPHC_QPCTX_M
332 
333 #define IRDMAQPSQ_PARENTMRSTAG_S 32
334 #define IRDMAQPSQ_PARENTMRSTAG_M \
335 	(0xffffffffULL << IRDMAQPSQ_PARENTMRSTAG_S)
336 
337 #define IRDMAQPSQ_MWSTAG_S 0
338 #define IRDMAQPSQ_MWSTAG_M (0xffffffffULL << IRDMAQPSQ_MWSTAG_S)
339 
340 #define IRDMAQPSQ_BASEVA_TO_FBO_S IRDMA_CQPHC_QPCTX_S
341 #define IRDMAQPSQ_BASEVA_TO_FBO_M IRDMA_CQPHC_QPCTX_M
342 
343 /* Local Invalidate */
344 #define IRDMAQPSQ_LOCSTAG_S 0
345 #define IRDMAQPSQ_LOCSTAG_M (0xffffffffULL << IRDMAQPSQ_LOCSTAG_S)
346 
347 /* iwarp QP RQ WQE common fields */
348 #define IRDMAQPRQ_ADDFRAGCNT_S IRDMAQPSQ_ADDFRAGCNT_S
349 #define IRDMAQPRQ_ADDFRAGCNT_M IRDMAQPSQ_ADDFRAGCNT_M
350 
351 #define IRDMAQPRQ_VALID_S IRDMAQPSQ_VALID_S
352 #define IRDMAQPRQ_VALID_M IRDMAQPSQ_VALID_M
353 
354 #define IRDMAQPRQ_COMPLCTX_S IRDMA_CQPHC_QPCTX_S
355 #define IRDMAQPRQ_COMPLCTX_M IRDMA_CQPHC_QPCTX_M
356 
357 #define IRDMAQPRQ_FRAG_LEN_S IRDMAQPSQ_FRAG_LEN_S
358 #define IRDMAQPRQ_FRAG_LEN_M IRDMAQPSQ_FRAG_LEN_M
359 
360 #define IRDMAQPRQ_STAG_S IRDMAQPSQ_FRAG_STAG_S
361 #define IRDMAQPRQ_STAG_M IRDMAQPSQ_FRAG_STAG_M
362 
363 #define IRDMAQPRQ_TO_S IRDMAQPSQ_FRAG_TO_S
364 #define IRDMAQPRQ_TO_M IRDMAQPSQ_FRAG_TO_M
365 
366 #define IRDMAPFINT_OICR_HMC_ERR_M BIT(26)
367 #define IRDMAPFINT_OICR_PE_PUSH_M BIT(27)
368 #define IRDMAPFINT_OICR_PE_CRITERR_M BIT(28)
369 
370 #define IRDMA_GET_CURRENT_CQ_ELEM(_cq) \
371 	( \
372 		(_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf  \
373 	)
374 #define IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(_cq) \
375 	( \
376 		((struct irdma_extended_cqe *) \
377 		((_cq)->cq_base))[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
378 	)
379 
380 #define IRDMA_RING_INIT(_ring, _size) \
381 	{ \
382 		(_ring).head = 0; \
383 		(_ring).tail = 0; \
384 		(_ring).size = (_size); \
385 	}
386 #define IRDMA_RING_SIZE(_ring) ((_ring).size)
387 #define IRDMA_RING_CURRENT_HEAD(_ring) ((_ring).head)
388 #define IRDMA_RING_CURRENT_TAIL(_ring) ((_ring).tail)
389 
390 #define IRDMA_RING_MOVE_HEAD(_ring, _retcode) \
391 	{ \
392 		register u32 size; \
393 		size = (_ring).size;  \
394 		if (!IRDMA_RING_FULL_ERR(_ring)) { \
395 			(_ring).head = ((_ring).head + 1) % size; \
396 			(_retcode) = 0; \
397 		} else { \
398 			(_retcode) = ENOSPC; \
399 		} \
400 	}
401 #define IRDMA_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \
402 	{ \
403 		register u32 size; \
404 		size = (_ring).size; \
405 		if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < size) { \
406 			(_ring).head = ((_ring).head + (_count)) % size; \
407 			(_retcode) = 0; \
408 		} else { \
409 			(_retcode) = ENOSPC; \
410 		} \
411 	}
412 #define IRDMA_SQ_RING_MOVE_HEAD(_ring, _retcode) \
413 	{ \
414 		register u32 size; \
415 		size = (_ring).size;  \
416 		if (!IRDMA_SQ_RING_FULL_ERR(_ring)) { \
417 			(_ring).head = ((_ring).head + 1) % size; \
418 			(_retcode) = 0; \
419 		} else { \
420 			(_retcode) = ENOSPC; \
421 		} \
422 	}
423 #define IRDMA_SQ_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \
424 	{ \
425 		register u32 size; \
426 		size = (_ring).size; \
427 		if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \
428 			(_ring).head = ((_ring).head + (_count)) % size; \
429 			(_retcode) = 0; \
430 		} else { \
431 			(_retcode) = ENOSPC; \
432 		} \
433 	}
434 #define IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(_ring, _count) \
435 	(_ring).head = ((_ring).head + (_count)) % (_ring).size
436 
437 #define IRDMA_RING_MOVE_TAIL(_ring) \
438 	(_ring).tail = ((_ring).tail + 1) % (_ring).size
439 
440 #define IRDMA_RING_MOVE_HEAD_NOCHECK(_ring) \
441 	(_ring).head = ((_ring).head + 1) % (_ring).size
442 
443 #define IRDMA_RING_MOVE_TAIL_BY_COUNT(_ring, _count) \
444 	(_ring).tail = ((_ring).tail + (_count)) % (_ring).size
445 
446 #define IRDMA_RING_SET_TAIL(_ring, _pos) \
447 	(_ring).tail = (_pos) % (_ring).size
448 
449 #define IRDMA_RING_FULL_ERR(_ring) \
450 	( \
451 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 1))  \
452 	)
453 
454 #define IRDMA_ERR_RING_FULL2(_ring) \
455 	( \
456 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 2))  \
457 	)
458 
459 #define IRDMA_ERR_RING_FULL3(_ring) \
460 	( \
461 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 3))  \
462 	)
463 
464 #define IRDMA_SQ_RING_FULL_ERR(_ring) \
465 	( \
466 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 257))  \
467 	)
468 
469 #define IRDMA_ERR_SQ_RING_FULL2(_ring) \
470 	( \
471 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 258))  \
472 	)
473 #define IRDMA_ERR_SQ_RING_FULL3(_ring) \
474 	( \
475 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 259))  \
476 	)
477 #define IRDMA_RING_MORE_WORK(_ring) \
478 	( \
479 		(IRDMA_RING_USED_QUANTA(_ring) != 0) \
480 	)
481 
482 #define IRDMA_RING_USED_QUANTA(_ring) \
483 	( \
484 		(((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \
485 	)
486 
487 #define IRDMA_RING_FREE_QUANTA(_ring) \
488 	( \
489 		((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 1) \
490 	)
491 
492 #define IRDMA_SQ_RING_FREE_QUANTA(_ring) \
493 	( \
494 		((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 257) \
495 	)
496 
497 #define IRDMA_ATOMIC_RING_MOVE_HEAD(_ring, index, _retcode) \
498 	{ \
499 		index = IRDMA_RING_CURRENT_HEAD(_ring); \
500 		IRDMA_RING_MOVE_HEAD(_ring, _retcode); \
501 	}
502 
503 enum irdma_qp_wqe_size {
504 	IRDMA_WQE_SIZE_32  = 32,
505 	IRDMA_WQE_SIZE_64  = 64,
506 	IRDMA_WQE_SIZE_96  = 96,
507 	IRDMA_WQE_SIZE_128 = 128,
508 	IRDMA_WQE_SIZE_256 = 256,
509 };
510 
511 /**
512  * set_64bit_val - set 64 bit value to hw wqe
513  * @wqe_words: wqe addr to write
514  * @byte_index: index in wqe
515  * @val: value to write
516  **/
517 static inline void set_64bit_val(__le64 *wqe_words, u32 byte_index, u64 val)
518 {
519 	wqe_words[byte_index >> 3] = htole64(val);
520 }
521 
522 /**
523  * set_32bit_val - set 32 bit value to hw wqe
524  * @wqe_words: wqe addr to write
525  * @byte_index: index in wqe
526  * @val: value to write
527  **/
528 static inline void set_32bit_val(__le32 *wqe_words, u32 byte_index, u32 val)
529 {
530 	wqe_words[byte_index >> 2] = htole32(val);
531 }
532 
533 /**
534  * get_64bit_val - read 64 bit value from wqe
535  * @wqe_words: wqe addr
536  * @byte_index: index to read from
537  * @val: read value
538  **/
539 static inline void get_64bit_val(__le64 *wqe_words, u32 byte_index, u64 *val)
540 {
541 	*val = le64toh(wqe_words[byte_index >> 3]);
542 }
543 
544 /**
545  * get_32bit_val - read 32 bit value from wqe
546  * @wqe_words: wqe addr
547  * @byte_index: index to reaad from
548  * @val: return 32 bit value
549  **/
550 static inline void get_32bit_val(__le32 *wqe_words, u32 byte_index, u32 *val)
551 {
552 	*val = le32toh(wqe_words[byte_index >> 2]);
553 }
554 #endif /* IRDMA_DEFS_H */
555