1//===-- X86InstrExtension.td - Sign and Zero Extensions ----*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the sign and zero extension operations. 10// 11//===----------------------------------------------------------------------===// 12 13let hasSideEffects = 0 in { 14 let Defs = [AX], Uses = [AL] in // AX = signext(AL) 15 def CBW : I<0x98, RawFrm, (outs), (ins), 16 "{cbtw|cbw}", []>, OpSize16, Sched<[WriteALU]>; 17 let Defs = [EAX], Uses = [AX] in // EAX = signext(AX) 18 def CWDE : I<0x98, RawFrm, (outs), (ins), 19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>; 20 21 let Defs = [AX,DX], Uses = [AX] in // DX:AX = signext(AX) 22 def CWD : I<0x99, RawFrm, (outs), (ins), 23 "{cwtd|cwd}", []>, OpSize16, Sched<[WriteALU]>; 24 let Defs = [EAX,EDX], Uses = [EAX] in // EDX:EAX = signext(EAX) 25 def CDQ : I<0x99, RawFrm, (outs), (ins), 26 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>; 27 28 29 let Defs = [RAX], Uses = [EAX] in // RAX = signext(EAX) 30 def CDQE : RI<0x98, RawFrm, (outs), (ins), 31 "{cltq|cdqe}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>; 32 33 let Defs = [RAX,RDX], Uses = [RAX] in // RDX:RAX = signext(RAX) 34 def CQO : RI<0x99, RawFrm, (outs), (ins), 35 "{cqto|cqo}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>; 36} 37 38// Sign/Zero extenders 39let hasSideEffects = 0 in { 40def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src), 41 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, 42 TB, OpSize16, Sched<[WriteALU]>; 43let mayLoad = 1 in 44def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src), 45 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, 46 TB, OpSize16, Sched<[WriteALULd]>; 47} // hasSideEffects = 0 48def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src), 49 "movs{bl|x}\t{$src, $dst|$dst, $src}", 50 [(set GR32:$dst, (sext GR8:$src))]>, TB, 51 OpSize32, Sched<[WriteALU]>; 52def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), 53 "movs{bl|x}\t{$src, $dst|$dst, $src}", 54 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB, 55 OpSize32, Sched<[WriteALULd]>; 56def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), 57 "movs{wl|x}\t{$src, $dst|$dst, $src}", 58 [(set GR32:$dst, (sext GR16:$src))]>, TB, 59 OpSize32, Sched<[WriteALU]>; 60def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), 61 "movs{wl|x}\t{$src, $dst|$dst, $src}", 62 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, 63 OpSize32, TB, Sched<[WriteALULd]>; 64 65let hasSideEffects = 0 in { 66def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src), 67 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, 68 TB, OpSize16, Sched<[WriteALU]>; 69let mayLoad = 1 in 70def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src), 71 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, 72 TB, OpSize16, Sched<[WriteALULd]>; 73} // hasSideEffects = 0 74def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), 75 "movz{bl|x}\t{$src, $dst|$dst, $src}", 76 [(set GR32:$dst, (zext GR8:$src))]>, TB, 77 OpSize32, Sched<[WriteALU]>; 78def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), 79 "movz{bl|x}\t{$src, $dst|$dst, $src}", 80 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB, 81 OpSize32, Sched<[WriteALULd]>; 82def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), 83 "movz{wl|x}\t{$src, $dst|$dst, $src}", 84 [(set GR32:$dst, (zext GR16:$src))]>, TB, 85 OpSize32, Sched<[WriteALU]>; 86def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), 87 "movz{wl|x}\t{$src, $dst|$dst, $src}", 88 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, 89 TB, OpSize32, Sched<[WriteALULd]>; 90 91// These instructions exist as a consequence of operand size prefix having 92// control of the destination size, but not the input size. Only support them 93// for the disassembler. 94let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 95def MOVSX16rr16: I<0xBF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 96 "movs{ww|x}\t{$src, $dst|$dst, $src}", 97 []>, TB, OpSize16, Sched<[WriteALU]>, NotMemoryFoldable; 98def MOVZX16rr16: I<0xB7, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 99 "movz{ww|x}\t{$src, $dst|$dst, $src}", 100 []>, TB, OpSize16, Sched<[WriteALU]>, NotMemoryFoldable; 101let mayLoad = 1 in { 102def MOVSX16rm16: I<0xBF, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 103 "movs{ww|x}\t{$src, $dst|$dst, $src}", 104 []>, OpSize16, TB, Sched<[WriteALULd]>, NotMemoryFoldable; 105def MOVZX16rm16: I<0xB7, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 106 "movz{ww|x}\t{$src, $dst|$dst, $src}", 107 []>, TB, OpSize16, Sched<[WriteALULd]>, NotMemoryFoldable; 108} // mayLoad = 1 109} // isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 110 111// These are the same as the regular MOVZX32rr8 and MOVZX32rm8 112// except that they use GR32_NOREX for the output operand register class 113// instead of GR32. This allows them to operate on h registers on x86-64. 114let hasSideEffects = 0, isCodeGenOnly = 1 in { 115def MOVZX32rr8_NOREX : I<0xB6, MRMSrcReg, 116 (outs GR32_NOREX:$dst), (ins GR8_NOREX:$src), 117 "movz{bl|x}\t{$src, $dst|$dst, $src}", 118 []>, TB, OpSize32, Sched<[WriteALU]>; 119let mayLoad = 1 in 120def MOVZX32rm8_NOREX : I<0xB6, MRMSrcMem, 121 (outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src), 122 "movz{bl|x}\t{$src, $dst|$dst, $src}", 123 []>, TB, OpSize32, Sched<[WriteALULd]>; 124 125def MOVSX32rr8_NOREX : I<0xBE, MRMSrcReg, 126 (outs GR32_NOREX:$dst), (ins GR8_NOREX:$src), 127 "movs{bl|x}\t{$src, $dst|$dst, $src}", 128 []>, TB, OpSize32, Sched<[WriteALU]>; 129let mayLoad = 1 in 130def MOVSX32rm8_NOREX : I<0xBE, MRMSrcMem, 131 (outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src), 132 "movs{bl|x}\t{$src, $dst|$dst, $src}", 133 []>, TB, OpSize32, Sched<[WriteALULd]>; 134} 135 136// MOVSX64rr8 always has a REX prefix and it has an 8-bit register 137// operand, which makes it a rare instruction with an 8-bit register 138// operand that can never access an h register. If support for h registers 139// were generalized, this would require a special register class. 140def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src), 141 "movs{bq|x}\t{$src, $dst|$dst, $src}", 142 [(set GR64:$dst, (sext GR8:$src))]>, TB, 143 Sched<[WriteALU]>; 144def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src), 145 "movs{bq|x}\t{$src, $dst|$dst, $src}", 146 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, 147 TB, Sched<[WriteALULd]>; 148def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src), 149 "movs{wq|x}\t{$src, $dst|$dst, $src}", 150 [(set GR64:$dst, (sext GR16:$src))]>, TB, 151 Sched<[WriteALU]>; 152def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), 153 "movs{wq|x}\t{$src, $dst|$dst, $src}", 154 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, 155 TB, Sched<[WriteALULd]>; 156def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), 157 "movs{lq|xd}\t{$src, $dst|$dst, $src}", 158 [(set GR64:$dst, (sext GR32:$src))]>, 159 Sched<[WriteALU]>, Requires<[In64BitMode]>; 160def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src), 161 "movs{lq|xd}\t{$src, $dst|$dst, $src}", 162 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>, 163 Sched<[WriteALULd]>, Requires<[In64BitMode]>; 164 165// These instructions exist as a consequence of operand size prefix having 166// control of the destination size, but not the input size. Only support them 167// for the disassembler. 168let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 169def MOVSX16rr32: I<0x63, MRMSrcReg, (outs GR16:$dst), (ins GR32:$src), 170 "movs{lq|xd}\t{$src, $dst|$dst, $src}", []>, 171 Sched<[WriteALU]>, OpSize16, Requires<[In64BitMode]>; 172def MOVSX32rr32: I<0x63, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 173 "movs{lq|xd}\t{$src, $dst|$dst, $src}", []>, 174 Sched<[WriteALU]>, OpSize32, Requires<[In64BitMode]>; 175let mayLoad = 1 in { 176def MOVSX16rm32: I<0x63, MRMSrcMem, (outs GR16:$dst), (ins i32mem:$src), 177 "movs{lq|xd}\t{$src, $dst|$dst, $src}", []>, 178 Sched<[WriteALULd]>, OpSize16, Requires<[In64BitMode]>; 179def MOVSX32rm32: I<0x63, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 180 "movs{lq|xd}\t{$src, $dst|$dst, $src}", []>, 181 Sched<[WriteALULd]>, OpSize32, Requires<[In64BitMode]>; 182} // mayLoad = 1 183} // isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 184 185// movzbq and movzwq encodings for the disassembler 186let hasSideEffects = 0 in { 187def MOVZX64rr8 : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src), 188 "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, 189 TB, Sched<[WriteALU]>; 190let mayLoad = 1 in 191def MOVZX64rm8 : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src), 192 "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, 193 TB, Sched<[WriteALULd]>; 194def MOVZX64rr16 : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src), 195 "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, 196 TB, Sched<[WriteALU]>; 197let mayLoad = 1 in 198def MOVZX64rm16 : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), 199 "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, 200 TB, Sched<[WriteALULd]>; 201} 202 203// 64-bit zero-extension patterns use SUBREG_TO_REG and an operation writing a 204// 32-bit register. 205def : Pat<(i64 (zext GR8:$src)), 206 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8:$src), sub_32bit)>; 207def : Pat<(zextloadi64i8 addr:$src), 208 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 209 210def : Pat<(i64 (zext GR16:$src)), 211 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16:$src), sub_32bit)>; 212def : Pat<(zextloadi64i16 addr:$src), 213 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; 214 215// The preferred way to do 32-bit-to-64-bit zero extension on x86-64 is to use a 216// SUBREG_TO_REG to utilize implicit zero-extension, however this isn't possible 217// when the 32-bit value is defined by a truncate or is copied from something 218// where the high bits aren't necessarily all zero. In such cases, we fall back 219// to these explicit zext instructions. 220def : Pat<(i64 (zext GR32:$src)), 221 (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src), sub_32bit)>; 222def : Pat<(i64 (zextloadi64i32 addr:$src)), 223 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; 224