xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/X86InstrControl.td (revision 85868e8a1daeaae7a0e48effb2ea2310ae3b02c6)
1//===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the X86 jump, return, call, and related instructions.
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14//  Control Flow Instructions.
15//
16
17// Return instructions.
18//
19// The X86retflag return instructions are variadic because we may add ST0 and
20// ST1 arguments when returning values on the x87 stack.
21let isTerminator = 1, isReturn = 1, isBarrier = 1,
22    hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
23  def RETL   : I   <0xC3, RawFrm, (outs), (ins variable_ops),
24                    "ret{l}", []>, OpSize32, Requires<[Not64BitMode]>;
25  def RETQ   : I   <0xC3, RawFrm, (outs), (ins variable_ops),
26                    "ret{q}", []>, OpSize32, Requires<[In64BitMode]>;
27  def RETW   : I   <0xC3, RawFrm, (outs), (ins),
28                    "ret{w}", []>, OpSize16;
29  def RETIL  : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
30                    "ret{l}\t$amt", []>, OpSize32, Requires<[Not64BitMode]>;
31  def RETIQ  : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
32                    "ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>;
33  def RETIW  : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
34                    "ret{w}\t$amt", []>, OpSize16;
35  def LRETL  : I   <0xCB, RawFrm, (outs), (ins),
36                    "{l}ret{l|f}", []>, OpSize32;
37  def LRETQ  : RI  <0xCB, RawFrm, (outs), (ins),
38                    "{l}ret{|f}q", []>, Requires<[In64BitMode]>;
39  def LRETW  : I   <0xCB, RawFrm, (outs), (ins),
40                    "{l}ret{w|f}", []>, OpSize16;
41  def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
42                    "{l}ret{l|f}\t$amt", []>, OpSize32;
43  def LRETIQ : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
44                    "{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>;
45  def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
46                    "{l}ret{w|f}\t$amt", []>, OpSize16;
47
48  // The machine return from interrupt instruction, but sometimes we need to
49  // perform a post-epilogue stack adjustment. Codegen emits the pseudo form
50  // which expands to include an SP adjustment if necessary.
51  def IRET16 : I   <0xcf, RawFrm, (outs), (ins), "iret{w}", []>,
52               OpSize16;
53  def IRET32 : I   <0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>, OpSize32;
54  def IRET64 : RI  <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>;
55  let isCodeGenOnly = 1 in
56  def IRET : PseudoI<(outs), (ins i32imm:$adj), [(X86iret timm:$adj)]>;
57  def RET  : PseudoI<(outs), (ins i32imm:$adj, variable_ops), [(X86retflag timm:$adj)]>;
58}
59
60// Unconditional branches.
61let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
62  def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
63                       "jmp\t$dst", [(br bb:$dst)]>;
64  let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
65    def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget16:$dst),
66                          "jmp\t$dst", []>, OpSize16;
67    def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget32:$dst),
68                          "jmp\t$dst", []>, OpSize32;
69  }
70}
71
72// Conditional Branches.
73let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump],
74    isCodeGenOnly = 1, ForceDisassemble = 1 in {
75  def JCC_1 : Ii8PCRel <0x70, AddCCFrm, (outs),
76                        (ins brtarget8:$dst, ccode:$cond),
77                        "j${cond}\t$dst",
78                        [(X86brcond bb:$dst, timm:$cond, EFLAGS)]>;
79  let hasSideEffects = 0 in {
80    def JCC_2 : Ii16PCRel<0x80, AddCCFrm, (outs),
81                          (ins brtarget16:$dst, ccode:$cond),
82                          "j${cond}\t$dst",
83                          []>, OpSize16, TB;
84    def JCC_4 : Ii32PCRel<0x80, AddCCFrm, (outs),
85                          (ins brtarget32:$dst, ccode:$cond),
86                          "j${cond}\t$dst",
87                          []>, TB, OpSize32;
88  }
89}
90
91def : InstAlias<"jo\t$dst",  (JCC_1 brtarget8:$dst,  0), 0>;
92def : InstAlias<"jno\t$dst", (JCC_1 brtarget8:$dst,  1), 0>;
93def : InstAlias<"jb\t$dst",  (JCC_1 brtarget8:$dst,  2), 0>;
94def : InstAlias<"jae\t$dst", (JCC_1 brtarget8:$dst,  3), 0>;
95def : InstAlias<"je\t$dst",  (JCC_1 brtarget8:$dst,  4), 0>;
96def : InstAlias<"jne\t$dst", (JCC_1 brtarget8:$dst,  5), 0>;
97def : InstAlias<"jbe\t$dst", (JCC_1 brtarget8:$dst,  6), 0>;
98def : InstAlias<"ja\t$dst",  (JCC_1 brtarget8:$dst,  7), 0>;
99def : InstAlias<"js\t$dst",  (JCC_1 brtarget8:$dst,  8), 0>;
100def : InstAlias<"jns\t$dst", (JCC_1 brtarget8:$dst,  9), 0>;
101def : InstAlias<"jp\t$dst",  (JCC_1 brtarget8:$dst, 10), 0>;
102def : InstAlias<"jnp\t$dst", (JCC_1 brtarget8:$dst, 11), 0>;
103def : InstAlias<"jl\t$dst",  (JCC_1 brtarget8:$dst, 12), 0>;
104def : InstAlias<"jge\t$dst", (JCC_1 brtarget8:$dst, 13), 0>;
105def : InstAlias<"jle\t$dst", (JCC_1 brtarget8:$dst, 14), 0>;
106def : InstAlias<"jg\t$dst",  (JCC_1 brtarget8:$dst, 15), 0>;
107
108// jcx/jecx/jrcx instructions.
109let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
110  // These are the 32-bit versions of this instruction for the asmparser.  In
111  // 32-bit mode, the address size prefix is jcxz and the unprefixed version is
112  // jecxz.
113  let Uses = [CX] in
114    def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
115                        "jcxz\t$dst", []>, AdSize16, Requires<[Not64BitMode]>;
116  let Uses = [ECX] in
117    def JECXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
118                        "jecxz\t$dst", []>, AdSize32;
119
120  let Uses = [RCX] in
121    def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
122                         "jrcxz\t$dst", []>, AdSize64, Requires<[In64BitMode]>;
123}
124
125// Indirect branches
126let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
127  def JMP16r     : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst",
128                     [(brind GR16:$dst)]>, Requires<[Not64BitMode]>,
129                     OpSize16, Sched<[WriteJump]>;
130  def JMP16m     : I<0xFF, MRM4m, (outs), (ins i16mem:$dst), "jmp{w}\t{*}$dst",
131                     [(brind (loadi16 addr:$dst))]>, Requires<[Not64BitMode]>,
132                     OpSize16, Sched<[WriteJumpLd]>;
133
134  def JMP32r     : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
135                     [(brind GR32:$dst)]>, Requires<[Not64BitMode]>,
136                     OpSize32, Sched<[WriteJump]>;
137  def JMP32m     : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
138                     [(brind (loadi32 addr:$dst))]>, Requires<[Not64BitMode]>,
139                     OpSize32, Sched<[WriteJumpLd]>;
140
141  def JMP64r     : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
142                     [(brind GR64:$dst)]>, Requires<[In64BitMode]>,
143                     Sched<[WriteJump]>;
144  def JMP64m     : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
145                     [(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>,
146                     Sched<[WriteJumpLd]>;
147
148  // Win64 wants indirect jumps leaving the function to have a REX_W prefix.
149  // These are switched from TAILJMPr/m64_REX in MCInstLower.
150  let isCodeGenOnly = 1, hasREX_WPrefix = 1 in {
151    def JMP64r_REX : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
152                       "rex64 jmp{q}\t{*}$dst", []>, Sched<[WriteJump]>;
153    let mayLoad = 1 in
154    def JMP64m_REX : I<0xFF, MRM4m, (outs), (ins i64mem:$dst),
155                       "rex64 jmp{q}\t{*}$dst", []>, Sched<[WriteJumpLd]>;
156
157  }
158
159  // Non-tracking jumps for IBT, use with caution.
160  let isCodeGenOnly = 1 in {
161    def JMP16r_NT : I<0xFF, MRM4r, (outs), (ins GR16 : $dst), "jmp{w}\t{*}$dst",
162                      [(X86NoTrackBrind GR16 : $dst)]>, Requires<[Not64BitMode]>,
163                      OpSize16, Sched<[WriteJump]>, NOTRACK;
164
165    def JMP16m_NT : I<0xFF, MRM4m, (outs), (ins i16mem : $dst), "jmp{w}\t{*}$dst",
166                      [(X86NoTrackBrind (loadi16 addr : $dst))]>,
167                      Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>,
168                      NOTRACK;
169
170    def JMP32r_NT : I<0xFF, MRM4r, (outs), (ins GR32 : $dst), "jmp{l}\t{*}$dst",
171                      [(X86NoTrackBrind GR32 : $dst)]>, Requires<[Not64BitMode]>,
172                      OpSize32, Sched<[WriteJump]>, NOTRACK;
173    def JMP32m_NT : I<0xFF, MRM4m, (outs), (ins i32mem : $dst), "jmp{l}\t{*}$dst",
174                      [(X86NoTrackBrind (loadi32 addr : $dst))]>,
175                      Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>,
176                      NOTRACK;
177
178    def JMP64r_NT : I<0xFF, MRM4r, (outs), (ins GR64 : $dst), "jmp{q}\t{*}$dst",
179                      [(X86NoTrackBrind GR64 : $dst)]>, Requires<[In64BitMode]>,
180                      Sched<[WriteJump]>, NOTRACK;
181    def JMP64m_NT : I<0xFF, MRM4m, (outs), (ins i64mem : $dst), "jmp{q}\t{*}$dst",
182                      [(X86NoTrackBrind(loadi64 addr : $dst))]>,
183                      Requires<[In64BitMode]>, Sched<[WriteJumpLd]>, NOTRACK;
184  }
185
186  let Predicates = [Not64BitMode], AsmVariantName = "att" in {
187    def FARJMP16i  : Iseg16<0xEA, RawFrmImm16, (outs),
188                            (ins i16imm:$off, i16imm:$seg),
189                            "ljmp{w}\t$seg, $off", []>,
190                            OpSize16, Sched<[WriteJump]>;
191    def FARJMP32i  : Iseg32<0xEA, RawFrmImm16, (outs),
192                            (ins i32imm:$off, i16imm:$seg),
193                            "ljmp{l}\t$seg, $off", []>,
194                            OpSize32, Sched<[WriteJump]>;
195  }
196  def FARJMP64   : RI<0xFF, MRM5m, (outs), (ins opaquemem:$dst),
197                      "ljmp{q}\t{*}$dst", []>, Sched<[WriteJump]>, Requires<[In64BitMode]>;
198
199  let AsmVariantName = "att" in
200  def FARJMP16m  : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst),
201                     "ljmp{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>;
202  def FARJMP32m  : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst),
203                     "{l}jmp{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>;
204}
205
206// Loop instructions
207let SchedRW = [WriteJump] in {
208def LOOP   : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
209def LOOPE  : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
210def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
211}
212
213//===----------------------------------------------------------------------===//
214//  Call Instructions...
215//
216let isCall = 1 in
217  // All calls clobber the non-callee saved registers. ESP is marked as
218  // a use to prevent stack-pointer assignments that appear immediately
219  // before calls from potentially appearing dead. Uses for argument
220  // registers are added manually.
221  let Uses = [ESP, SSP] in {
222    def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
223                           (outs), (ins i32imm_pcrel:$dst),
224                           "call{l}\t$dst", []>, OpSize32,
225                      Requires<[Not64BitMode]>, Sched<[WriteJump]>;
226    let hasSideEffects = 0 in
227      def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
228                             (outs), (ins i16imm_pcrel:$dst),
229                             "call{w}\t$dst", []>, OpSize16,
230                        Sched<[WriteJump]>;
231    def CALL16r     : I<0xFF, MRM2r, (outs), (ins GR16:$dst),
232                        "call{w}\t{*}$dst", [(X86call GR16:$dst)]>,
233                      OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
234    def CALL16m     : I<0xFF, MRM2m, (outs), (ins i16mem:$dst),
235                        "call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))]>,
236                        OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>,
237                        Sched<[WriteJumpLd]>;
238    def CALL32r     : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
239                        "call{l}\t{*}$dst", [(X86call GR32:$dst)]>, OpSize32,
240                        Requires<[Not64BitMode,NotUseRetpolineIndirectCalls]>,
241                        Sched<[WriteJump]>;
242    def CALL32m     : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
243                        "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))]>,
244                        OpSize32,
245                        Requires<[Not64BitMode,FavorMemIndirectCall,
246                                  NotUseRetpolineIndirectCalls]>,
247                        Sched<[WriteJumpLd]>;
248
249    // Non-tracking calls for IBT, use with caution.
250    let isCodeGenOnly = 1 in {
251      def CALL16r_NT : I<0xFF, MRM2r, (outs), (ins GR16 : $dst),
252                        "call{w}\t{*}$dst",[(X86NoTrackCall GR16 : $dst)]>,
253                        OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK;
254      def CALL16m_NT : I<0xFF, MRM2m, (outs), (ins i16mem : $dst),
255                        "call{w}\t{*}$dst",[(X86NoTrackCall(loadi16 addr : $dst))]>,
256                        OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>,
257                        Sched<[WriteJumpLd]>, NOTRACK;
258      def CALL32r_NT : I<0xFF, MRM2r, (outs), (ins GR32 : $dst),
259                        "call{l}\t{*}$dst",[(X86NoTrackCall GR32 : $dst)]>,
260                        OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK;
261      def CALL32m_NT : I<0xFF, MRM2m, (outs), (ins i32mem : $dst),
262                        "call{l}\t{*}$dst",[(X86NoTrackCall(loadi32 addr : $dst))]>,
263                        OpSize32, Requires<[Not64BitMode,FavorMemIndirectCall]>,
264                        Sched<[WriteJumpLd]>, NOTRACK;
265    }
266
267    let Predicates = [Not64BitMode], AsmVariantName = "att" in {
268      def FARCALL16i  : Iseg16<0x9A, RawFrmImm16, (outs),
269                               (ins i16imm:$off, i16imm:$seg),
270                               "lcall{w}\t$seg, $off", []>,
271                               OpSize16, Sched<[WriteJump]>;
272      def FARCALL32i  : Iseg32<0x9A, RawFrmImm16, (outs),
273                               (ins i32imm:$off, i16imm:$seg),
274                               "lcall{l}\t$seg, $off", []>,
275                               OpSize32, Sched<[WriteJump]>;
276    }
277
278    def FARCALL16m  : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst),
279                        "lcall{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>;
280    def FARCALL32m  : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst),
281                        "{l}call{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>;
282  }
283
284
285// Tail call stuff.
286let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
287    isCodeGenOnly = 1, Uses = [ESP, SSP] in {
288  def TCRETURNdi : PseudoI<(outs), (ins i32imm_pcrel:$dst, i32imm:$offset),
289                           []>, Sched<[WriteJump]>, NotMemoryFoldable;
290  def TCRETURNri : PseudoI<(outs), (ins ptr_rc_tailcall:$dst, i32imm:$offset),
291                           []>, Sched<[WriteJump]>, NotMemoryFoldable;
292  let mayLoad = 1 in
293  def TCRETURNmi : PseudoI<(outs), (ins i32mem_TC:$dst, i32imm:$offset),
294                           []>, Sched<[WriteJumpLd]>;
295
296  def TAILJMPd : PseudoI<(outs), (ins i32imm_pcrel:$dst),
297                         []>, Sched<[WriteJump]>;
298
299  def TAILJMPr : PseudoI<(outs), (ins ptr_rc_tailcall:$dst),
300                         []>, Sched<[WriteJump]>;
301  let mayLoad = 1 in
302  def TAILJMPm : PseudoI<(outs), (ins i32mem_TC:$dst),
303                         []>, Sched<[WriteJumpLd]>;
304}
305
306// Conditional tail calls are similar to the above, but they are branches
307// rather than barriers, and they use EFLAGS.
308let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1,
309    isCodeGenOnly = 1, SchedRW = [WriteJump] in
310  let Uses = [ESP, EFLAGS, SSP] in {
311  def TCRETURNdicc : PseudoI<(outs),
312                     (ins i32imm_pcrel:$dst, i32imm:$offset, i32imm:$cond), []>;
313
314  // This gets substituted to a conditional jump instruction in MC lowering.
315  def TAILJMPd_CC : PseudoI<(outs), (ins i32imm_pcrel:$dst, i32imm:$cond), []>;
316}
317
318
319//===----------------------------------------------------------------------===//
320//  Call Instructions...
321//
322
323// RSP is marked as a use to prevent stack-pointer assignments that appear
324// immediately before calls from potentially appearing dead. Uses for argument
325// registers are added manually.
326let isCall = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in {
327  // NOTE: this pattern doesn't match "X86call imm", because we do not know
328  // that the offset between an arbitrary immediate and the call will fit in
329  // the 32-bit pcrel field that we have.
330  def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
331                        (outs), (ins i64i32imm_pcrel:$dst),
332                        "call{q}\t$dst", []>, OpSize32,
333                      Requires<[In64BitMode]>;
334  def CALL64r       : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
335                        "call{q}\t{*}$dst", [(X86call GR64:$dst)]>,
336                      Requires<[In64BitMode,NotUseRetpolineIndirectCalls]>;
337  def CALL64m       : I<0xFF, MRM2m, (outs), (ins i64mem:$dst),
338                        "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
339                      Requires<[In64BitMode,FavorMemIndirectCall,
340                                NotUseRetpolineIndirectCalls]>;
341
342  // Non-tracking calls for IBT, use with caution.
343  let isCodeGenOnly = 1 in {
344    def CALL64r_NT : I<0xFF, MRM2r, (outs), (ins GR64 : $dst),
345                      "call{q}\t{*}$dst",[(X86NoTrackCall GR64 : $dst)]>,
346                      Requires<[In64BitMode]>, NOTRACK;
347    def CALL64m_NT : I<0xFF, MRM2m, (outs), (ins i64mem : $dst),
348                       "call{q}\t{*}$dst",
349                       [(X86NoTrackCall(loadi64 addr : $dst))]>,
350                       Requires<[In64BitMode,FavorMemIndirectCall]>, NOTRACK;
351  }
352
353  def FARCALL64   : RI<0xFF, MRM3m, (outs), (ins opaquemem:$dst),
354                       "lcall{q}\t{*}$dst", []>;
355}
356
357let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
358    isCodeGenOnly = 1, Uses = [RSP, SSP] in {
359  def TCRETURNdi64   : PseudoI<(outs),
360                               (ins i64i32imm_pcrel:$dst, i32imm:$offset),
361                               []>, Sched<[WriteJump]>;
362  def TCRETURNri64   : PseudoI<(outs),
363                               (ins ptr_rc_tailcall:$dst, i32imm:$offset),
364                               []>, Sched<[WriteJump]>, NotMemoryFoldable;
365  let mayLoad = 1 in
366  def TCRETURNmi64   : PseudoI<(outs),
367                               (ins i64mem_TC:$dst, i32imm:$offset),
368                               []>, Sched<[WriteJumpLd]>, NotMemoryFoldable;
369
370  def TAILJMPd64 : PseudoI<(outs), (ins i64i32imm_pcrel:$dst),
371                           []>, Sched<[WriteJump]>;
372
373  def TAILJMPr64 : PseudoI<(outs), (ins ptr_rc_tailcall:$dst),
374                           []>, Sched<[WriteJump]>;
375
376  let mayLoad = 1 in
377  def TAILJMPm64 : PseudoI<(outs), (ins i64mem_TC:$dst),
378                           []>, Sched<[WriteJumpLd]>;
379
380  // Win64 wants indirect jumps leaving the function to have a REX_W prefix.
381  let hasREX_WPrefix = 1 in {
382    def TAILJMPr64_REX : PseudoI<(outs), (ins ptr_rc_tailcall:$dst),
383                                 []>, Sched<[WriteJump]>;
384
385    let mayLoad = 1 in
386    def TAILJMPm64_REX : PseudoI<(outs), (ins i64mem_TC:$dst),
387                                 []>, Sched<[WriteJumpLd]>;
388  }
389}
390
391let isPseudo = 1, isCall = 1, isCodeGenOnly = 1,
392    Uses = [RSP, SSP],
393    usesCustomInserter = 1,
394    SchedRW = [WriteJump] in {
395  def RETPOLINE_CALL32 :
396    PseudoI<(outs), (ins GR32:$dst), [(X86call GR32:$dst)]>,
397            Requires<[Not64BitMode,UseRetpolineIndirectCalls]>;
398
399  def RETPOLINE_CALL64 :
400    PseudoI<(outs), (ins GR64:$dst), [(X86call GR64:$dst)]>,
401            Requires<[In64BitMode,UseRetpolineIndirectCalls]>;
402
403  // Retpoline variant of indirect tail calls.
404  let isTerminator = 1, isReturn = 1, isBarrier = 1 in {
405    def RETPOLINE_TCRETURN64 :
406      PseudoI<(outs), (ins GR64:$dst, i32imm:$offset), []>;
407    def RETPOLINE_TCRETURN32 :
408      PseudoI<(outs), (ins GR32:$dst, i32imm:$offset), []>;
409  }
410}
411
412// Conditional tail calls are similar to the above, but they are branches
413// rather than barriers, and they use EFLAGS.
414let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1,
415    isCodeGenOnly = 1, SchedRW = [WriteJump] in
416  let Uses = [RSP, EFLAGS, SSP] in {
417  def TCRETURNdi64cc : PseudoI<(outs),
418                           (ins i64i32imm_pcrel:$dst, i32imm:$offset,
419                            i32imm:$cond), []>;
420
421  // This gets substituted to a conditional jump instruction in MC lowering.
422  def TAILJMPd64_CC : PseudoI<(outs),
423                              (ins i64i32imm_pcrel:$dst, i32imm:$cond), []>;
424}
425