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Date |
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LOC |
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.. | - | - | ||||
AsmParser/ | H | - | - | 1,710 | 1,304 | |
Disassembler/ | H | - | - | 359 | 272 | |
MCTargetDesc/ | H | - | - | 1,690 | 1,275 | |
TargetInfo/ | H | - | - | 44 | 18 | |
README.txt | H A D | 20-Dec-2019 | 3.9 KiB | 160 | 108 | |
SystemZ.h | H A D | 28-Jul-2024 | 8.6 KiB | 213 | 141 | |
SystemZ.td | H A D | 22-Aug-2021 | 3.2 KiB | 94 | 70 | |
SystemZAsmPrinter.cpp | H A D | 28-Jul-2024 | 55.5 KiB | 1,610 | 1,306 | |
SystemZAsmPrinter.h | H A D | 18-Dec-2023 | 4.7 KiB | 127 | 78 | |
SystemZCallingConv.cpp | H A D | 24-Jul-2022 | 1.1 KiB | 31 | 15 | |
SystemZCallingConv.h | H A D | 24-Jul-2022 | 8.2 KiB | 226 | 146 | |
SystemZCallingConv.td | H A D | 18-Dec-2023 | 14.2 KiB | 307 | 253 | |
SystemZConstantPoolValue.cpp | H A D | 27-Aug-2020 | 1.8 KiB | 51 | 36 | |
SystemZConstantPoolValue.h | H A D | 27-Aug-2020 | 1.7 KiB | 58 | 32 | |
SystemZCopyPhysRegs.cpp | H A D | 04-Jul-2022 | 3.6 KiB | 113 | 74 | |
SystemZElimCompare.cpp | H A D | 28-Jul-2024 | 26 KiB | 735 | 523 | |
SystemZFeatures.td | H A D | 28-Jul-2024 | 14.7 KiB | 385 | 320 | |
SystemZFrameLowering.cpp | H A D | 28-Jul-2024 | 58.8 KiB | 1,529 | 1,082 | |
SystemZFrameLowering.h | H A D | 28-Jul-2024 | 6.9 KiB | 174 | 106 | |
SystemZHazardRecognizer.cpp | H A D | 18-Dec-2023 | 14.8 KiB | 464 | 319 | |
SystemZHazardRecognizer.h | H A D | 13-Jun-2021 | 5.9 KiB | 162 | 58 | |
SystemZISelDAGToDAG.cpp | H A D | 28-Jul-2024 | 75.8 KiB | 2,106 | 1,481 | |
SystemZISelLowering.cpp | H A D | 21-Nov-2024 | 370.1 KiB | 9,739 | 7,376 | |
SystemZISelLowering.h | H A D | 28-Jul-2024 | 33.3 KiB | 832 | 503 | |
SystemZInstrBuilder.h | H A D | 27-Aug-2020 | 1.6 KiB | 45 | 25 | |
SystemZInstrDFP.td | H A D | 20-Dec-2019 | 9.3 KiB | 247 | 208 | |
SystemZInstrFP.td | H A D | 28-Jul-2024 | 26.2 KiB | 598 | 503 | |
SystemZInstrFormats.td | H A D | 28-Jul-2024 | 192.7 KiB | 5,580 | 4,853 | |
SystemZInstrHFP.td | H A D | 28-Jul-2024 | 10.1 KiB | 250 | 206 | |
SystemZInstrInfo.cpp | H A D | 28-Jul-2024 | 80.9 KiB | 2,308 | 1,854 | |
SystemZInstrInfo.h | H A D | 28-Jul-2024 | 16 KiB | 394 | 228 | |
SystemZInstrInfo.td | H A D | 28-Jul-2024 | 104.4 KiB | 2,363 | 2,022 | |
SystemZInstrSystem.td | H A D | 28-Jul-2024 | 18.4 KiB | 552 | 427 | |
SystemZInstrVector.td | H A D | 28-Jul-2024 | 94.8 KiB | 2,028 | 1,784 | |
SystemZLDCleanup.cpp | H A D | 28-Jul-2024 | 5 KiB | 147 | 90 | |
SystemZLongBranch.cpp | H A D | 14-Apr-2023 | 16.7 KiB | 488 | 314 | |
SystemZMCInstLower.cpp | H A D | 02-Dec-2021 | 3.1 KiB | 101 | 76 | |
SystemZMCInstLower.h | H A D | 27-Jan-2022 | 1.3 KiB | 43 | 23 | |
SystemZMachineFunctionInfo.cpp | H A D | 04-Jul-2022 | 772 | 23 | 9 | |
SystemZMachineFunctionInfo.h | H A D | 18-Dec-2023 | 4.3 KiB | 115 | 64 | |
SystemZMachineScheduler.cpp | H A D | 20-Mar-2022 | 8.7 KiB | 261 | 163 | |
SystemZMachineScheduler.h | H A D | 02-Sep-2023 | 5.1 KiB | 156 | 73 | |
SystemZOperands.td | H A D | 18-Dec-2023 | 26 KiB | 676 | 570 | |
SystemZOperators.td | H A D | 28-Jul-2024 | 53.9 KiB | 1,043 | 970 | |
SystemZPatterns.td | H A D | 28-Jul-2024 | 8.4 KiB | 175 | 157 | |
SystemZPostRewrite.cpp | H A D | 04-Jul-2022 | 10.1 KiB | 266 | 187 | |
SystemZProcessors.td | H A D | 04-Jul-2022 | 1.9 KiB | 44 | 34 | |
SystemZRegisterInfo.cpp | H A D | 24-Jan-2024 | 17.8 KiB | 466 | 366 | |
SystemZRegisterInfo.h | H A D | 02-Sep-2023 | 6.6 KiB | 184 | 100 | |
SystemZRegisterInfo.td | H A D | 18-Dec-2023 | 13.6 KiB | 350 | 302 | |
SystemZSchedule.td | H A D | 04-Jul-2022 | 2.2 KiB | 69 | 57 | |
SystemZScheduleZ13.td | H A D | 28-Jul-2024 | 72.6 KiB | 1,564 | 1,268 | |
SystemZScheduleZ14.td | H A D | 28-Jul-2024 | 78.2 KiB | 1,654 | 1,353 | |
SystemZScheduleZ15.td | H A D | 28-Jul-2024 | 80.9 KiB | 1,700 | 1,395 | |
SystemZScheduleZ16.td | H A D | 28-Jul-2024 | 82.9 KiB | 1,733 | 1,424 | |
SystemZScheduleZ196.td | H A D | 28-Jul-2024 | 55.9 KiB | 1,245 | 1,002 | |
SystemZScheduleZEC12.td | H A D | 28-Jul-2024 | 57.6 KiB | 1,290 | 1,035 | |
SystemZSelectionDAGInfo.cpp | H A D | 14-Apr-2023 | 12 KiB | 270 | 202 | |
SystemZSelectionDAGInfo.h | H A D | 04-Jul-2022 | 3.1 KiB | 73 | 47 | |
SystemZShortenInst.cpp | H A D | 28-Jul-2024 | 12 KiB | 401 | 299 | |
SystemZSubtarget.cpp | H A D | 28-Jul-2024 | 4.3 KiB | 132 | 84 | |
SystemZSubtarget.h | H A D | 02-Sep-2023 | 4.6 KiB | 129 | 77 | |
SystemZTDC.cpp | H A D | 27-Jan-2022 | 13.4 KiB | 393 | 274 | |
SystemZTargetMachine.cpp | H A D | 28-Jul-2024 | 12 KiB | 336 | 194 | |
SystemZTargetMachine.h | H A D | 18-Dec-2023 | 2.3 KiB | 64 | 34 | |
SystemZTargetObjectFile.cpp | H A D | 28-Jul-2024 | 712 | 20 | 9 | |
SystemZTargetObjectFile.h | H A D | 28-Jul-2024 | 905 | 28 | 11 | |
SystemZTargetStreamer.h | H A D | 18-Dec-2023 | 2.2 KiB | 57 | 40 | |
SystemZTargetTransformInfo.cpp | H A D | 28-Jul-2024 | 50.4 KiB | 1,345 | 963 | |
SystemZTargetTransformInfo.h | H A D | 28-Jul-2024 | 6 KiB | 138 | 97 | |
ZOSLibcallNames.def | H A D | 18-Dec-2023 | 3.7 KiB |
README.txt
1//===---------------------------------------------------------------------===// 2// Random notes about and ideas for the SystemZ backend. 3//===---------------------------------------------------------------------===// 4 5The initial backend is deliberately restricted to z10. We should add support 6for later architectures at some point. 7 8-- 9 10If an inline asm ties an i32 "r" result to an i64 input, the input 11will be treated as an i32, leaving the upper bits uninitialised. 12For example: 13 14define void @f4(i32 *%dst) { 15 %val = call i32 asm "blah $0", "=r,0" (i64 103) 16 store i32 %val, i32 *%dst 17 ret void 18} 19 20from CodeGen/SystemZ/asm-09.ll will use LHI rather than LGHI. 21to load 103. This seems to be a general target-independent problem. 22 23-- 24 25The tuning of the choice between LOAD ADDRESS (LA) and addition in 26SystemZISelDAGToDAG.cpp is suspect. It should be tweaked based on 27performance measurements. 28 29-- 30 31There is no scheduling support. 32 33-- 34 35We don't use the BRANCH ON INDEX instructions. 36 37-- 38 39We only use MVC, XC and CLC for constant-length block operations. 40We could extend them to variable-length operations too, 41using EXECUTE RELATIVE LONG. 42 43MVCIN, MVCLE and CLCLE may be worthwhile too. 44 45-- 46 47We don't use CUSE or the TRANSLATE family of instructions for string 48operations. The TRANSLATE ones are probably more difficult to exploit. 49 50-- 51 52We don't take full advantage of builtins like fabsl because the calling 53conventions require f128s to be returned by invisible reference. 54 55-- 56 57ADD LOGICAL WITH SIGNED IMMEDIATE could be useful when we need to 58produce a carry. SUBTRACT LOGICAL IMMEDIATE could be useful when we 59need to produce a borrow. (Note that there are no memory forms of 60ADD LOGICAL WITH CARRY and SUBTRACT LOGICAL WITH BORROW, so the high 61part of 128-bit memory operations would probably need to be done 62via a register.) 63 64-- 65 66We don't use ICM, STCM, or CLM. 67 68-- 69 70We don't use ADD (LOGICAL) HIGH, SUBTRACT (LOGICAL) HIGH, 71or COMPARE (LOGICAL) HIGH yet. 72 73-- 74 75DAGCombiner doesn't yet fold truncations of extended loads. Functions like: 76 77 unsigned long f (unsigned long x, unsigned short *y) 78 { 79 return (x << 32) | *y; 80 } 81 82therefore end up as: 83 84 sllg %r2, %r2, 32 85 llgh %r0, 0(%r3) 86 lr %r2, %r0 87 br %r14 88 89but truncating the load would give: 90 91 sllg %r2, %r2, 32 92 lh %r2, 0(%r3) 93 br %r14 94 95-- 96 97Functions like: 98 99define i64 @f1(i64 %a) { 100 %and = and i64 %a, 1 101 ret i64 %and 102} 103 104ought to be implemented as: 105 106 lhi %r0, 1 107 ngr %r2, %r0 108 br %r14 109 110but two-address optimizations reverse the order of the AND and force: 111 112 lhi %r0, 1 113 ngr %r0, %r2 114 lgr %r2, %r0 115 br %r14 116 117CodeGen/SystemZ/and-04.ll has several examples of this. 118 119-- 120 121Out-of-range displacements are usually handled by loading the full 122address into a register. In many cases it would be better to create 123an anchor point instead. E.g. for: 124 125define void @f4a(i128 *%aptr, i64 %base) { 126 %addr = add i64 %base, 524288 127 %bptr = inttoptr i64 %addr to i128 * 128 %a = load volatile i128 *%aptr 129 %b = load i128 *%bptr 130 %add = add i128 %a, %b 131 store i128 %add, i128 *%aptr 132 ret void 133} 134 135(from CodeGen/SystemZ/int-add-08.ll) we load %base+524288 and %base+524296 136into separate registers, rather than using %base+524288 as a base for both. 137 138-- 139 140Dynamic stack allocations round the size to 8 bytes and then allocate 141that rounded amount. It would be simpler to subtract the unrounded 142size from the copy of the stack pointer and then align the result. 143See CodeGen/SystemZ/alloca-01.ll for an example. 144 145-- 146 147If needed, we can support 16-byte atomics using LPQ, STPQ and CSDG. 148 149-- 150 151We might want to model all access registers and use them to spill 15232-bit values. 153 154-- 155 156We might want to use the 'overflow' condition of eg. AR to support 157llvm.sadd.with.overflow.i32 and related instructions - the generated code 158for signed overflow check is currently quite bad. This would improve 159the results of using -ftrapv. 160