1 //===----------------------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLVM_LIB_TARGET_RISCV_RISCVSELECTIONDAGINFO_H 10 #define LLVM_LIB_TARGET_RISCV_RISCVSELECTIONDAGINFO_H 11 12 #include "llvm/CodeGen/SDNodeInfo.h" 13 #include "llvm/CodeGen/SelectionDAGTargetInfo.h" 14 15 #define GET_SDNODE_ENUM 16 #include "RISCVGenSDNodeInfo.inc" 17 18 namespace llvm { 19 20 namespace RISCVISD { 21 // RISCVISD Node TSFlags 22 enum : llvm::SDNodeTSFlags { 23 HasPassthruOpMask = 1 << 0, 24 HasMaskOpMask = 1 << 1, 25 }; 26 } // namespace RISCVISD 27 28 class RISCVSelectionDAGInfo : public SelectionDAGGenTargetInfo { 29 public: 30 RISCVSelectionDAGInfo(); 31 32 ~RISCVSelectionDAGInfo() override; 33 34 void verifyTargetNode(const SelectionDAG &DAG, 35 const SDNode *N) const override; 36 hasPassthruOp(unsigned Opcode)37 bool hasPassthruOp(unsigned Opcode) const { 38 return GenNodeInfo.getDesc(Opcode).TSFlags & RISCVISD::HasPassthruOpMask; 39 } 40 hasMaskOp(unsigned Opcode)41 bool hasMaskOp(unsigned Opcode) const { 42 return GenNodeInfo.getDesc(Opcode).TSFlags & RISCVISD::HasMaskOpMask; 43 } 44 getMAccOpcode(unsigned MulOpcode)45 unsigned getMAccOpcode(unsigned MulOpcode) const { 46 switch (static_cast<RISCVISD::GenNodeType>(MulOpcode)) { 47 default: 48 llvm_unreachable("Unexpected opcode"); 49 case RISCVISD::VWMUL_VL: 50 return RISCVISD::VWMACC_VL; 51 case RISCVISD::VWMULU_VL: 52 return RISCVISD::VWMACCU_VL; 53 case RISCVISD::VWMULSU_VL: 54 return RISCVISD::VWMACCSU_VL; 55 } 56 } 57 }; 58 59 } // namespace llvm 60 61 #endif // LLVM_LIB_TARGET_RISCV_RISCVSELECTIONDAGINFO_H 62