1//===-- RISCVInstrInfoXsf.td - SiFive custom instructions --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the vendor extensions defined by SiFive. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// XSFVCP extension instructions. 15//===----------------------------------------------------------------------===// 16 17def VCIXVS2 : RISCVVConstraint<VS2Constraint.Value>; 18def VCIXVS2VS1 : RISCVVConstraint<!or(VS2Constraint.Value, 19 VS1Constraint.Value)>; 20 21class VCIXType<bits<4> val> { 22 bits<4> Val = val; 23} 24 25def VCIX_X : VCIXType<0b0000>; 26def VCIX_XV : VCIXType<0b0010>; 27def VCIX_XVV : VCIXType<0b1010>; 28def VCIX_XVW : VCIXType<0b1111>; 29 30// The payload and tsimm5 operands are all marked as ImmArg in the IR 31// intrinsic and will be target constant, so use TImmLeaf rather than ImmLeaf. 32class PayloadOp<int bitsNum> : RISCVOp, TImmLeaf<XLenVT, "return isUInt<" # bitsNum # ">(Imm);"> { 33 let ParserMatchClass = UImmAsmOperand<bitsNum>; 34 let DecoderMethod = "decodeUImmOperand<"# bitsNum # ">"; 35 let OperandType = "OPERAND_UIMM" # bitsNum; 36} 37 38def payload1 : PayloadOp<1>; 39def payload2 : PayloadOp<2>; 40def payload5 : PayloadOp<5>; 41 42def tsimm5 : Operand<XLenVT>, TImmLeaf<XLenVT, [{return isInt<5>(Imm);}]> { 43 let ParserMatchClass = SImmAsmOperand<5>; 44 let EncoderMethod = "getImmOpValue"; 45 let DecoderMethod = "decodeSImmOperand<5>"; 46 let MCOperandPredicate = [{ 47 int64_t Imm; 48 if (MCOp.evaluateAsConstantImm(Imm)) 49 return isInt<5>(Imm); 50 return MCOp.isBareSymbolRef(); 51 }]; 52} 53 54class SwapVCIXIns<dag funct6, dag rd, dag rs2, dag rs1, bit swap> { 55 dag Ins = !con(funct6, !if(swap, rs2, rd), !if(swap, rd, rs2), rs1); 56} 57 58class RVInstVCCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins, 59 string opcodestr, string argstr> 60 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 61 bits<5> rs2; 62 bits<5> rs1; 63 bits<5> rd; 64 bits<2> funct6_lo2; 65 bit vm; 66 67 let Inst{31-28} = funct6_hi4; 68 let Inst{27-26} = funct6_lo2; 69 let Inst{25} = vm; 70 let Inst{24-20} = rs2; 71 let Inst{19-15} = rs1; 72 let Inst{14-12} = funct3; 73 let Inst{11-7} = rd; 74 let Inst{6-0} = OPC_CUSTOM_2.Value; 75 76 let Uses = [VTYPE, VL]; 77 let RVVConstraint = NoConstraint; 78} 79 80class RVInstVCFCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins, 81 string opcodestr, string argstr> 82 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 83 bits<5> rs2; 84 bits<5> rs1; 85 bits<5> rd; 86 bit funct6_lo1; 87 bit vm; 88 89 let Inst{31-28} = funct6_hi4; 90 let Inst{27} = 1; 91 let Inst{26} = funct6_lo1; 92 let Inst{25} = vm; 93 let Inst{24-20} = rs2; 94 let Inst{19-15} = rs1; 95 let Inst{14-12} = funct3; 96 let Inst{11-7} = rd; 97 let Inst{6-0} = OPC_CUSTOM_2.Value; 98 99 let Uses = [VTYPE, VL]; 100 let RVVConstraint = NoConstraint; 101} 102 103class VCIXInfo<string suffix, VCIXType type, DAGOperand TyRd, 104 DAGOperand TyRs2, DAGOperand TyRs1, bit HaveOutputDst> { 105 string OpcodeStr = !if(HaveOutputDst, "sf.vc.v." # suffix, 106 "sf.vc." # suffix); 107 bits<4> Funct6_hi4 = type.Val; 108 bits<3> Funct3 = !cond(!eq(TyRs1, VR): 0b000, 109 !eq(TyRs1, GPR): 0b100, 110 !eq(TyRs1, FPR32): 0b101, 111 !eq(TyRs1, simm5): 0b011); 112 dag Outs = !if(!not(HaveOutputDst), (outs), 113 !if(!or(!eq(type, VCIX_XVV), !eq(type, VCIX_XVW)), 114 (outs TyRd:$rd_wb), (outs TyRd:$rd))); 115 dag Ins = SwapVCIXIns<!if(!ne(TyRs1, FPR32), (ins uimm2:$funct6_lo2), 116 (ins uimm1:$funct6_lo1)), 117 !if(!and(HaveOutputDst, !or(!eq(type, VCIX_X), 118 !eq(type, VCIX_XV))), 119 (ins), (ins TyRd:$rd)), 120 (ins TyRs2:$rs2), 121 (ins TyRs1:$rs1), 122 !if(!eq(type, VCIX_X), 1, 0)>.Ins; 123 string Prototype = !if(!eq(type, VCIX_X), "$funct6_lo2, $rs2, $rd, $rs1", 124 !if(!ne(TyRs1, FPR32), "$funct6_lo2, $rd, $rs2, $rs1", 125 "$funct6_lo1, $rd, $rs2, $rs1")); 126 string Constraints = !if(!not(HaveOutputDst), "", 127 !if(!or(!eq(type, VCIX_XVV), 128 !eq(type, VCIX_XVW)), "$rd = $rd_wb", "")); 129 RISCVVConstraint RVVConstraint = !if(!or(!not(HaveOutputDst), 130 !ne(type, VCIX_XVW)), NoConstraint, 131 !if(!eq(TyRs1, VR), VCIXVS2VS1, VCIXVS2)); 132} 133 134class CustomSiFiveVCIX<VCIXInfo info> 135 : RVInstVCCustom2<info.Funct6_hi4, info.Funct3, info.Outs, 136 info.Ins, info.OpcodeStr, info.Prototype> { 137 let Constraints = info.Constraints; 138 let RVVConstraint = info.RVVConstraint; 139} 140 141class CustomSiFiveVCIF<VCIXInfo info> 142 : RVInstVCFCustom2<info.Funct6_hi4, info.Funct3, info.Outs, 143 info.Ins, info.OpcodeStr, info.Prototype> { 144 let Constraints = info.Constraints; 145 let RVVConstraint = info.RVVConstraint; 146} 147 148multiclass CustomSiFiveVCIXorVCIF<string suffix, VCIXType type, 149 DAGOperand TyRd, DAGOperand TyRs2, 150 DAGOperand TyRs1, bit HaveOutputDst> { 151 defvar info = VCIXInfo<suffix, type, TyRd, TyRs2, TyRs1, HaveOutputDst>; 152 if !eq(TyRs1, FPR32) then { 153 def NAME : CustomSiFiveVCIF<info>; 154 } else { 155 def NAME : CustomSiFiveVCIX<info>; 156 } 157} 158 159multiclass CustomSiFiveVCIX<string suffix, VCIXType type, 160 DAGOperand InTyRd, DAGOperand InTyRs2, 161 DAGOperand InTyRs1> { 162 let vm = 1 in 163 defm VC_ # NAME : CustomSiFiveVCIXorVCIF<suffix, type, InTyRd, InTyRs2, 164 InTyRs1, 0>; 165 let vm = 0 in 166 defm VC_V_ # NAME : CustomSiFiveVCIXorVCIF<suffix, type, VR, InTyRs2, 167 InTyRs1, 1>; 168} 169 170let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { 171class CustomSiFiveVMACC<bits<6> funct6, RISCVVFormat opv, string opcodestr> 172 : RVInstVCCustom2<funct6{5-2}, opv.Value, (outs VR:$rd), (ins VR:$rs1, VR:$rs2), 173 opcodestr, "$rd, $rs1, $rs2"> { 174 let vm = 1; 175 let funct6_lo2 = funct6{1-0}; 176} 177} 178 179class CustomSiFiveVFNRCLIP<bits<6> funct6, RISCVVFormat opv, string opcodestr> 180 : VALUVF<funct6, opv, opcodestr> { 181 let Inst{6-0} = OPC_CUSTOM_2.Value; 182} 183 184let Predicates = [HasVendorXSfvcp], mayLoad = 0, mayStore = 0, 185 hasSideEffects = 1, hasNoSchedulingInfo = 1, DecoderNamespace = "XSfvcp" in { 186 defm X : CustomSiFiveVCIX<"x", VCIX_X, uimm5, uimm5, GPR>, Sched<[]>; 187 defm I : CustomSiFiveVCIX<"i", VCIX_X, uimm5, uimm5, simm5>, Sched<[]>; 188 defm XV : CustomSiFiveVCIX<"xv", VCIX_XV, uimm5, VR, GPR>, Sched<[]>; 189 defm IV : CustomSiFiveVCIX<"iv", VCIX_XV, uimm5, VR, simm5>, Sched<[]>; 190 defm VV : CustomSiFiveVCIX<"vv", VCIX_XV, uimm5, VR, VR>, Sched<[]>; 191 defm FV : CustomSiFiveVCIX<"fv", VCIX_XV, uimm5, VR, FPR32>, Sched<[]>; 192 defm XVV : CustomSiFiveVCIX<"xvv", VCIX_XVV, VR, VR, GPR>, Sched<[]>; 193 defm IVV : CustomSiFiveVCIX<"ivv", VCIX_XVV, VR, VR, simm5>, Sched<[]>; 194 defm VVV : CustomSiFiveVCIX<"vvv", VCIX_XVV, VR, VR, VR>, Sched<[]>; 195 defm FVV : CustomSiFiveVCIX<"fvv", VCIX_XVV, VR, VR, FPR32>, Sched<[]>; 196 defm XVW : CustomSiFiveVCIX<"xvw", VCIX_XVW, VR, VR, GPR>, Sched<[]>; 197 defm IVW : CustomSiFiveVCIX<"ivw", VCIX_XVW, VR, VR, simm5>, Sched<[]>; 198 defm VVW : CustomSiFiveVCIX<"vvw", VCIX_XVW, VR, VR, VR>, Sched<[]>; 199 defm FVW : CustomSiFiveVCIX<"fvw", VCIX_XVW, VR, VR, FPR32>, Sched<[]>; 200} 201 202let Predicates = [HasVendorXSfvqmaccdod], DecoderNamespace = "XSfvqmaccdod" in { 203 def VQMACCU_2x8x2 : CustomSiFiveVMACC<0b101100, OPMVV, "sf.vqmaccu.2x8x2">; 204 def VQMACC_2x8x2 : CustomSiFiveVMACC<0b101101, OPMVV, "sf.vqmacc.2x8x2">; 205 def VQMACCUS_2x8x2 : CustomSiFiveVMACC<0b101110, OPMVV, "sf.vqmaccus.2x8x2">; 206 def VQMACCSU_2x8x2 : CustomSiFiveVMACC<0b101111, OPMVV, "sf.vqmaccsu.2x8x2">; 207} 208 209let Predicates = [HasVendorXSfvqmaccqoq], DecoderNamespace = "XSfvqmaccqoq" in { 210 def VQMACCU_4x8x4 : CustomSiFiveVMACC<0b111100, OPMVV, "sf.vqmaccu.4x8x4">; 211 def VQMACC_4x8x4 : CustomSiFiveVMACC<0b111101, OPMVV, "sf.vqmacc.4x8x4">; 212 def VQMACCUS_4x8x4 : CustomSiFiveVMACC<0b111110, OPMVV, "sf.vqmaccus.4x8x4">; 213 def VQMACCSU_4x8x4 : CustomSiFiveVMACC<0b111111, OPMVV, "sf.vqmaccsu.4x8x4">; 214} 215 216let Predicates = [HasVendorXSfvfwmaccqqq], DecoderNamespace = "XSfvfwmaccqqq" in { 217 def VFWMACC_4x4x4 : CustomSiFiveVMACC<0b111100, OPFVV, "sf.vfwmacc.4x4x4">; 218} 219 220let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvfnrclipxfqf", 221 Uses = [FRM] in { 222 def VFNRCLIP_XU_F_QF : CustomSiFiveVFNRCLIP<0b100010, OPFVF, "sf.vfnrclip.xu.f.qf">; 223 def VFNRCLIP_X_F_QF : CustomSiFiveVFNRCLIP<0b100011, OPFVF, "sf.vfnrclip.x.f.qf">; 224} 225 226class VPseudoVC_X<Operand OpClass, DAGOperand RS1Class> : 227 Pseudo<(outs), 228 (ins OpClass:$op1, payload5:$rs2, payload5:$rd, RS1Class:$r1, 229 AVL:$vl, ixlenimm:$sew), []>, 230 RISCVVPseudo { 231 let mayLoad = 0; 232 let mayStore = 0; 233 let HasVLOp = 1; 234 let HasSEWOp = 1; 235 let hasSideEffects = 0; 236 let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); 237} 238 239class VPseudoVC_XV<Operand OpClass, VReg RS2Class, DAGOperand RS1Class> : 240 Pseudo<(outs), 241 (ins OpClass:$op1, payload5:$rd, RS2Class:$rs2, RS1Class:$r1, 242 AVL:$vl, ixlenimm:$sew), []>, 243 RISCVVPseudo { 244 let mayLoad = 0; 245 let mayStore = 0; 246 let HasVLOp = 1; 247 let HasSEWOp = 1; 248 let hasSideEffects = 0; 249 let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); 250} 251 252class VPseudoVC_XVV<Operand OpClass, VReg RDClass, VReg RS2Class, 253 DAGOperand RS1Class> : 254 Pseudo<(outs), 255 (ins OpClass:$op1, RDClass:$rd, RS2Class:$rs2, RS1Class:$r1, 256 AVL:$vl, ixlenimm:$sew), []>, 257 RISCVVPseudo { 258 let mayLoad = 0; 259 let mayStore = 0; 260 let HasVLOp = 1; 261 let HasSEWOp = 1; 262 let hasSideEffects = 0; 263 let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); 264} 265 266class VPseudoVC_V_X<Operand OpClass, VReg RDClass, DAGOperand RS1Class> : 267 Pseudo<(outs RDClass:$rd), 268 (ins OpClass:$op1, payload5:$rs2, RS1Class:$r1, 269 AVL:$vl, ixlenimm:$sew), []>, 270 RISCVVPseudo { 271 let mayLoad = 0; 272 let mayStore = 0; 273 let HasVLOp = 1; 274 let HasSEWOp = 1; 275 let hasSideEffects = 0; 276 let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); 277} 278 279class VPseudoVC_V_XV<Operand OpClass, VReg RDClass, VReg RS2Class, 280 DAGOperand RS1Class> : 281 Pseudo<(outs RDClass:$rd), 282 (ins OpClass:$op1, RS2Class:$rs2, RS1Class:$r1, 283 AVL:$vl, ixlenimm:$sew), []>, 284 RISCVVPseudo { 285 let mayLoad = 0; 286 let mayStore = 0; 287 let HasVLOp = 1; 288 let HasSEWOp = 1; 289 let hasSideEffects = 0; 290 let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); 291} 292 293class VPseudoVC_V_XVV<Operand OpClass, VReg RDClass, VReg RS2Class, 294 DAGOperand RS1Class> : 295 Pseudo<(outs RDClass:$rd), 296 (ins OpClass:$op1, RDClass:$rs3, RS2Class:$rs2, RS1Class:$r1, 297 AVL:$vl, ixlenimm:$sew), []>, 298 RISCVVPseudo { 299 let mayLoad = 0; 300 let mayStore = 0; 301 let HasVLOp = 1; 302 let HasSEWOp = 1; 303 let hasSideEffects = 0; 304 let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); 305} 306 307multiclass VPseudoVC_X<LMULInfo m, DAGOperand RS1Class, 308 Operand OpClass = payload2> { 309 let VLMul = m.value in { 310 let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in { 311 def "PseudoVC_" # NAME # "_SE_" # m.MX 312 : VPseudoVC_X<OpClass, RS1Class>, 313 Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>; 314 def "PseudoVC_V_" # NAME # "_SE_" # m.MX 315 : VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>, 316 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>; 317 } 318 def "PseudoVC_V_" # NAME # "_" # m.MX 319 : VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>, 320 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>; 321 } 322} 323 324multiclass VPseudoVC_XV<LMULInfo m, DAGOperand RS1Class, 325 Operand OpClass = payload2> { 326 let VLMul = m.value in { 327 let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in { 328 def "PseudoVC_" # NAME # "_SE_" # m.MX 329 : VPseudoVC_XV<OpClass, m.vrclass, RS1Class>, 330 Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>; 331 def "PseudoVC_V_" # NAME # "_SE_" # m.MX 332 : VPseudoVC_V_XV<OpClass, m.vrclass, m.vrclass, RS1Class>, 333 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>; 334 } 335 def "PseudoVC_V_" # NAME # "_" # m.MX 336 : VPseudoVC_V_XV<OpClass, m.vrclass, m.vrclass, RS1Class>, 337 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>; 338 } 339} 340 341multiclass VPseudoVC_XVV<LMULInfo m, DAGOperand RS1Class, 342 Operand OpClass = payload2> { 343 let VLMul = m.value in { 344 let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in { 345 def "PseudoVC_" # NAME # "_SE_" # m.MX 346 : VPseudoVC_XVV<OpClass, m.vrclass, m.vrclass, RS1Class>, 347 Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>; 348 def "PseudoVC_V_" # NAME # "_SE_" # m.MX 349 : VPseudoVC_V_XVV<OpClass, m.vrclass, m.vrclass, RS1Class>, 350 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>; 351 } 352 def "PseudoVC_V_" # NAME # "_" # m.MX 353 : VPseudoVC_V_XVV<OpClass, m.vrclass, m.vrclass, RS1Class>, 354 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>; 355 } 356} 357 358multiclass VPseudoVC_XVW<LMULInfo m, DAGOperand RS1Class, 359 Operand OpClass = payload2> { 360 let VLMul = m.value in { 361 let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in 362 def "PseudoVC_" # NAME # "_SE_" # m.MX 363 : VPseudoVC_XVV<OpClass, m.wvrclass, m.vrclass, RS1Class>, 364 Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>; 365 let Constraints = "@earlyclobber $rd, $rd = $rs3" in { 366 let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in 367 def "PseudoVC_V_" # NAME # "_SE_" # m.MX 368 : VPseudoVC_V_XVV<OpClass, m.wvrclass, m.vrclass, RS1Class>, 369 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>; 370 def "PseudoVC_V_" # NAME # "_" # m.MX 371 : VPseudoVC_V_XVV<OpClass, m.wvrclass, m.vrclass, RS1Class>, 372 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>; 373 } 374 } 375} 376 377multiclass VPseudoSiFiveVMACC<string mx, VReg vd_type, VReg vs2_type, 378 string Constraint = ""> { 379 def "Pseudo" # NAME # "_" # mx 380 : VPseudoTernaryNoMaskWithPolicy<vd_type, V_M1.vrclass, vs2_type, Constraint>; 381} 382 383multiclass VPseudoSiFiveVQMACCDOD<string Constraint = ""> { 384 foreach m = MxListVF8 in 385 let VLMul = m.value in 386 defm NAME : VPseudoSiFiveVMACC<m.MX, m.vrclass, m.vrclass, Constraint>; 387} 388 389multiclass VPseudoSiFiveVQMACCQOQ<string Constraint = ""> { 390 foreach m = [V_MF2, V_M1, V_M2, V_M4] in 391 let VLMul = m.value in 392 defm NAME : VPseudoSiFiveVMACC<m.MX, m.wvrclass, m.vrclass, Constraint>; 393} 394 395multiclass VPseudoSiFiveVFWMACC<string Constraint = ""> { 396 foreach m = MxListVF2 in 397 let VLMul = m.value in 398 defm NAME : VPseudoSiFiveVMACC<m.MX, m.wvrclass, m.vrclass, Constraint>; 399} 400 401multiclass VPseudoSiFiveVFNRCLIP<string Constraint = "@earlyclobber $rd"> { 402 foreach i = 0-4 in 403 let hasSideEffects = 0, hasPostISelHook = 1 in 404 defm "Pseudo" # NAME : VPseudoBinaryRoundingMode<MxListW[i].vrclass, 405 MxListVF4[i].vrclass, 406 FPR32, MxListW[i], 407 Constraint, /*sew*/0, 408 UsesVXRM=0>; 409} 410 411let Predicates = [HasVendorXSfvcp] in { 412 foreach m = MxList in { 413 defm X : VPseudoVC_X<m, GPR>; 414 defm I : VPseudoVC_X<m, tsimm5>; 415 defm XV : VPseudoVC_XV<m, GPR>; 416 defm IV : VPseudoVC_XV<m, tsimm5>; 417 defm VV : VPseudoVC_XV<m, m.vrclass>; 418 defm XVV : VPseudoVC_XVV<m, GPR>; 419 defm IVV : VPseudoVC_XVV<m, tsimm5>; 420 defm VVV : VPseudoVC_XVV<m, m.vrclass>; 421 } 422 foreach f = FPList in { 423 foreach m = f.MxList in { 424 defm f.FX # "V" : VPseudoVC_XV<m, f.fprclass, payload1>; 425 defm f.FX # "VV" : VPseudoVC_XVV<m, f.fprclass, payload1>; 426 } 427 } 428 foreach m = MxListW in { 429 defm XVW : VPseudoVC_XVW<m, GPR>; 430 defm IVW : VPseudoVC_XVW<m, tsimm5>; 431 defm VVW : VPseudoVC_XVW<m, m.vrclass>; 432 } 433 foreach f = FPListW in { 434 foreach m = f.MxList in 435 defm f.FX # "VW" : VPseudoVC_XVW<m, f.fprclass, payload1>; 436 } 437} 438 439let Predicates = [HasVendorXSfvqmaccdod] in { 440 defm VQMACCU_2x8x2 : VPseudoSiFiveVQMACCDOD; 441 defm VQMACC_2x8x2 : VPseudoSiFiveVQMACCDOD; 442 defm VQMACCUS_2x8x2 : VPseudoSiFiveVQMACCDOD; 443 defm VQMACCSU_2x8x2 : VPseudoSiFiveVQMACCDOD; 444} 445 446let Predicates = [HasVendorXSfvqmaccqoq] in { 447 defm VQMACCU_4x8x4 : VPseudoSiFiveVQMACCQOQ; 448 defm VQMACC_4x8x4 : VPseudoSiFiveVQMACCQOQ; 449 defm VQMACCUS_4x8x4 : VPseudoSiFiveVQMACCQOQ; 450 defm VQMACCSU_4x8x4 : VPseudoSiFiveVQMACCQOQ; 451} 452 453let Predicates = [HasVendorXSfvfwmaccqqq] in { 454 defm VFWMACC_4x4x4 : VPseudoSiFiveVFWMACC; 455} 456 457let Predicates = [HasVendorXSfvfnrclipxfqf] in { 458 defm VFNRCLIP_XU_F_QF : VPseudoSiFiveVFNRCLIP; 459 defm VFNRCLIP_X_F_QF : VPseudoSiFiveVFNRCLIP; 460} 461 462// SDNode 463def SDT_SF_VC_V_X : SDTypeProfile<1, 4, [SDTCisVec<0>, 464 SDTCisVT<1, XLenVT>, 465 SDTCisSameAs<1, 2>, 466 SDTCisSameAs<1, 3>, 467 SDTCisSameAs<1, 4>]>; 468 469def SDT_SF_VC_XV : SDTypeProfile<0, 5, [SDTCisSameAs<0, 1>, 470 SDTCisVec<2>, 471 SDTCisSameAs<0, 4>, 472 SDTCisVT<0, XLenVT>]>; 473 474def SDT_SF_VC_V_XV : SDTypeProfile<1, 4, [SDTCisVec<0>, 475 SDTCisVT<1, XLenVT>, 476 SDTCisSameAs<0, 2>, 477 SDTCisSameAs<1, 4>]>; 478 479def SDT_SF_VC_XVV : SDTypeProfile<0, 5, [SDTCisVT<0, XLenVT>, 480 SDTCisVec<1>, 481 SDTCisSameAs<1, 2>, 482 SDTCisSameAs<0, 4>]>; 483 484def SDT_SF_VC_V_XVV : SDTypeProfile<1, 5, [SDTCisVec<0>, 485 SDTCisVT<1, XLenVT>, 486 SDTCisSameAs<0, 2>, 487 SDTCisSameAs<0, 3>, 488 SDTCisSameAs<1, 5>]>; 489 490def SDT_SF_VC_XVW : SDTypeProfile<0, 5, [SDTCisVT<0, XLenVT>, 491 SDTCisVec<1>, SDTCisVec<2>, 492 SDTCisSameAs<0, 4>]>; 493 494def SDT_SF_VC_V_XVW : SDTypeProfile<1, 5, [SDTCisVec<0>, 495 SDTCisVT<1, XLenVT>, 496 SDTCisSameAs<0, 2>, 497 SDTCisVec<3>, 498 SDTCisSameAs<1, 5>]>; 499 500def sf_vc_v_x_se : SDNode<"RISCVISD::SF_VC_V_X_SE", SDT_SF_VC_V_X, [SDNPHasChain]>; 501def sf_vc_v_i_se : SDNode<"RISCVISD::SF_VC_V_I_SE", SDT_SF_VC_V_X, [SDNPHasChain]>; 502def sf_vc_vv_se : SDNode<"RISCVISD::SF_VC_VV_SE", SDT_SF_VC_XV, [SDNPHasChain]>; 503def sf_vc_xv_se : SDNode<"RISCVISD::SF_VC_XV_SE", SDT_SF_VC_XV, [SDNPHasChain]>; 504def sf_vc_iv_se : SDNode<"RISCVISD::SF_VC_IV_SE", SDT_SF_VC_XV, [SDNPHasChain]>; 505def sf_vc_fv_se : SDNode<"RISCVISD::SF_VC_FV_SE", SDT_SF_VC_XV, [SDNPHasChain]>; 506def sf_vc_v_vv_se : SDNode<"RISCVISD::SF_VC_V_VV_SE", SDT_SF_VC_V_XV, [SDNPHasChain]>; 507def sf_vc_v_xv_se : SDNode<"RISCVISD::SF_VC_V_XV_SE", SDT_SF_VC_V_XV, [SDNPHasChain]>; 508def sf_vc_v_iv_se : SDNode<"RISCVISD::SF_VC_V_IV_SE", SDT_SF_VC_V_XV, [SDNPHasChain]>; 509def sf_vc_v_fv_se : SDNode<"RISCVISD::SF_VC_V_FV_SE", SDT_SF_VC_V_XV, [SDNPHasChain]>; 510def sf_vc_vvv_se : SDNode<"RISCVISD::SF_VC_VVV_SE", SDT_SF_VC_XVV, [SDNPHasChain]>; 511def sf_vc_xvv_se : SDNode<"RISCVISD::SF_VC_XVV_SE", SDT_SF_VC_XVV, [SDNPHasChain]>; 512def sf_vc_ivv_se : SDNode<"RISCVISD::SF_VC_IVV_SE", SDT_SF_VC_XVV, [SDNPHasChain]>; 513def sf_vc_fvv_se : SDNode<"RISCVISD::SF_VC_FVV_SE", SDT_SF_VC_XVV, [SDNPHasChain]>; 514def sf_vc_v_vvv_se : SDNode<"RISCVISD::SF_VC_V_VVV_SE", SDT_SF_VC_V_XVV, [SDNPHasChain]>; 515def sf_vc_v_xvv_se : SDNode<"RISCVISD::SF_VC_V_XVV_SE", SDT_SF_VC_V_XVV, [SDNPHasChain]>; 516def sf_vc_v_ivv_se : SDNode<"RISCVISD::SF_VC_V_IVV_SE", SDT_SF_VC_V_XVV, [SDNPHasChain]>; 517def sf_vc_v_fvv_se : SDNode<"RISCVISD::SF_VC_V_FVV_SE", SDT_SF_VC_V_XVV, [SDNPHasChain]>; 518def sf_vc_vvw_se : SDNode<"RISCVISD::SF_VC_VVW_SE", SDT_SF_VC_XVW, [SDNPHasChain]>; 519def sf_vc_xvw_se : SDNode<"RISCVISD::SF_VC_XVW_SE", SDT_SF_VC_XVW, [SDNPHasChain]>; 520def sf_vc_ivw_se : SDNode<"RISCVISD::SF_VC_IVW_SE", SDT_SF_VC_XVW, [SDNPHasChain]>; 521def sf_vc_fvw_se : SDNode<"RISCVISD::SF_VC_FVW_SE", SDT_SF_VC_XVW, [SDNPHasChain]>; 522def sf_vc_v_vvw_se : SDNode<"RISCVISD::SF_VC_V_VVW_SE", SDT_SF_VC_V_XVW, [SDNPHasChain]>; 523def sf_vc_v_xvw_se : SDNode<"RISCVISD::SF_VC_V_XVW_SE", SDT_SF_VC_V_XVW, [SDNPHasChain]>; 524def sf_vc_v_ivw_se : SDNode<"RISCVISD::SF_VC_V_IVW_SE", SDT_SF_VC_V_XVW, [SDNPHasChain]>; 525def sf_vc_v_fvw_se : SDNode<"RISCVISD::SF_VC_V_FVW_SE", SDT_SF_VC_V_XVW, [SDNPHasChain]>; 526 527class VPatVC_OP4_ISD<SDPatternOperator op, 528 string inst, 529 ValueType op2_type, 530 ValueType op3_type, 531 ValueType op4_type, 532 int sew, 533 DAGOperand op2_kind, 534 DAGOperand op3_kind, 535 DAGOperand op4_kind, 536 Operand op1_kind = payload2> : 537 Pat<(op 538 (XLenVT op1_kind:$op1), 539 (op2_type op2_kind:$op2), 540 (op3_type op3_kind:$op3), 541 (op4_type op4_kind:$op4), 542 VLOpFrag), 543 (!cast<Instruction>(inst) 544 (XLenVT op1_kind:$op1), 545 (op2_type op2_kind:$op2), 546 (op3_type op3_kind:$op3), 547 (op4_type op4_kind:$op4), 548 GPR:$vl, sew)>; 549 550class VPatVC_V_OP4_ISD<SDPatternOperator op, 551 string inst, 552 ValueType result_type, 553 ValueType op2_type, 554 ValueType op3_type, 555 ValueType op4_type, 556 int sew, 557 DAGOperand op2_kind, 558 DAGOperand op3_kind, 559 DAGOperand op4_kind, 560 Operand op1_kind = payload2> : 561 Pat<(result_type (op 562 (XLenVT op1_kind:$op1), 563 (op2_type op2_kind:$op2), 564 (op3_type op3_kind:$op3), 565 (op4_type op4_kind:$op4), 566 VLOpFrag)), 567 (!cast<Instruction>(inst) 568 (XLenVT op1_kind:$op1), 569 (op2_type op2_kind:$op2), 570 (op3_type op3_kind:$op3), 571 (op4_type op4_kind:$op4), 572 GPR:$vl, sew)>; 573 574 575class VPatVC_V_OP3_ISD<SDPatternOperator op, 576 string inst, 577 ValueType result_type, 578 ValueType op2_type, 579 ValueType op3_type, 580 int sew, 581 DAGOperand op2_kind, 582 DAGOperand op3_kind, 583 Operand op1_kind = payload2> : 584 Pat<(result_type (op 585 (XLenVT op1_kind:$op1), 586 (op2_type op2_kind:$op2), 587 (op3_type op3_kind:$op3), 588 VLOpFrag)), 589 (!cast<Instruction>(inst) 590 (XLenVT op1_kind:$op1), 591 (op2_type op2_kind:$op2), 592 (op3_type op3_kind:$op3), 593 GPR:$vl, sew)>; 594 595class VPatVC_OP4<string intrinsic_name, 596 string inst, 597 ValueType op2_type, 598 ValueType op3_type, 599 ValueType op4_type, 600 int sew, 601 DAGOperand op2_kind, 602 DAGOperand op3_kind, 603 DAGOperand op4_kind, 604 Operand op1_kind = payload2> : 605 Pat<(!cast<Intrinsic>(intrinsic_name) 606 (XLenVT op1_kind:$op1), 607 (op2_type op2_kind:$op2), 608 (op3_type op3_kind:$op3), 609 (op4_type op4_kind:$op4), 610 VLOpFrag), 611 (!cast<Instruction>(inst) 612 (XLenVT op1_kind:$op1), 613 (op2_type op2_kind:$op2), 614 (op3_type op3_kind:$op3), 615 (op4_type op4_kind:$op4), 616 GPR:$vl, sew)>; 617 618class VPatVC_V_OP4<string intrinsic_name, 619 string inst, 620 ValueType result_type, 621 ValueType op2_type, 622 ValueType op3_type, 623 ValueType op4_type, 624 int sew, 625 DAGOperand op2_kind, 626 DAGOperand op3_kind, 627 DAGOperand op4_kind, 628 Operand op1_kind = payload2> : 629 Pat<(result_type (!cast<Intrinsic>(intrinsic_name) 630 (XLenVT op1_kind:$op1), 631 (op2_type op2_kind:$op2), 632 (op3_type op3_kind:$op3), 633 (op4_type op4_kind:$op4), 634 VLOpFrag)), 635 (!cast<Instruction>(inst) 636 (XLenVT op1_kind:$op1), 637 (op2_type op2_kind:$op2), 638 (op3_type op3_kind:$op3), 639 (op4_type op4_kind:$op4), 640 GPR:$vl, sew)>; 641 642class VPatVC_V_OP3<string intrinsic_name, 643 string inst, 644 ValueType result_type, 645 ValueType op2_type, 646 ValueType op3_type, 647 int sew, 648 DAGOperand op2_kind, 649 DAGOperand op3_kind, 650 Operand op1_kind = payload2> : 651 Pat<(result_type (!cast<Intrinsic>(intrinsic_name) 652 (XLenVT op1_kind:$op1), 653 (op2_type op2_kind:$op2), 654 (op3_type op3_kind:$op3), 655 VLOpFrag)), 656 (!cast<Instruction>(inst) 657 (XLenVT op1_kind:$op1), 658 (op2_type op2_kind:$op2), 659 (op3_type op3_kind:$op3), 660 GPR:$vl, sew)>; 661 662multiclass VPatVC_X<string intrinsic_suffix, string instruction_suffix, 663 VTypeInfo vti, ValueType type, DAGOperand kind> { 664 def : VPatVC_V_OP3_ISD<!cast<SDPatternOperator>("sf_vc_v_" # intrinsic_suffix # "_se"), 665 "PseudoVC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX, 666 vti.Vector, XLenVT, type, vti.Log2SEW, 667 payload5, kind>; 668 def : VPatVC_V_OP3<"int_riscv_sf_vc_v_" # intrinsic_suffix, 669 "PseudoVC_V_" # instruction_suffix # "_" # vti.LMul.MX, 670 vti.Vector, XLenVT, type, vti.Log2SEW, 671 payload5, kind>; 672} 673 674multiclass VPatVC_XV<string intrinsic_suffix, string instruction_suffix, 675 VTypeInfo vti, ValueType type, DAGOperand kind, 676 Operand op1_kind = payload2> { 677 def : VPatVC_OP4_ISD<!cast<SDPatternOperator>("sf_vc_" # intrinsic_suffix # "_se"), 678 "PseudoVC_" # instruction_suffix # "_SE_" # vti.LMul.MX, 679 XLenVT, vti.Vector, type, vti.Log2SEW, 680 payload5, vti.RegClass, kind, op1_kind>; 681 def : VPatVC_V_OP3_ISD<!cast<SDPatternOperator>("sf_vc_v_" # intrinsic_suffix # "_se"), 682 "PseudoVC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX, 683 vti.Vector, vti.Vector, type, vti.Log2SEW, 684 vti.RegClass, kind, op1_kind>; 685 def : VPatVC_V_OP3<"int_riscv_sf_vc_v_" # intrinsic_suffix, 686 "PseudoVC_V_" # instruction_suffix # "_" # vti.LMul.MX, 687 vti.Vector, vti.Vector, type, vti.Log2SEW, 688 vti.RegClass, kind, op1_kind>; 689} 690 691multiclass VPatVC_XVV<string intrinsic_suffix, string instruction_suffix, 692 VTypeInfo wti, VTypeInfo vti, ValueType type, DAGOperand kind, 693 Operand op1_kind = payload2> { 694 def : VPatVC_OP4_ISD<!cast<SDPatternOperator>("sf_vc_" # intrinsic_suffix # "_se"), 695 "PseudoVC_" # instruction_suffix # "_SE_" # vti.LMul.MX, 696 wti.Vector, vti.Vector, type, vti.Log2SEW, 697 wti.RegClass, vti.RegClass, kind, op1_kind>; 698 def : VPatVC_V_OP4_ISD<!cast<SDPatternOperator>("sf_vc_v_" # intrinsic_suffix # "_se"), 699 "PseudoVC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX, 700 wti.Vector, wti.Vector, vti.Vector, type, vti.Log2SEW, 701 wti.RegClass, vti.RegClass, kind, op1_kind>; 702 def : VPatVC_V_OP4<"int_riscv_sf_vc_v_" # intrinsic_suffix, 703 "PseudoVC_V_" # instruction_suffix # "_" # vti.LMul.MX, 704 wti.Vector, wti.Vector, vti.Vector, type, vti.Log2SEW, 705 wti.RegClass, vti.RegClass, kind, op1_kind>; 706} 707 708class GetFTypeInfo<int Sew> { 709 ValueType Scalar = !cond(!eq(Sew, 16) : f16, 710 !eq(Sew, 32) : f32, 711 !eq(Sew, 64) : f64); 712 RegisterClass ScalarRegClass = !cond(!eq(Sew, 16) : FPR16, 713 !eq(Sew, 32) : FPR32, 714 !eq(Sew, 64) : FPR64); 715 716 string ScalarSuffix = !cond(!eq(Scalar, f16) : "FPR16", 717 !eq(Scalar, f32) : "FPR32", 718 !eq(Scalar, f64) : "FPR64"); 719} 720 721multiclass VPatVMACC<string intrinsic, string instruction, string kind, 722 list<VTypeInfoToWide> info_pairs, ValueType vec_m1> { 723 foreach pair = info_pairs in { 724 defvar VdInfo = pair.Wti; 725 defvar Vs2Info = pair.Vti; 726 let Predicates = [HasVInstructions] in 727 def : VPatTernaryNoMaskWithPolicy<"int_riscv_sf_" # intrinsic, 728 "Pseudo" # instruction, kind, VdInfo.Vector, 729 vec_m1, Vs2Info.Vector, 730 Vs2Info.Log2SEW, Vs2Info.LMul, 731 VdInfo.RegClass, VR, Vs2Info.RegClass>; 732 } 733} 734 735defset list<VTypeInfoToWide> VQMACCDODInfoPairs = { 736 def : VTypeInfoToWide<VI8M1, VI32M1>; 737 def : VTypeInfoToWide<VI8M2, VI32M2>; 738 def : VTypeInfoToWide<VI8M4, VI32M4>; 739 def : VTypeInfoToWide<VI8M8, VI32M8>; 740} 741 742defset list<VTypeInfoToWide> VQMACCQOQInfoPairs = { 743 def : VTypeInfoToWide<VI8MF2, VI32M1>; 744 def : VTypeInfoToWide<VI8M1, VI32M2>; 745 def : VTypeInfoToWide<VI8M2, VI32M4>; 746 def : VTypeInfoToWide<VI8M4, VI32M8>; 747} 748 749multiclass VPatVQMACCDOD<string intrinsic, string instruction, string kind> 750 : VPatVMACC<intrinsic, instruction, kind, VQMACCDODInfoPairs, vint8m1_t>; 751 752multiclass VPatVQMACCQOQ<string intrinsic, string instruction, string kind> 753 : VPatVMACC<intrinsic, instruction, kind, VQMACCQOQInfoPairs, vint8m1_t>; 754 755multiclass VPatVFWMACC<string intrinsic, string instruction, string kind> 756 : VPatVMACC<intrinsic, instruction, kind, AllWidenableBFloatToFloatVectors, 757 vbfloat16m1_t>; 758 759defset list<VTypeInfoToWide> VFNRCLIPInfoPairs = { 760 def : VTypeInfoToWide<VI8MF8, VF32MF2>; 761 def : VTypeInfoToWide<VI8MF4, VF32M1>; 762 def : VTypeInfoToWide<VI8MF2, VF32M2>; 763 def : VTypeInfoToWide<VI8M1, VF32M4>; 764 def : VTypeInfoToWide<VI8M2, VF32M8>; 765} 766 767multiclass VPatVFNRCLIP<string intrinsic, string instruction> { 768 foreach pair = VFNRCLIPInfoPairs in { 769 defvar Vti = pair.Vti; 770 defvar Wti = pair.Wti; 771 defm : VPatBinaryRoundingMode<"int_riscv_sf_" # intrinsic, 772 "Pseudo" # instruction # "_" # Vti.LMul.MX, 773 Vti.Vector, Wti.Vector, Wti.Scalar, Vti.Mask, 774 Vti.Log2SEW, Vti.RegClass, 775 Wti.RegClass, Wti.ScalarRegClass>; 776 } 777} 778 779let Predicates = [HasVendorXSfvcp] in { 780 foreach vti = AllIntegerVectors in { 781 defm : VPatVC_X<"x", "X", vti, XLenVT, GPR>; 782 defm : VPatVC_X<"i", "I", vti, XLenVT, tsimm5>; 783 defm : VPatVC_XV<"xv", "XV", vti, XLenVT, GPR>; 784 defm : VPatVC_XV<"iv", "IV", vti, XLenVT, tsimm5>; 785 defm : VPatVC_XV<"vv", "VV", vti, vti.Vector, vti.RegClass>; 786 defm : VPatVC_XVV<"xvv", "XVV", vti, vti, XLenVT, GPR>; 787 defm : VPatVC_XVV<"ivv", "IVV", vti, vti, XLenVT, tsimm5>; 788 defm : VPatVC_XVV<"vvv", "VVV", vti, vti, vti.Vector, vti.RegClass>; 789 790 if !ne(vti.SEW, 8) then { 791 defvar finfo = GetFTypeInfo<vti.SEW>; 792 defm : VPatVC_XV<"fv", finfo.ScalarSuffix # "V", vti, finfo.Scalar, 793 finfo.ScalarRegClass, payload1>; 794 defm : VPatVC_XVV<"fvv", finfo.ScalarSuffix # "VV", vti, vti, finfo.Scalar, 795 finfo.ScalarRegClass, payload1>; 796 } 797 } 798 foreach VtiToWti = AllWidenableIntVectors in { 799 defvar vti = VtiToWti.Vti; 800 defvar wti = VtiToWti.Wti; 801 defvar iinfo = GetIntVTypeInfo<vti>.Vti; 802 defm : VPatVC_XVV<"xvw", "XVW", wti, vti, iinfo.Scalar, iinfo.ScalarRegClass>; 803 defm : VPatVC_XVV<"ivw", "IVW", wti, vti, XLenVT, tsimm5>; 804 defm : VPatVC_XVV<"vvw", "VVW", wti, vti, vti.Vector, vti.RegClass>; 805 806 if !ne(vti.SEW, 8) then { 807 defvar finfo = GetFTypeInfo<vti.SEW>; 808 defm : VPatVC_XVV<"fvw", finfo.ScalarSuffix # "VW", wti, vti, finfo.Scalar, 809 finfo.ScalarRegClass, payload1>; 810 } 811 } 812} 813 814let Predicates = [HasVendorXSfvqmaccdod] in { 815 defm : VPatVQMACCDOD<"vqmaccu_2x8x2", "VQMACCU", "2x8x2">; 816 defm : VPatVQMACCDOD<"vqmacc_2x8x2", "VQMACC", "2x8x2">; 817 defm : VPatVQMACCDOD<"vqmaccus_2x8x2", "VQMACCUS", "2x8x2">; 818 defm : VPatVQMACCDOD<"vqmaccsu_2x8x2", "VQMACCSU", "2x8x2">; 819} 820 821let Predicates = [HasVendorXSfvqmaccqoq] in { 822 defm : VPatVQMACCQOQ<"vqmaccu_4x8x4", "VQMACCU", "4x8x4">; 823 defm : VPatVQMACCQOQ<"vqmacc_4x8x4", "VQMACC", "4x8x4">; 824 defm : VPatVQMACCQOQ<"vqmaccus_4x8x4", "VQMACCUS", "4x8x4">; 825 defm : VPatVQMACCQOQ<"vqmaccsu_4x8x4", "VQMACCSU", "4x8x4">; 826} 827 828let Predicates = [HasVendorXSfvfwmaccqqq] in { 829 defm : VPatVFWMACC<"vfwmacc_4x4x4", "VFWMACC", "4x4x4">; 830} 831 832let Predicates = [HasVendorXSfvfnrclipxfqf] in { 833 defm : VPatVFNRCLIP<"vfnrclip_xu_f_qf", "VFNRCLIP_XU_F_QF">; 834 defm : VPatVFNRCLIP<"vfnrclip_x_f_qf", "VFNRCLIP_X_F_QF">; 835} 836 837let Predicates = [HasVendorXSiFivecdiscarddlone] in { 838 let hasNoSchedulingInfo = 1, hasSideEffects = 1, mayLoad = 0, mayStore = 0, 839 DecoderNamespace = "XSiFivecdiscarddlone" in 840 def SF_CDISCARD_D_L1 841 : RVInstIUnary<0b111111000010, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1), 842 "sf.cdiscard.d.l1", "$rs1">, Sched<[]> { 843 let rd = 0; 844 } 845 def : InstAlias<"sf.cdiscard.d.l1", (SF_CDISCARD_D_L1 X0)>; 846} // Predicates = [HasVendorXSifivecdiscarddlone] 847 848let Predicates = [HasVendorXSiFivecflushdlone] in { 849 let hasNoSchedulingInfo = 1, hasSideEffects = 1, mayLoad = 0, mayStore = 0, 850 DecoderNamespace = "XSiFivecflushdlone" in 851 def SF_CFLUSH_D_L1 852 : RVInstIUnary<0b111111000000, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1), 853 "sf.cflush.d.l1", "$rs1">, Sched<[]> { 854 let rd = 0; 855 } 856 def : InstAlias<"sf.cflush.d.l1", (SF_CFLUSH_D_L1 X0)>; 857} // Predicates = [HasVendorXSifivecflushdlone] 858 859let Predicates = [HasVendorXSfcease] in { 860 let hasNoSchedulingInfo = 1, hasSideEffects = 1, mayLoad = 0, mayStore = 0, 861 DecoderNamespace = "XSfcease" in 862 def SF_CEASE : RVInstIUnary<0b001100000101, 0b000, OPC_SYSTEM, (outs), (ins), 863 "sf.cease", "">, Sched<[]> { 864 let rs1 = 0b00000; 865 let rd = 0b00000; 866} 867} 868