1//===-- RISCVFeatures.td - RISC-V Features and Extensions --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// RISC-V subtarget features and instruction predicates. 11//===----------------------------------------------------------------------===// 12 13// Integer Extensions 14 15def FeatureStdExtI 16 : SubtargetFeature<"i", "HasStdExtI", "true", 17 "'I' (Base Integer Instruction Set)">; 18def HasStdExtI : Predicate<"Subtarget->hasStdExtI()">, 19 AssemblerPredicate<(all_of FeatureStdExtI), 20 "'I' (Base Integer Instruction Set)">; 21def FeatureStdExtZic64b 22 : SubtargetFeature<"zic64b", "HasStdExtZic64b", "true", 23 "'Zic64b' (Cache Block Size Is 64 Bytes)">; 24 25def FeatureStdExtZicbom 26 : SubtargetFeature<"zicbom", "HasStdExtZicbom", "true", 27 "'Zicbom' (Cache-Block Management Instructions)">; 28def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">, 29 AssemblerPredicate<(all_of FeatureStdExtZicbom), 30 "'Zicbom' (Cache-Block Management Instructions)">; 31 32def FeatureStdExtZicbop 33 : SubtargetFeature<"zicbop", "HasStdExtZicbop", "true", 34 "'Zicbop' (Cache-Block Prefetch Instructions)">; 35def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">, 36 AssemblerPredicate<(all_of FeatureStdExtZicbop), 37 "'Zicbop' (Cache-Block Prefetch Instructions)">; 38 39def FeatureStdExtZicboz 40 : SubtargetFeature<"zicboz", "HasStdExtZicboz", "true", 41 "'Zicboz' (Cache-Block Zero Instructions)">; 42def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">, 43 AssemblerPredicate<(all_of FeatureStdExtZicboz), 44 "'Zicboz' (Cache-Block Zero Instructions)">; 45 46def FeatureStdExtZiccamoa 47 : SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true", 48 "'Ziccamoa' (Main Memory Supports All Atomics in A)">; 49 50def FeatureStdExtZiccif 51 : SubtargetFeature<"ziccif", "HasStdExtZiccif", "true", 52 "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">; 53 54def FeatureStdExtZicclsm 55 : SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true", 56 "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">; 57 58def FeatureStdExtZiccrse 59 : SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true", 60 "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">; 61 62def FeatureStdExtZicsr 63 : SubtargetFeature<"zicsr", "HasStdExtZicsr", "true", 64 "'zicsr' (CSRs)">; 65def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">, 66 AssemblerPredicate<(all_of FeatureStdExtZicsr), 67 "'Zicsr' (CSRs)">; 68 69def FeatureStdExtZicntr 70 : SubtargetFeature<"zicntr", "HasStdExtZicntr", "true", 71 "'Zicntr' (Base Counters and Timers)", 72 [FeatureStdExtZicsr]>; 73 74def FeatureStdExtZicond 75 : SubtargetFeature<"zicond", "HasStdExtZicond", "true", 76 "'Zicond' (Integer Conditional Operations)">; 77def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">, 78 AssemblerPredicate<(all_of FeatureStdExtZicond), 79 "'Zicond' (Integer Conditional Operations)">; 80 81def FeatureStdExtZifencei 82 : SubtargetFeature<"zifencei", "HasStdExtZifencei", "true", 83 "'Zifencei' (fence.i)">; 84def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">, 85 AssemblerPredicate<(all_of FeatureStdExtZifencei), 86 "'Zifencei' (fence.i)">; 87 88def FeatureStdExtZihintpause 89 : SubtargetFeature<"zihintpause", "HasStdExtZihintpause", "true", 90 "'Zihintpause' (Pause Hint)">; 91def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">, 92 AssemblerPredicate<(all_of FeatureStdExtZihintpause), 93 "'Zihintpause' (Pause Hint)">; 94 95def FeatureStdExtZihintntl 96 : SubtargetFeature<"zihintntl", "HasStdExtZihintntl", "true", 97 "'Zihintntl' (Non-Temporal Locality Hints)">; 98def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">, 99 AssemblerPredicate<(all_of FeatureStdExtZihintntl), 100 "'Zihintntl' (Non-Temporal Locality Hints)">; 101 102def FeatureStdExtZihpm 103 : SubtargetFeature<"zihpm", "HasStdExtZihpm", "true", 104 "'Zihpm' (Hardware Performance Counters)", 105 [FeatureStdExtZicsr]>; 106 107def FeatureStdExtZimop : SubtargetFeature<"experimental-zimop", "HasStdExtZimop", "true", 108 "'Zimop' (May-Be-Operations)">; 109def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">, 110 AssemblerPredicate<(all_of FeatureStdExtZimop), 111 "'Zimop' (May-Be-Operations)">; 112 113def FeatureStdExtZicfilp 114 : SubtargetFeature<"experimental-zicfilp", "HasStdExtZicfilp", "true", 115 "'Zicfilp' (Landing pad)">; 116def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">, 117 AssemblerPredicate<(all_of FeatureStdExtZicfilp), 118 "'Zicfilp' (Landing pad)">; 119 120def FeatureStdExtZicfiss 121 : SubtargetFeature<"experimental-zicfiss", "HasStdExtZicfiss", "true", 122 "'Zicfiss' (Shadow stack)", 123 [FeatureStdExtZicsr, FeatureStdExtZimop]>; 124def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">, 125 AssemblerPredicate<(all_of FeatureStdExtZicfiss), 126 "'Zicfiss' (Shadow stack)">; 127def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">; 128 129// Multiply Extensions 130 131def FeatureStdExtM 132 : SubtargetFeature<"m", "HasStdExtM", "true", 133 "'M' (Integer Multiplication and Division)">; 134def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, 135 AssemblerPredicate<(all_of FeatureStdExtM), 136 "'M' (Integer Multiplication and Division)">; 137 138def FeatureStdExtZmmul 139 : SubtargetFeature<"zmmul", "HasStdExtZmmul", "true", 140 "'Zmmul' (Integer Multiplication)">; 141 142def HasStdExtMOrZmmul 143 : Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">, 144 AssemblerPredicate<(any_of FeatureStdExtM, FeatureStdExtZmmul), 145 "'M' (Integer Multiplication and Division) or " 146 "'Zmmul' (Integer Multiplication)">; 147 148// Atomic Extensions 149 150def FeatureStdExtA 151 : SubtargetFeature<"a", "HasStdExtA", "true", 152 "'A' (Atomic Instructions)">; 153def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, 154 AssemblerPredicate<(all_of FeatureStdExtA), 155 "'A' (Atomic Instructions)">; 156 157def FeatureStdExtZtso 158 : SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true", 159 "'Ztso' (Memory Model - Total Store Order)">; 160def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">, 161 AssemblerPredicate<(all_of FeatureStdExtZtso), 162 "'Ztso' (Memory Model - Total Store Order)">; 163def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">; 164 165def FeatureStdExtZa64rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs", "true", 166 "'Za64rs' (Reservation Set Size of at Most 64 Bytes)">; 167 168def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs", "true", 169 "'Za128rs' (Reservation Set Size of at Most 128 Bytes)">; 170 171def FeatureStdExtZacas 172 : SubtargetFeature<"experimental-zacas", "HasStdExtZacas", "true", 173 "'Zacas' (Atomic Compare-And-Swap Instructions)">; 174def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">, 175 AssemblerPredicate<(all_of FeatureStdExtZacas), 176 "'Zacas' (Atomic Compare-And-Swap Instructions)">; 177def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">; 178 179def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true", 180 "'Zawrs' (Wait on Reservation Set)">; 181def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">, 182 AssemblerPredicate<(all_of FeatureStdExtZawrs), 183 "'Zawrs' (Wait on Reservation Set)">; 184 185// Floating Point Extensions 186 187def FeatureStdExtF 188 : SubtargetFeature<"f", "HasStdExtF", "true", 189 "'F' (Single-Precision Floating-Point)", 190 [FeatureStdExtZicsr]>; 191def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, 192 AssemblerPredicate<(all_of FeatureStdExtF), 193 "'F' (Single-Precision Floating-Point)">; 194 195def FeatureStdExtD 196 : SubtargetFeature<"d", "HasStdExtD", "true", 197 "'D' (Double-Precision Floating-Point)", 198 [FeatureStdExtF]>; 199def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, 200 AssemblerPredicate<(all_of FeatureStdExtD), 201 "'D' (Double-Precision Floating-Point)">; 202 203def FeatureStdExtZfhmin 204 : SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true", 205 "'Zfhmin' (Half-Precision Floating-Point Minimal)", 206 [FeatureStdExtF]>; 207def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">, 208 AssemblerPredicate<(all_of FeatureStdExtZfhmin), 209 "'Zfh' (Half-Precision Floating-Point) or " 210 "'Zfhmin' (Half-Precision Floating-Point Minimal)">; 211 212def FeatureStdExtZfh 213 : SubtargetFeature<"zfh", "HasStdExtZfh", "true", 214 "'Zfh' (Half-Precision Floating-Point)", 215 [FeatureStdExtZfhmin]>; 216def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">, 217 AssemblerPredicate<(all_of FeatureStdExtZfh), 218 "'Zfh' (Half-Precision Floating-Point)">; 219def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">; 220 221def FeatureStdExtZfbfmin 222 : SubtargetFeature<"experimental-zfbfmin", "HasStdExtZfbfmin", "true", 223 "'Zfbfmin' (Scalar BF16 Converts)", 224 [FeatureStdExtF]>; 225def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">, 226 AssemblerPredicate<(all_of FeatureStdExtZfbfmin), 227 "'Zfbfmin' (Scalar BF16 Converts)">; 228 229def HasHalfFPLoadStoreMove 230 : Predicate<"Subtarget->hasHalfFPLoadStoreMove()">, 231 AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin, 232 FeatureStdExtZfbfmin), 233 "'Zfh' (Half-Precision Floating-Point) or " 234 "'Zfhmin' (Half-Precision Floating-Point Minimal) or " 235 "'Zfbfmin' (Scalar BF16 Converts)">; 236 237def FeatureStdExtZfa 238 : SubtargetFeature<"zfa", "HasStdExtZfa", "true", 239 "'Zfa' (Additional Floating-Point)", 240 [FeatureStdExtF]>; 241def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">, 242 AssemblerPredicate<(all_of FeatureStdExtZfa), 243 "'Zfa' (Additional Floating-Point)">; 244 245def FeatureStdExtZfinx 246 : SubtargetFeature<"zfinx", "HasStdExtZfinx", "true", 247 "'Zfinx' (Float in Integer)", 248 [FeatureStdExtZicsr]>; 249def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">, 250 AssemblerPredicate<(all_of FeatureStdExtZfinx), 251 "'Zfinx' (Float in Integer)">; 252 253def FeatureStdExtZdinx 254 : SubtargetFeature<"zdinx", "HasStdExtZdinx", "true", 255 "'Zdinx' (Double in Integer)", 256 [FeatureStdExtZfinx]>; 257def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">, 258 AssemblerPredicate<(all_of FeatureStdExtZdinx), 259 "'Zdinx' (Double in Integer)">; 260 261def FeatureStdExtZhinxmin 262 : SubtargetFeature<"zhinxmin", "HasStdExtZhinxmin", "true", 263 "'Zhinxmin' (Half Float in Integer Minimal)", 264 [FeatureStdExtZfinx]>; 265def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">, 266 AssemblerPredicate<(all_of FeatureStdExtZhinxmin), 267 "'Zhinx' (Half Float in Integer) or " 268 "'Zhinxmin' (Half Float in Integer Minimal)">; 269 270def FeatureStdExtZhinx 271 : SubtargetFeature<"zhinx", "HasStdExtZhinx", "true", 272 "'Zhinx' (Half Float in Integer)", 273 [FeatureStdExtZhinxmin]>; 274def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">, 275 AssemblerPredicate<(all_of FeatureStdExtZhinx), 276 "'Zhinx' (Half Float in Integer)">; 277def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">; 278 279// Compressed Extensions 280 281def FeatureStdExtC 282 : SubtargetFeature<"c", "HasStdExtC", "true", 283 "'C' (Compressed Instructions)">; 284def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, 285 AssemblerPredicate<(all_of FeatureStdExtC), 286 "'C' (Compressed Instructions)">; 287 288def FeatureNoRVCHints 289 : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false", 290 "Disable RVC Hint Instructions.">; 291def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">, 292 AssemblerPredicate<(all_of(not FeatureNoRVCHints)), 293 "RVC Hint Instructions">; 294 295def FeatureStdExtZca 296 : SubtargetFeature<"zca", "HasStdExtZca", "true", 297 "'Zca' (part of the C extension, excluding compressed " 298 "floating point loads/stores)">; 299 300def HasStdExtCOrZca 301 : Predicate<"Subtarget->hasStdExtCOrZca()">, 302 AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZca), 303 "'C' (Compressed Instructions) or " 304 "'Zca' (part of the C extension, excluding " 305 "compressed floating point loads/stores)">; 306 307def FeatureStdExtZcb 308 : SubtargetFeature<"zcb", "HasStdExtZcb", "true", 309 "'Zcb' (Compressed basic bit manipulation instructions)", 310 [FeatureStdExtZca]>; 311def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">, 312 AssemblerPredicate<(all_of FeatureStdExtZcb), 313 "'Zcb' (Compressed basic bit manipulation instructions)">; 314 315def FeatureStdExtZcd 316 : SubtargetFeature<"zcd", "HasStdExtZcd", "true", 317 "'Zcd' (Compressed Double-Precision Floating-Point Instructions)", 318 [FeatureStdExtZca]>; 319 320def HasStdExtCOrZcd 321 : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">, 322 AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd), 323 "'C' (Compressed Instructions) or " 324 "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">; 325 326def FeatureStdExtZcf 327 : SubtargetFeature<"zcf", "HasStdExtZcf", "true", 328 "'Zcf' (Compressed Single-Precision Floating-Point Instructions)", 329 [FeatureStdExtZca]>; 330 331def FeatureStdExtZcmp 332 : SubtargetFeature<"zcmp", "HasStdExtZcmp", "true", 333 "'Zcmp' (sequenced instuctions for code-size reduction)", 334 [FeatureStdExtZca]>; 335def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">, 336 AssemblerPredicate<(all_of FeatureStdExtZcmp), 337 "'Zcmp' (sequenced instuctions for code-size reduction)">; 338 339def FeatureStdExtZcmt 340 : SubtargetFeature<"zcmt", "HasStdExtZcmt", "true", 341 "'Zcmt' (table jump instuctions for code-size reduction)", 342 [FeatureStdExtZca, FeatureStdExtZicsr]>; 343def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">, 344 AssemblerPredicate<(all_of FeatureStdExtZcmt), 345 "'Zcmt' (table jump instuctions for code-size reduction)">; 346 347def FeatureStdExtZce 348 : SubtargetFeature<"zce", "HasStdExtZce", "true", 349 "'Zce' (Compressed extensions for microcontrollers)", 350 [FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp, 351 FeatureStdExtZcmt]>; 352 353def HasStdExtCOrZcfOrZce 354 : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() " 355 "Subtarget->hasStdExtZce()">, 356 AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf, 357 FeatureStdExtZce), 358 "'C' (Compressed Instructions) or " 359 "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">; 360 361def FeatureStdExtZcmop : SubtargetFeature<"experimental-zcmop", "HasStdExtZcmop", "true", 362 "'Zcmop' (Compressed May-Be-Operations)", 363 [FeatureStdExtZca]>; 364def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">, 365 AssemblerPredicate<(all_of FeatureStdExtZcmop), 366 "'Zcmop' (Compressed May-Be-Operations)">; 367 368// Bitmanip Extensions 369 370def FeatureStdExtZba 371 : SubtargetFeature<"zba", "HasStdExtZba", "true", 372 "'Zba' (Address Generation Instructions)">; 373def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">, 374 AssemblerPredicate<(all_of FeatureStdExtZba), 375 "'Zba' (Address Generation Instructions)">; 376def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">; 377 378def FeatureStdExtZbb 379 : SubtargetFeature<"zbb", "HasStdExtZbb", "true", 380 "'Zbb' (Basic Bit-Manipulation)">; 381def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">, 382 AssemblerPredicate<(all_of FeatureStdExtZbb), 383 "'Zbb' (Basic Bit-Manipulation)">; 384 385def FeatureStdExtZbc 386 : SubtargetFeature<"zbc", "HasStdExtZbc", "true", 387 "'Zbc' (Carry-Less Multiplication)">; 388def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">, 389 AssemblerPredicate<(all_of FeatureStdExtZbc), 390 "'Zbc' (Carry-Less Multiplication)">; 391 392def FeatureStdExtZbs 393 : SubtargetFeature<"zbs", "HasStdExtZbs", "true", 394 "'Zbs' (Single-Bit Instructions)">; 395def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">, 396 AssemblerPredicate<(all_of FeatureStdExtZbs), 397 "'Zbs' (Single-Bit Instructions)">; 398 399// Bitmanip Extensions for Cryptography Extensions 400 401def FeatureStdExtZbkb 402 : SubtargetFeature<"zbkb", "HasStdExtZbkb", "true", 403 "'Zbkb' (Bitmanip instructions for Cryptography)">; 404def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">, 405 AssemblerPredicate<(all_of FeatureStdExtZbkb), 406 "'Zbkb' (Bitmanip instructions for Cryptography)">; 407 408def FeatureStdExtZbkx 409 : SubtargetFeature<"zbkx", "HasStdExtZbkx", "true", 410 "'Zbkx' (Crossbar permutation instructions)">; 411def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">, 412 AssemblerPredicate<(all_of FeatureStdExtZbkx), 413 "'Zbkx' (Crossbar permutation instructions)">; 414 415def HasStdExtZbbOrZbkb 416 : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()">, 417 AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb), 418 "'Zbb' (Basic Bit-Manipulation) or " 419 "'Zbkb' (Bitmanip instructions for Cryptography)">; 420 421// The Carry-less multiply subextension for cryptography is a subset of basic 422// carry-less multiply subextension. The former should be enabled if the latter 423// is enabled. 424def FeatureStdExtZbkc 425 : SubtargetFeature<"zbkc", "HasStdExtZbkc", "true", 426 "'Zbkc' (Carry-less multiply instructions for " 427 "Cryptography)">; 428def HasStdExtZbkc 429 : Predicate<"Subtarget->hasStdExtZbkc()">, 430 AssemblerPredicate<(all_of FeatureStdExtZbkc), 431 "'Zbkc' (Carry-less multiply instructions for Cryptography)">; 432 433def HasStdExtZbcOrZbkc 434 : Predicate<"Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()">, 435 AssemblerPredicate<(any_of FeatureStdExtZbc, FeatureStdExtZbkc), 436 "'Zbc' (Carry-Less Multiplication) or " 437 "'Zbkc' (Carry-less multiply instructions " 438 "for Cryptography)">; 439 440// Cryptography Extensions 441 442def FeatureStdExtZknd 443 : SubtargetFeature<"zknd", "HasStdExtZknd", "true", 444 "'Zknd' (NIST Suite: AES Decryption)">; 445def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">, 446 AssemblerPredicate<(all_of FeatureStdExtZknd), 447 "'Zknd' (NIST Suite: AES Decryption)">; 448 449def FeatureStdExtZkne 450 : SubtargetFeature<"zkne", "HasStdExtZkne", "true", 451 "'Zkne' (NIST Suite: AES Encryption)">; 452def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">, 453 AssemblerPredicate<(all_of FeatureStdExtZkne), 454 "'Zkne' (NIST Suite: AES Encryption)">; 455 456// Some instructions belong to both Zknd and Zkne subextensions. 457// They should be enabled if either has been specified. 458def HasStdExtZkndOrZkne 459 : Predicate<"Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne()">, 460 AssemblerPredicate<(any_of FeatureStdExtZknd, FeatureStdExtZkne), 461 "'Zknd' (NIST Suite: AES Decryption) or " 462 "'Zkne' (NIST Suite: AES Encryption)">; 463 464def FeatureStdExtZknh 465 : SubtargetFeature<"zknh", "HasStdExtZknh", "true", 466 "'Zknh' (NIST Suite: Hash Function Instructions)">; 467def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">, 468 AssemblerPredicate<(all_of FeatureStdExtZknh), 469 "'Zknh' (NIST Suite: Hash Function Instructions)">; 470 471def FeatureStdExtZksed 472 : SubtargetFeature<"zksed", "HasStdExtZksed", "true", 473 "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">; 474def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">, 475 AssemblerPredicate<(all_of FeatureStdExtZksed), 476 "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">; 477 478def FeatureStdExtZksh 479 : SubtargetFeature<"zksh", "HasStdExtZksh", "true", 480 "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">; 481def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">, 482 AssemblerPredicate<(all_of FeatureStdExtZksh), 483 "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">; 484 485def FeatureStdExtZkr 486 : SubtargetFeature<"zkr", "HasStdExtZkr", "true", 487 "'Zkr' (Entropy Source Extension)">; 488def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">, 489 AssemblerPredicate<(all_of FeatureStdExtZkr), 490 "'Zkr' (Entropy Source Extension)">; 491 492def FeatureStdExtZkn 493 : SubtargetFeature<"zkn", "HasStdExtZkn", "true", 494 "'Zkn' (NIST Algorithm Suite)", 495 [FeatureStdExtZbkb, 496 FeatureStdExtZbkc, 497 FeatureStdExtZbkx, 498 FeatureStdExtZkne, 499 FeatureStdExtZknd, 500 FeatureStdExtZknh]>; 501 502def FeatureStdExtZks 503 : SubtargetFeature<"zks", "HasStdExtZks", "true", 504 "'Zks' (ShangMi Algorithm Suite)", 505 [FeatureStdExtZbkb, 506 FeatureStdExtZbkc, 507 FeatureStdExtZbkx, 508 FeatureStdExtZksed, 509 FeatureStdExtZksh]>; 510 511def FeatureStdExtZkt 512 : SubtargetFeature<"zkt", "HasStdExtZkt", "true", 513 "'Zkt' (Data Independent Execution Latency)">; 514 515def FeatureStdExtZk 516 : SubtargetFeature<"zk", "HasStdExtZk", "true", 517 "'Zk' (Standard scalar cryptography extension)", 518 [FeatureStdExtZkn, 519 FeatureStdExtZkr, 520 FeatureStdExtZkt]>; 521 522// Vector Extensions 523 524def FeatureStdExtZvl32b : SubtargetFeature<"zvl32b", "ZvlLen", "32", 525 "'Zvl' (Minimum Vector Length) 32">; 526 527foreach i = { 6-16 } in { 528 defvar I = !shl(1, i); 529 def FeatureStdExtZvl#I#b : 530 SubtargetFeature<"zvl"#I#"b", "ZvlLen", !cast<string>(I), 531 "'Zvl' (Minimum Vector Length) "#I, 532 [!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>; 533} 534 535def FeatureStdExtZve32x 536 : SubtargetFeature<"zve32x", "HasStdExtZve32x", "true", 537 "'Zve32x' (Vector Extensions for Embedded Processors " 538 "with maximal 32 EEW)", 539 [FeatureStdExtZicsr, FeatureStdExtZvl32b]>; 540 541def FeatureStdExtZve32f 542 : SubtargetFeature<"zve32f", "HasStdExtZve32f", "true", 543 "'Zve32f' (Vector Extensions for Embedded Processors " 544 "with maximal 32 EEW and F extension)", 545 [FeatureStdExtZve32x, FeatureStdExtF]>; 546 547def FeatureStdExtZve64x 548 : SubtargetFeature<"zve64x", "HasStdExtZve64x", "true", 549 "'Zve64x' (Vector Extensions for Embedded Processors " 550 "with maximal 64 EEW)", 551 [FeatureStdExtZve32x, FeatureStdExtZvl64b]>; 552 553def FeatureStdExtZve64f 554 : SubtargetFeature<"zve64f", "HasStdExtZve64f", "true", 555 "'Zve64f' (Vector Extensions for Embedded Processors " 556 "with maximal 64 EEW and F extension)", 557 [FeatureStdExtZve32f, FeatureStdExtZve64x]>; 558 559def FeatureStdExtZve64d 560 : SubtargetFeature<"zve64d", "HasStdExtZve64d", "true", 561 "'Zve64d' (Vector Extensions for Embedded Processors " 562 "with maximal 64 EEW, F and D extension)", 563 [FeatureStdExtZve64f, FeatureStdExtD]>; 564 565def FeatureStdExtV 566 : SubtargetFeature<"v", "HasStdExtV", "true", 567 "'V' (Vector Extension for Application Processors)", 568 [FeatureStdExtZvl128b, FeatureStdExtZve64d]>; 569 570def FeatureStdExtZvfbfmin 571 : SubtargetFeature<"experimental-zvfbfmin", "HasStdExtZvfbfmin", "true", 572 "'Zvbfmin' (Vector BF16 Converts)", 573 [FeatureStdExtZve32f]>; 574def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">, 575 AssemblerPredicate<(all_of FeatureStdExtZvfbfmin), 576 "'Zvfbfmin' (Vector BF16 Converts)">; 577 578def FeatureStdExtZvfbfwma 579 : SubtargetFeature<"experimental-zvfbfwma", "HasStdExtZvfbfwma", "true", 580 "'Zvfbfwma' (Vector BF16 widening mul-add)", 581 [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>; 582def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">, 583 AssemblerPredicate<(all_of FeatureStdExtZvfbfwma), 584 "'Zvfbfwma' (Vector BF16 widening mul-add)">; 585 586def FeatureStdExtZvfhmin 587 : SubtargetFeature<"zvfhmin", "HasStdExtZvfhmin", "true", 588 "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)", 589 [FeatureStdExtZve32f]>; 590 591def FeatureStdExtZvfh 592 : SubtargetFeature<"zvfh", "HasStdExtZvfh", "true", 593 "'Zvfh' (Vector Half-Precision Floating-Point)", 594 [FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>; 595 596def HasStdExtZfhOrZvfh 597 : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">, 598 AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZvfh), 599 "'Zfh' (Half-Precision Floating-Point) or " 600 "'Zvfh' (Vector Half-Precision Floating-Point)">; 601 602// Vector Cryptography and Bitmanip Extensions 603 604def FeatureStdExtZvkb 605 : SubtargetFeature<"zvkb", "HasStdExtZvkb", "true", 606 "'Zvkb' (Vector Bit-manipulation used in Cryptography)">; 607def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">, 608 AssemblerPredicate<(all_of FeatureStdExtZvkb), 609 "'Zvkb' (Vector Bit-manipulation used in Cryptography)">; 610 611def FeatureStdExtZvbb 612 : SubtargetFeature<"zvbb", "HasStdExtZvbb", "true", 613 "'Zvbb' (Vector basic bit-manipulation instructions)", 614 [FeatureStdExtZvkb]>; 615def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">, 616 AssemblerPredicate<(all_of FeatureStdExtZvbb), 617 "'Zvbb' (Vector basic bit-manipulation instructions)">; 618 619def FeatureStdExtZvbc 620 : SubtargetFeature<"zvbc", "HasStdExtZvbc", "true", 621 "'Zvbc' (Vector Carryless Multiplication)">; 622def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">, 623 AssemblerPredicate<(all_of FeatureStdExtZvbc), 624 "'Zvbc' (Vector Carryless Multiplication)">; 625 626def FeatureStdExtZvkg 627 : SubtargetFeature<"zvkg", "HasStdExtZvkg", "true", 628 "'Zvkg' (Vector GCM instructions for Cryptography)">; 629def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">, 630 AssemblerPredicate<(all_of FeatureStdExtZvkg), 631 "'Zvkg' (Vector GCM instructions for Cryptography)">; 632 633def FeatureStdExtZvkned 634 : SubtargetFeature<"zvkned", "HasStdExtZvkned", "true", 635 "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">; 636def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">, 637 AssemblerPredicate<(all_of FeatureStdExtZvkned), 638 "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">; 639 640def FeatureStdExtZvknha 641 : SubtargetFeature<"zvknha", "HasStdExtZvknha", "true", 642 "'Zvknha' (Vector SHA-2 (SHA-256 only))">; 643def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">, 644 AssemblerPredicate<(all_of FeatureStdExtZvknha), 645 "'Zvknha' (Vector SHA-2 (SHA-256 only))">; 646 647def FeatureStdExtZvknhb 648 : SubtargetFeature<"zvknhb", "HasStdExtZvknhb", "true", 649 "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))", 650 [FeatureStdExtZve64x]>; 651def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">, 652 AssemblerPredicate<(all_of FeatureStdExtZvknhb), 653 "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">; 654 655def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarget->hasStdExtZvknhb()">, 656 AssemblerPredicate<(any_of FeatureStdExtZvknha, FeatureStdExtZvknhb), 657 "'Zvknha' or 'Zvknhb' (Vector SHA-2)">; 658 659def FeatureStdExtZvksed 660 : SubtargetFeature<"zvksed", "HasStdExtZvksed", "true", 661 "'Zvksed' (SM4 Block Cipher Instructions)">; 662def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">, 663 AssemblerPredicate<(all_of FeatureStdExtZvksed), 664 "'Zvksed' (SM4 Block Cipher Instructions)">; 665 666def FeatureStdExtZvksh 667 : SubtargetFeature<"zvksh", "HasStdExtZvksh", "true", 668 "'Zvksh' (SM3 Hash Function Instructions)">; 669def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">, 670 AssemblerPredicate<(all_of FeatureStdExtZvksh), 671 "'Zvksh' (SM3 Hash Function Instructions)">; 672 673def FeatureStdExtZvkt 674 : SubtargetFeature<"zvkt", "HasStdExtZvkt", "true", 675 "'Zvkt' (Vector Data-Independent Execution Latency)">; 676 677// Zvk short-hand extensions 678 679def FeatureStdExtZvkn 680 : SubtargetFeature<"zvkn", "HasStdExtZvkn", "true", 681 "'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and " 682 "'Zvkt')", 683 [FeatureStdExtZvkned, FeatureStdExtZvknhb, 684 FeatureStdExtZvkb, FeatureStdExtZvkt]>; 685 686def FeatureStdExtZvknc 687 : SubtargetFeature<"zvknc", "HasStdExtZvknc", "true", 688 "'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')", 689 [FeatureStdExtZvkn, FeatureStdExtZvbc]>; 690 691def FeatureStdExtZvkng 692 : SubtargetFeature<"zvkng", "HasStdExtZvkng", "true", 693 "'zvkng' (shorthand for 'Zvkn' and 'Zvkg')", 694 [FeatureStdExtZvkn, FeatureStdExtZvkg]>; 695 696def FeatureStdExtZvks 697 : SubtargetFeature<"zvks", "HasStdExtZvks", "true", 698 "'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and " 699 "'Zvkt')", 700 [FeatureStdExtZvksed, FeatureStdExtZvksh, 701 FeatureStdExtZvkb, FeatureStdExtZvkt]>; 702 703def FeatureStdExtZvksc 704 : SubtargetFeature<"zvksc", "HasStdExtZvksc", "true", 705 "'Zvksc' (shorthand for 'Zvks' and 'Zvbc')", 706 [FeatureStdExtZvks, FeatureStdExtZvbc]>; 707 708def FeatureStdExtZvksg 709 : SubtargetFeature<"zvksg", "HasStdExtZvksg", "true", 710 "'Zvksg' (shorthand for 'Zvks' and 'Zvkg')", 711 [FeatureStdExtZvks, FeatureStdExtZvkg]>; 712 713// Vector instruction predicates 714 715def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">, 716 AssemblerPredicate< 717 (any_of FeatureStdExtZve32x), 718 "'V' (Vector Extension for Application Processors), 'Zve32x' " 719 "(Vector Extensions for Embedded Processors)">; 720def HasVInstructionsI64 : Predicate<"Subtarget->hasVInstructionsI64()">, 721 AssemblerPredicate< 722 (any_of FeatureStdExtZve64x), 723 "'V' (Vector Extension for Application Processors) or 'Zve64x' " 724 "(Vector Extensions for Embedded Processors)">; 725def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">, 726 AssemblerPredicate< 727 (any_of FeatureStdExtZve32f), 728 "'V' (Vector Extension for Application Processors), 'Zve32f' " 729 "(Vector Extensions for Embedded Processors)">; 730 731def HasVInstructionsF16Minimal : Predicate<"Subtarget->hasVInstructionsF16Minimal()">, 732 AssemblerPredicate<(any_of FeatureStdExtZvfhmin, FeatureStdExtZvfh), 733 "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) or " 734 "'Zvfh' (Vector Half-Precision Floating-Point)">; 735 736def HasVInstructionsBF16 : Predicate<"Subtarget->hasVInstructionsBF16()">; 737def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">; 738def HasVInstructionsF64 : Predicate<"Subtarget->hasVInstructionsF64()">; 739 740def HasVInstructionsFullMultiply : Predicate<"Subtarget->hasVInstructionsFullMultiply()">; 741 742// Hypervisor Extensions 743 744def FeatureStdExtH 745 : SubtargetFeature<"h", "HasStdExtH", "true", 746 "'H' (Hypervisor)">; 747 748def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">, 749 AssemblerPredicate<(all_of FeatureStdExtH), 750 "'H' (Hypervisor)">; 751 752// Supervisor extensions 753 754def FeatureStdExtSmaia 755 : SubtargetFeature<"smaia", "HasStdExtSmaia", "true", 756 "'Smaia' (Advanced Interrupt Architecture Machine " 757 "Level)", []>; 758def FeatureStdExtSsaia 759 : SubtargetFeature<"ssaia", "HasStdExtSsaia", "true", 760 "'Ssaia' (Advanced Interrupt Architecture Supervisor " 761 "Level)", []>; 762 763def FeatureStdExtSmepmp 764 : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", 765 "'Smepmp' (Enhanced Physical Memory Protection)", []>; 766 767def FeatureStdExtSvinval 768 : SubtargetFeature<"svinval", "HasStdExtSvinval", "true", 769 "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">; 770def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">, 771 AssemblerPredicate<(all_of FeatureStdExtSvinval), 772 "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">; 773 774def FeatureStdExtSvnapot 775 : SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true", 776 "'Svnapot' (NAPOT Translation Contiguity)">; 777 778def FeatureStdExtSvpbmt 779 : SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true", 780 "'Svpbmt' (Page-Based Memory Types)">; 781 782//===----------------------------------------------------------------------===// 783// Vendor extensions 784//===----------------------------------------------------------------------===// 785 786// Ventana Extenions 787 788def FeatureVendorXVentanaCondOps 789 : SubtargetFeature<"xventanacondops", "HasVendorXVentanaCondOps", "true", 790 "'XVentanaCondOps' (Ventana Conditional Ops)">; 791def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()">, 792 AssemblerPredicate<(all_of FeatureVendorXVentanaCondOps), 793 "'XVentanaCondOps' (Ventana Conditional Ops)">; 794 795// T-Head Extensions 796 797def FeatureVendorXTHeadBa 798 : SubtargetFeature<"xtheadba", "HasVendorXTHeadBa", "true", 799 "'xtheadba' (T-Head address calculation instructions)">; 800def HasVendorXTHeadBa : Predicate<"Subtarget->hasVendorXTHeadBa()">, 801 AssemblerPredicate<(all_of FeatureVendorXTHeadBa), 802 "'xtheadba' (T-Head address calculation instructions)">; 803 804def FeatureVendorXTHeadBb 805 : SubtargetFeature<"xtheadbb", "HasVendorXTHeadBb", "true", 806 "'xtheadbb' (T-Head basic bit-manipulation instructions)">; 807def HasVendorXTHeadBb : Predicate<"Subtarget->hasVendorXTHeadBb()">, 808 AssemblerPredicate<(all_of FeatureVendorXTHeadBb), 809 "'xtheadbb' (T-Head basic bit-manipulation instructions)">; 810 811def FeatureVendorXTHeadBs 812 : SubtargetFeature<"xtheadbs", "HasVendorXTHeadBs", "true", 813 "'xtheadbs' (T-Head single-bit instructions)">; 814def HasVendorXTHeadBs : Predicate<"Subtarget->hasVendorXTHeadBs()">, 815 AssemblerPredicate<(all_of FeatureVendorXTHeadBs), 816 "'xtheadbs' (T-Head single-bit instructions)">; 817 818def FeatureVendorXTHeadCondMov 819 : SubtargetFeature<"xtheadcondmov", "HasVendorXTHeadCondMov", "true", 820 "'xtheadcondmov' (T-Head conditional move instructions)">; 821def HasVendorXTHeadCondMov : Predicate<"Subtarget->hasVendorXTHeadCondMov()">, 822 AssemblerPredicate<(all_of FeatureVendorXTHeadCondMov), 823 "'xtheadcondmov' (T-Head conditional move instructions)">; 824 825def FeatureVendorXTHeadCmo 826 : SubtargetFeature<"xtheadcmo", "HasVendorXTHeadCmo", "true", 827 "'xtheadcmo' (T-Head cache management instructions)">; 828def HasVendorXTHeadCmo : Predicate<"Subtarget->hasVendorXTHeadCmo()">, 829 AssemblerPredicate<(all_of FeatureVendorXTHeadCmo), 830 "'xtheadcmo' (T-Head cache management instructions)">; 831 832def FeatureVendorXTHeadFMemIdx 833 : SubtargetFeature<"xtheadfmemidx", "HasVendorXTHeadFMemIdx", "true", 834 "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)", 835 [FeatureStdExtF]>; 836def HasVendorXTHeadFMemIdx : Predicate<"Subtarget->hasVendorXTHeadFMemIdx()">, 837 AssemblerPredicate<(all_of FeatureVendorXTHeadFMemIdx), 838 "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)">; 839 840def FeatureVendorXTHeadMac 841 : SubtargetFeature<"xtheadmac", "HasVendorXTHeadMac", "true", 842 "'xtheadmac' (T-Head Multiply-Accumulate Instructions)">; 843def HasVendorXTHeadMac : Predicate<"Subtarget->hasVendorXTHeadMac()">, 844 AssemblerPredicate<(all_of FeatureVendorXTHeadMac), 845 "'xtheadmac' (T-Head Multiply-Accumulate Instructions)">; 846 847def FeatureVendorXTHeadMemIdx 848 : SubtargetFeature<"xtheadmemidx", "HasVendorXTHeadMemIdx", "true", 849 "'xtheadmemidx' (T-Head Indexed Memory Operations)">; 850def HasVendorXTHeadMemIdx : Predicate<"Subtarget->hasVendorXTHeadMemIdx()">, 851 AssemblerPredicate<(all_of FeatureVendorXTHeadMemIdx), 852 "'xtheadmemidx' (T-Head Indexed Memory Operations)">; 853 854def FeatureVendorXTHeadMemPair 855 : SubtargetFeature<"xtheadmempair", "HasVendorXTHeadMemPair", "true", 856 "'xtheadmempair' (T-Head two-GPR Memory Operations)">; 857def HasVendorXTHeadMemPair : Predicate<"Subtarget->hasVendorXTHeadMemPair()">, 858 AssemblerPredicate<(all_of FeatureVendorXTHeadMemPair), 859 "'xtheadmempair' (T-Head two-GPR Memory Operations)">; 860 861def FeatureVendorXTHeadSync 862 : SubtargetFeature<"xtheadsync", "HasVendorXTHeadSync", "true", 863 "'xtheadsync' (T-Head multicore synchronization instructions)">; 864def HasVendorXTHeadSync : Predicate<"Subtarget->hasVendorXTHeadSync()">, 865 AssemblerPredicate<(all_of FeatureVendorXTHeadSync), 866 "'xtheadsync' (T-Head multicore synchronization instructions)">; 867 868def FeatureVendorXTHeadVdot 869 : SubtargetFeature<"xtheadvdot", "HasVendorXTHeadVdot", "true", 870 "'xtheadvdot' (T-Head Vector Extensions for Dot)", 871 [FeatureStdExtV]>; 872def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">, 873 AssemblerPredicate<(all_of FeatureVendorXTHeadVdot), 874 "'xtheadvdot' (T-Head Vector Extensions for Dot)">; 875 876// SiFive Extensions 877 878def FeatureVendorXSfvcp 879 : SubtargetFeature<"xsfvcp", "HasVendorXSfvcp", "true", 880 "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)", 881 [FeatureStdExtZve32x]>; 882def HasVendorXSfvcp : Predicate<"Subtarget->hasVendorXSfvcp()">, 883 AssemblerPredicate<(all_of FeatureVendorXSfvcp), 884 "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)">; 885 886def FeatureVendorXSfvqmaccdod 887 : SubtargetFeature<"xsfvqmaccdod", "HasVendorXSfvqmaccdod", "true", 888 "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))", 889 [FeatureStdExtZve32x]>; 890def HasVendorXSfvqmaccdod 891 : Predicate<"Subtarget->hasVendorXSfvqmaccdod()">, 892 AssemblerPredicate<(all_of FeatureVendorXSfvqmaccdod), 893 "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))">; 894 895def FeatureVendorXSfvqmaccqoq 896 : SubtargetFeature<"xsfvqmaccqoq", "HasVendorXSfvqmaccqoq", "true", 897 "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))", 898 [FeatureStdExtZve32x]>; 899def HasVendorXSfvqmaccqoq 900 : Predicate<"Subtarget->hasVendorXSfvqmaccqoq()">, 901 AssemblerPredicate<(all_of FeatureVendorXSfvqmaccqoq), 902 "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))">; 903 904def FeatureVendorXSfvfwmaccqqq 905 : SubtargetFeature<"xsfvfwmaccqqq", "HasVendorXSfvfwmaccqqq", "true", 906 "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))", 907 [FeatureStdExtZve32f, FeatureStdExtZvfbfmin]>; 908def HasVendorXSfvfwmaccqqq 909 : Predicate<"Subtarget->hasVendorXSfvfwmaccqqq()">, 910 AssemblerPredicate<(all_of FeatureVendorXSfvfwmaccqqq), 911 "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))">; 912 913def FeatureVendorXSfvfnrclipxfqf 914 : SubtargetFeature<"xsfvfnrclipxfqf", "HasVendorXSfvfnrclipxfqf", "true", 915 "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)", 916 [FeatureStdExtZve32f]>; 917def HasVendorXSfvfnrclipxfqf 918 : Predicate<"Subtarget->hasVendorXSfvfnrclipxfqf()">, 919 AssemblerPredicate<(all_of FeatureVendorXSfvfnrclipxfqf), 920 "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)">; 921 922// Core-V Extensions 923 924def FeatureVendorXCVelw 925 : SubtargetFeature<"xcvelw", "HasVendorXCVelw", "true", 926 "'XCVelw' (CORE-V Event Load Word)">; 927def HasVendorXCVelw 928 : Predicate<"Subtarget->hasVendorXCVelw()">, 929 AssemblerPredicate<(any_of FeatureVendorXCVelw), 930 "'XCVelw' (CORE-V Event Load Word)">; 931 932def FeatureVendorXCVbitmanip 933 : SubtargetFeature<"xcvbitmanip", "HasVendorXCVbitmanip", "true", 934 "'XCVbitmanip' (CORE-V Bit Manipulation)">; 935def HasVendorXCVbitmanip 936 : Predicate<"Subtarget->hasVendorXCVbitmanip()">, 937 AssemblerPredicate<(all_of FeatureVendorXCVbitmanip), 938 "'XCVbitmanip' (CORE-V Bit Manipulation)">; 939 940def FeatureVendorXCVmac 941 : SubtargetFeature<"xcvmac", "HasVendorXCVmac", "true", 942 "'XCVmac' (CORE-V Multiply-Accumulate)">; 943def HasVendorXCVmac 944 : Predicate<"Subtarget->hasVendorXCVmac()">, 945 AssemblerPredicate<(all_of FeatureVendorXCVmac), 946 "'XCVmac' (CORE-V Multiply-Accumulate)">; 947 948def FeatureVendorXCVmem 949 : SubtargetFeature<"xcvmem", "HasVendorXCVmem", "true", 950 "'XCVmem' (CORE-V Post-incrementing Load & Store)">; 951def HasVendorXCVmem 952 : Predicate<"Subtarget->hasVendorXCVmem()">, 953 AssemblerPredicate<(any_of FeatureVendorXCVmem), 954 "'XCVmem' (CORE-V Post-incrementing Load & Store)">; 955 956def FeatureVendorXCValu 957 : SubtargetFeature<"xcvalu", "HasVendorXCValu", "true", 958 "'XCValu' (CORE-V ALU Operations)">; 959def HasVendorXCValu 960 : Predicate<"Subtarget->hasVendorXCValu()">, 961 AssemblerPredicate<(all_of FeatureVendorXCValu), 962 "'XCValu' (CORE-V ALU Operations)">; 963 964def FeatureVendorXCVsimd 965 : SubtargetFeature<"xcvsimd", "HasVendorXCvsimd", "true", 966 "'XCVsimd' (CORE-V SIMD ALU)">; 967def HasVendorXCVsimd 968 : Predicate<"Subtarget->hasVendorXCVsimd()">, 969 AssemblerPredicate<(any_of FeatureVendorXCVsimd), 970 "'XCVsimd' (CORE-V SIMD ALU)">; 971 972def FeatureVendorXCVbi 973 : SubtargetFeature<"xcvbi", "HasVendorXCVbi", "true", 974 "'XCVbi' (CORE-V Immediate Branching)">; 975def HasVendorXCVbi 976 : Predicate<"Subtarget->hasVendorXCVbi()">, 977 AssemblerPredicate<(all_of FeatureVendorXCVbi), 978 "'XCVbi' (CORE-V Immediate Branching)">; 979 980//===----------------------------------------------------------------------===// 981// LLVM specific features and extensions 982//===----------------------------------------------------------------------===// 983 984// Feature32Bit exists to mark CPUs that support RV32 to distinquish them from 985// tuning CPU names. 986def Feature32Bit 987 : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">; 988def Feature64Bit 989 : SubtargetFeature<"64bit", "IsRV64", "true", "Implements RV64">; 990def IsRV64 : Predicate<"Subtarget->is64Bit()">, 991 AssemblerPredicate<(all_of Feature64Bit), 992 "RV64I Base Instruction Set">; 993def IsRV32 : Predicate<"!Subtarget->is64Bit()">, 994 AssemblerPredicate<(all_of (not Feature64Bit)), 995 "RV32I Base Instruction Set">; 996 997defvar RV32 = DefaultMode; 998def RV64 : HwMode<"+64bit", [IsRV64]>; 999 1000def FeatureRVE 1001 : SubtargetFeature<"e", "IsRVE", "true", 1002 "Implements RV{32,64}E (provides 16 rather than 32 GPRs)">; 1003def IsRVE : Predicate<"Subtarget->isRVE()">, 1004 AssemblerPredicate<(all_of FeatureRVE)>; 1005 1006def FeatureRelax 1007 : SubtargetFeature<"relax", "EnableLinkerRelax", "true", 1008 "Enable Linker relaxation.">; 1009 1010foreach i = {1-31} in 1011 def FeatureReserveX#i : 1012 SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]", 1013 "true", "Reserve X"#i>; 1014 1015def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore", 1016 "true", "Enable save/restore.">; 1017 1018def FeatureTrailingSeqCstFence : SubtargetFeature<"seq-cst-trailing-fence", 1019 "EnableSeqCstTrailingFence", 1020 "true", 1021 "Enable trailing fence for seq-cst store.">; 1022 1023def FeatureFastUnalignedAccess 1024 : SubtargetFeature<"fast-unaligned-access", "HasFastUnalignedAccess", 1025 "true", "Has reasonably performant unaligned " 1026 "loads and stores (both scalar and vector)">; 1027 1028def FeatureUnalignedScalarMem 1029 : SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem", 1030 "true", "Has reasonably performant unaligned scalar " 1031 "loads and stores">; 1032 1033def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", 1034 "UsePostRAScheduler", "true", "Schedule again after register allocation">; 1035 1036def TuneNoOptimizedZeroStrideLoad 1037 : SubtargetFeature<"no-optimized-zero-stride-load", "HasOptimizedZeroStrideLoad", 1038 "false", "Hasn't optimized (perform fewer memory operations)" 1039 "zero-stride vector load">; 1040 1041def Experimental 1042 : SubtargetFeature<"experimental", "HasExperimental", 1043 "true", "Experimental intrinsics">; 1044 1045// Some vector hardware implementations do not process all VLEN bits in parallel 1046// and instead split over multiple cycles. DLEN refers to the datapath width 1047// that can be done in parallel. 1048def TuneDLenFactor2 1049 : SubtargetFeature<"dlen-factor-2", "DLenFactor2", "true", 1050 "Vector unit DLEN(data path width) is half of VLEN">; 1051 1052def TuneNoDefaultUnroll 1053 : SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false", 1054 "Disable default unroll preference.">; 1055 1056// SiFive 7 is able to fuse integer ALU operations with a preceding branch 1057// instruction. 1058def TuneShortForwardBranchOpt 1059 : SubtargetFeature<"short-forward-branch-opt", "HasShortForwardBranchOpt", 1060 "true", "Enable short forward branch optimization">; 1061def HasShortForwardBranchOpt : Predicate<"Subtarget->hasShortForwardBranchOpt()">; 1062def NoShortForwardBranchOpt : Predicate<"!Subtarget->hasShortForwardBranchOpt()">; 1063 1064def TuneConditionalCompressedMoveFusion 1065 : SubtargetFeature<"conditional-cmv-fusion", "HasConditionalCompressedMoveFusion", 1066 "true", "Enable branch+c.mv fusion">; 1067def HasConditionalMoveFusion : Predicate<"Subtarget->hasConditionalMoveFusion()">; 1068def NoConditionalMoveFusion : Predicate<"!Subtarget->hasConditionalMoveFusion()">; 1069 1070def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7", 1071 "SiFive 7-Series processors", 1072 [TuneNoDefaultUnroll, 1073 TuneShortForwardBranchOpt]>; 1074 1075def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron", 1076 "Ventana Veyron-Series processors">; 1077 1078// Assume that lock-free native-width atomics are available, even if the target 1079// and operating system combination would not usually provide them. The user 1080// is responsible for providing any necessary __sync implementations. Code 1081// built with this feature is not ABI-compatible with code built without this 1082// feature, if atomic variables are exposed across the ABI boundary. 1083def FeatureForcedAtomics : SubtargetFeature< 1084 "forced-atomics", "HasForcedAtomics", "true", 1085 "Assume that lock-free native-width atomics are available">; 1086def HasAtomicLdSt 1087 : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()">; 1088 1089def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", 1090 "AllowTaggedGlobals", 1091 "true", "Use an instruction sequence for taking the address of a global " 1092 "that allows a memory tag in the upper address bits">; 1093