1//===--- P10InstrResources.td - P10 Scheduling Definitions -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// Automatically generated file, do not edit! 9// 10// This file defines the itinerary class data for the POWER10 processor. 11// 12//===----------------------------------------------------------------------===// 13// 22 Cycles Binary Floating Point operations, 2 input operands 14def : InstRW<[P10W_BF_22C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 15 (instrs 16 FDIVS, 17 XSDIVSP 18)>; 19 20// 2-way crack instructions 21// 22 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands 22def : InstRW<[P10W_BF_22C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 23 (instrs 24 FDIVS_rec 25)>; 26 27// 24 Cycles Binary Floating Point operations, 2 input operands 28def : InstRW<[P10W_BF_24C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 29 (instrs 30 XVDIVSP 31)>; 32 33// 26 Cycles Binary Floating Point operations, 1 input operands 34def : InstRW<[P10W_BF_26C, P10W_DISP_ANY, P10BF_Read], 35 (instrs 36 FSQRTS, 37 XSSQRTSP 38)>; 39 40// 2-way crack instructions 41// 26 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands 42def : InstRW<[P10W_BF_26C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 43 (instrs 44 FSQRTS_rec 45)>; 46 47// 27 Cycles Binary Floating Point operations, 1 input operands 48def : InstRW<[P10W_BF_27C, P10W_DISP_ANY, P10BF_Read], 49 (instrs 50 XVSQRTSP 51)>; 52 53// 27 Cycles Binary Floating Point operations, 2 input operands 54def : InstRW<[P10W_BF_27C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 55 (instrs 56 FDIV, 57 XSDIVDP, 58 XVDIVDP 59)>; 60 61// 2-way crack instructions 62// 27 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands 63def : InstRW<[P10W_BF_27C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 64 (instrs 65 FDIV_rec 66)>; 67 68// 36 Cycles Binary Floating Point operations, 1 input operands 69def : InstRW<[P10W_BF_36C, P10W_DISP_ANY, P10BF_Read], 70 (instrs 71 FSQRT, 72 XSSQRTDP, 73 XVSQRTDP 74)>; 75 76// 2-way crack instructions 77// 36 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands 78def : InstRW<[P10W_BF_36C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 79 (instrs 80 FSQRT_rec 81)>; 82 83// 7 Cycles Binary Floating Point operations, 1 input operands 84def : InstRW<[P10W_BF_7C, P10W_DISP_ANY, P10BF_Read], 85 (instrs 86 FCFID, 87 FCFIDS, 88 FCFIDU, 89 FCFIDUS, 90 FCTID, 91 FCTIDU, 92 FCTIDUZ, 93 FCTIDZ, 94 FCTIW, 95 FCTIWU, 96 FCTIWUZ, 97 FCTIWZ, 98 FRE, 99 FRES, 100 FRIMD, FRIMS, 101 FRIND, FRINS, 102 FRIPD, FRIPS, 103 FRIZD, FRIZS, 104 FRSP, 105 FRSQRTE, 106 FRSQRTES, 107 VCFSX, VCFSX_0, 108 VCFUX, VCFUX_0, 109 VCTSXS, VCTSXS_0, 110 VCTUXS, VCTUXS_0, 111 VLOGEFP, 112 VREFP, 113 VRFIM, 114 VRFIN, 115 VRFIP, 116 VRFIZ, 117 VRSQRTEFP, 118 XSCVDPHP, 119 XSCVDPSP, 120 XSCVDPSPN, 121 XSCVDPSXDS, XSCVDPSXDSs, 122 XSCVDPSXWS, XSCVDPSXWSs, 123 XSCVDPUXDS, XSCVDPUXDSs, 124 XSCVDPUXWS, XSCVDPUXWSs, 125 XSCVSPDP, 126 XSCVSXDDP, 127 XSCVSXDSP, 128 XSCVUXDDP, 129 XSCVUXDSP, 130 XSRDPI, 131 XSRDPIC, 132 XSRDPIM, 133 XSRDPIP, 134 XSRDPIZ, 135 XSREDP, 136 XSRESP, 137 XSRSP, 138 XSRSQRTEDP, 139 XSRSQRTESP, 140 XVCVDPSP, 141 XVCVDPSXDS, 142 XVCVDPSXWS, 143 XVCVDPUXDS, 144 XVCVDPUXWS, 145 XVCVSPBF16, 146 XVCVSPDP, 147 XVCVSPHP, 148 XVCVSPSXDS, 149 XVCVSPSXWS, 150 XVCVSPUXDS, 151 XVCVSPUXWS, 152 XVCVSXDDP, 153 XVCVSXDSP, 154 XVCVSXWDP, 155 XVCVSXWSP, 156 XVCVUXDDP, 157 XVCVUXDSP, 158 XVCVUXWDP, 159 XVCVUXWSP, 160 XVRDPI, 161 XVRDPIC, 162 XVRDPIM, 163 XVRDPIP, 164 XVRDPIZ, 165 XVREDP, 166 XVRESP, 167 XVRSPI, 168 XVRSPIC, 169 XVRSPIM, 170 XVRSPIP, 171 XVRSPIZ, 172 XVRSQRTEDP, 173 XVRSQRTESP 174)>; 175 176// 7 Cycles Binary Floating Point operations, 2 input operands 177def : InstRW<[P10W_BF_7C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 178 (instrs 179 FADD, 180 FADDS, 181 FMUL, 182 FMULS, 183 FSUB, 184 FSUBS, 185 VADDFP, 186 VSUBFP, 187 XSADDDP, 188 XSADDSP, 189 XSMULDP, 190 XSMULSP, 191 XSSUBDP, 192 XSSUBSP, 193 XVADDDP, 194 XVADDSP, 195 XVMULDP, 196 XVMULSP, 197 XVSUBDP, 198 XVSUBSP 199)>; 200 201// 7 Cycles Binary Floating Point operations, 3 input operands 202def : InstRW<[P10W_BF_7C, P10W_DISP_ANY, P10BF_Read, P10BF_Read, P10BF_Read], 203 (instrs 204 FMADD, 205 FMADDS, 206 FMSUB, 207 FMSUBS, 208 FNMADD, 209 FNMADDS, 210 FNMSUB, 211 FNMSUBS, 212 FSELD, FSELS, 213 VMADDFP, 214 VNMSUBFP, 215 XSMADDADP, 216 XSMADDASP, 217 XSMADDMDP, 218 XSMADDMSP, 219 XSMSUBADP, 220 XSMSUBASP, 221 XSMSUBMDP, 222 XSMSUBMSP, 223 XSNMADDADP, 224 XSNMADDASP, 225 XSNMADDMDP, 226 XSNMADDMSP, 227 XSNMSUBADP, 228 XSNMSUBASP, 229 XSNMSUBMDP, 230 XSNMSUBMSP, 231 XVMADDADP, 232 XVMADDASP, 233 XVMADDMDP, 234 XVMADDMSP, 235 XVMSUBADP, 236 XVMSUBASP, 237 XVMSUBMDP, 238 XVMSUBMSP, 239 XVNMADDADP, 240 XVNMADDASP, 241 XVNMADDMDP, 242 XVNMADDMSP, 243 XVNMSUBADP, 244 XVNMSUBASP, 245 XVNMSUBMDP, 246 XVNMSUBMSP 247)>; 248 249// 2-way crack instructions 250// 7 Cycles Binary Floating Point operations, and 7 Cycles Binary Floating Point operations, 1 input operands 251def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_BF_7C, P10W_DISP_ANY, P10BF_Read], 252 (instrs 253 VEXPTEFP 254)>; 255 256// 2-way crack instructions 257// 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands 258def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 259 (instrs 260 FADD_rec, 261 FADDS_rec, 262 FMUL_rec, 263 FMULS_rec, 264 FSUB_rec, 265 FSUBS_rec 266)>; 267 268// 2-way crack instructions 269// 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands 270def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 271 (instrs 272 FCFID_rec, 273 FCFIDS_rec, 274 FCFIDU_rec, 275 FCFIDUS_rec, 276 FCTID_rec, 277 FCTIDU_rec, 278 FCTIDUZ_rec, 279 FCTIDZ_rec, 280 FCTIW_rec, 281 FCTIWU_rec, 282 FCTIWUZ_rec, 283 FCTIWZ_rec, 284 FRE_rec, 285 FRES_rec, 286 FRIMD_rec, FRIMS_rec, 287 FRIND_rec, FRINS_rec, 288 FRIPD_rec, FRIPS_rec, 289 FRIZD_rec, FRIZS_rec, 290 FRSP_rec, 291 FRSQRTE_rec, 292 FRSQRTES_rec 293)>; 294 295// 2-way crack instructions 296// 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 3 input operands 297def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 298 (instrs 299 FMADD_rec, 300 FMADDS_rec, 301 FMSUB_rec, 302 FMSUBS_rec, 303 FNMADD_rec, 304 FNMADDS_rec, 305 FNMSUB_rec, 306 FNMSUBS_rec, 307 FSELD_rec, FSELS_rec 308)>; 309 310// 2 Cycles Branch operations, 0 input operands 311def : InstRW<[P10W_BR_2C, P10W_DISP_ANY], 312 (instrs 313 BCLR, BCLRn, BDNZLR, BDNZLR8, BDNZLRm, BDNZLRp, BDZLR, BDZLR8, BDZLRm, BDZLRp, gBCLR, 314 BCLRL, BCLRLn, BDNZLRL, BDNZLRLm, BDNZLRLp, BDZLRL, BDZLRLm, BDZLRLp, gBCLRL, 315 BL, BL8, BL8_NOP, BL8_NOP_RM, BL8_NOP_TLS, BL8_NOTOC, BL8_NOTOC_RM, BL8_NOTOC_TLS, BL8_RM, BL8_TLS, BL8_TLS_, BLR, BLR8, BLRL, BL_NOP, BL_NOP_RM, BL_RM, BL_TLS 316)>; 317 318// 2 Cycles Branch operations, 1 input operands 319def : InstRW<[P10W_BR_2C, P10W_DISP_ANY, P10BR_Read], 320 (instrs 321 B, BCC, BCCA, BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL, BCCLA, BCCLR, BCCLRL, CTRL_DEP, TAILB, TAILB8, 322 BA, TAILBA, TAILBA8, 323 BC, BCTR, BCTR8, BCTRL, BCTRL8, BCTRL8_LDinto_toc, BCTRL8_LDinto_toc_RM, BCTRL8_RM, BCTRL_LWZinto_toc, BCTRL_LWZinto_toc_RM, BCTRL_RM, BCn, BDNZ, BDNZ8, BDNZm, BDNZp, BDZ, BDZ8, BDZm, BDZp, TAILBCTR, TAILBCTR8, gBC, gBCat, 324 BCL, BCLalways, BCLn, BDNZL, BDNZLm, BDNZLp, BDZL, BDZLm, BDZLp, gBCL, gBCLat, 325 BLA, BLA8, BLA8_NOP, BLA8_NOP_RM, BLA8_RM, BLA_RM 326)>; 327 328// 2 Cycles Branch operations, 3 input operands 329def : InstRW<[P10W_BR_2C, P10W_DISP_ANY, P10BR_Read, P10BR_Read, P10BR_Read], 330 (instrs 331 BCCTR, BCCTR8, BCCTR8n, BCCTRn, gBCCTR, 332 BCCTRL, BCCTRL8, BCCTRL8n, BCCTRLn, gBCCTRL 333)>; 334 335// 2 Cycles Branch operations, 4 input operands 336def : InstRW<[P10W_BR_2C, P10W_DISP_ANY, P10BR_Read, P10BR_Read, P10BR_Read, P10BR_Read], 337 (instrs 338 BDNZA, BDNZAm, BDNZAp, BDZA, BDZAm, BDZAp, gBCA, gBCAat, 339 BDNZLA, BDNZLAm, BDNZLAp, BDZLA, BDZLAm, BDZLAp, gBCLA, gBCLAat 340)>; 341 342// 7 Cycles Crypto operations, 1 input operands 343def : InstRW<[P10W_CY_7C, P10W_DISP_ANY, P10CY_Read], 344 (instrs 345 VSBOX 346)>; 347 348// 7 Cycles Crypto operations, 2 input operands 349def : InstRW<[P10W_CY_7C, P10W_DISP_ANY, P10CY_Read, P10CY_Read], 350 (instrs 351 CFUGED, 352 CNTLZDM, 353 CNTTZDM, 354 PDEPD, 355 PEXTD, 356 VCFUGED, 357 VCIPHER, 358 VCIPHERLAST, 359 VCLZDM, 360 VCTZDM, 361 VGNB, 362 VNCIPHER, 363 VNCIPHERLAST, 364 VPDEPD, 365 VPEXTD, 366 VPMSUMB, 367 VPMSUMD, 368 VPMSUMH, 369 VPMSUMW 370)>; 371 372// 13 Cycles Decimal Floating Point operations, 1 input operands 373def : InstRW<[P10W_DF_13C, P10W_DISP_ANY, P10DF_Read], 374 (instrs 375 XSCVDPQP, 376 XSCVQPDP, 377 XSCVQPDPO, 378 XSCVQPSDZ, 379 XSCVQPSQZ, 380 XSCVQPSWZ, 381 XSCVQPUDZ, 382 XSCVQPUQZ, 383 XSCVQPUWZ, 384 XSCVSDQP, 385 XSCVSQQP, 386 XSCVUDQP, 387 XSCVUQQP 388)>; 389 390// 13 Cycles Decimal Floating Point operations, 2 input operands 391def : InstRW<[P10W_DF_13C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 392 (instrs 393 XSADDQP, 394 XSADDQPO, 395 XSSUBQP, 396 XSSUBQPO 397)>; 398 399// 13 Cycles Decimal Floating Point operations, 3 input operands 400def : InstRW<[P10W_DF_13C, P10W_DISP_ANY, P10DF_Read, P10DF_Read, P10DF_Read], 401 (instrs 402 BCDSR_rec, 403 XSRQPI, 404 XSRQPIX, 405 XSRQPXP 406)>; 407 408// 2-way crack instructions 409// 13 Cycles Decimal Floating Point operations, and 3 Cycles Store operations, 2 input operands 410def : InstRW<[P10W_DF_13C, P10W_DISP_EVEN, P10W_ST_3C, P10W_DISP_ANY], 411 (instrs 412 HASHST, HASHST8, 413 HASHSTP, HASHSTP8 414)>; 415 416// 24 Cycles Decimal Floating Point operations, 1 input operands 417def : InstRW<[P10W_DF_24C, P10W_DISP_ANY, P10DF_Read], 418 (instrs 419 BCDCTSQ_rec 420)>; 421 422// 25 Cycles Decimal Floating Point operations, 2 input operands 423def : InstRW<[P10W_DF_25C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 424 (instrs 425 XSMULQP, 426 XSMULQPO 427)>; 428 429// 25 Cycles Decimal Floating Point operations, 3 input operands 430def : InstRW<[P10W_DF_25C, P10W_DISP_ANY, P10DF_Read, P10DF_Read, P10DF_Read], 431 (instrs 432 XSMADDQP, 433 XSMADDQPO, 434 XSMSUBQP, 435 XSMSUBQPO, 436 XSNMADDQP, 437 XSNMADDQPO, 438 XSNMSUBQP, 439 XSNMSUBQPO 440)>; 441 442// 38 Cycles Decimal Floating Point operations, 2 input operands 443def : InstRW<[P10W_DF_38C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 444 (instrs 445 BCDCFSQ_rec 446)>; 447 448// 59 Cycles Decimal Floating Point operations, 2 input operands 449def : InstRW<[P10W_DF_59C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 450 (instrs 451 XSDIVQP, 452 XSDIVQPO 453)>; 454 455// 61 Cycles Decimal Floating Point operations, 2 input operands 456def : InstRW<[P10W_DF_61C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 457 (instrs 458 VDIVESQ, 459 VDIVEUQ, 460 VDIVSQ, 461 VDIVUQ 462)>; 463 464// 68 Cycles Decimal Floating Point operations, 2 input operands 465def : InstRW<[P10W_DF_68C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 466 (instrs 467 VMODSQ, 468 VMODUQ 469)>; 470 471// 77 Cycles Decimal Floating Point operations, 1 input operands 472def : InstRW<[P10W_DF_77C, P10W_DISP_ANY, P10DF_Read], 473 (instrs 474 XSSQRTQP, 475 XSSQRTQPO 476)>; 477 478// 20 Cycles Scalar Fixed-Point Divide operations, 2 input operands 479def : InstRW<[P10W_DV_20C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 480 (instrs 481 DIVW, 482 DIVWO, 483 DIVWU, 484 DIVWUO, 485 MODSW 486)>; 487 488// 2-way crack instructions 489// 20 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands 490def : InstRW<[P10W_DV_20C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 491 (instrs 492 DIVW_rec, 493 DIVWO_rec, 494 DIVWU_rec, 495 DIVWUO_rec 496)>; 497 498// 25 Cycles Scalar Fixed-Point Divide operations, 2 input operands 499def : InstRW<[P10W_DV_25C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 500 (instrs 501 DIVD, 502 DIVDO, 503 DIVDU, 504 DIVDUO, 505 DIVWE, 506 DIVWEO, 507 DIVWEU, 508 DIVWEUO 509)>; 510 511// 2-way crack instructions 512// 25 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands 513def : InstRW<[P10W_DV_25C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 514 (instrs 515 DIVD_rec, 516 DIVDO_rec, 517 DIVDU_rec, 518 DIVDUO_rec, 519 DIVWE_rec, 520 DIVWEO_rec, 521 DIVWEU_rec, 522 DIVWEUO_rec 523)>; 524 525// 27 Cycles Scalar Fixed-Point Divide operations, 2 input operands 526def : InstRW<[P10W_DV_27C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 527 (instrs 528 MODSD, 529 MODUD, 530 MODUW 531)>; 532 533// 41 Cycles Scalar Fixed-Point Divide operations, 2 input operands 534def : InstRW<[P10W_DV_41C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 535 (instrs 536 DIVDE, 537 DIVDEO, 538 DIVDEU, 539 DIVDEUO 540)>; 541 542// 2-way crack instructions 543// 41 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands 544def : InstRW<[P10W_DV_41C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 545 (instrs 546 DIVDE_rec, 547 DIVDEO_rec, 548 DIVDEU_rec, 549 DIVDEUO_rec 550)>; 551 552// 43 Cycles Scalar Fixed-Point Divide operations, 2 input operands 553def : InstRW<[P10W_DV_43C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 554 (instrs 555 VDIVSD, 556 VDIVUD 557)>; 558 559// 47 Cycles Scalar Fixed-Point Divide operations, 2 input operands 560def : InstRW<[P10W_DV_47C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 561 (instrs 562 VMODSD, 563 VMODUD 564)>; 565 566// 54 Cycles Scalar Fixed-Point Divide operations, 2 input operands 567def : InstRW<[P10W_DV_54C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 568 (instrs 569 VDIVSW, 570 VDIVUW 571)>; 572 573// 60 Cycles Scalar Fixed-Point Divide operations, 2 input operands 574def : InstRW<[P10W_DV_60C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 575 (instrs 576 VMODSW, 577 VMODUW 578)>; 579 580// 75 Cycles Scalar Fixed-Point Divide operations, 2 input operands 581def : InstRW<[P10W_DV_75C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 582 (instrs 583 VDIVESD, 584 VDIVEUD 585)>; 586 587// 83 Cycles Scalar Fixed-Point Divide operations, 2 input operands 588def : InstRW<[P10W_DV_83C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 589 (instrs 590 VDIVESW, 591 VDIVEUW 592)>; 593 594// 5 Cycles Fixed-Point and BCD operations, 1 input operands 595def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read], 596 (instrs 597 BCDCTN_rec, 598 VMUL10CUQ, 599 VMUL10UQ, 600 XSXSIGQP 601)>; 602 603// 5 Cycles Fixed-Point and BCD operations, 2 input operands 604def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read, P10DX_Read], 605 (instrs 606 BCDCFN_rec, 607 BCDCFZ_rec, 608 BCDCPSGN_rec, 609 BCDCTZ_rec, 610 BCDSETSGN_rec, 611 BCDUS_rec, 612 BCDUTRUNC_rec, 613 VADDCUQ, 614 VADDUQM, 615 VMUL10ECUQ, 616 VMUL10EUQ, 617 VSUBCUQ, 618 VSUBUQM, 619 XSCMPEQQP, 620 XSCMPEXPQP, 621 XSCMPGEQP, 622 XSCMPGTQP, 623 XSCMPOQP, 624 XSCMPUQP, 625 XSMAXCQP, 626 XSMINCQP, 627 XSTSTDCQP, 628 XXGENPCVBM 629)>; 630 631// 5 Cycles Fixed-Point and BCD operations, 3 input operands 632def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read, P10DX_Read, P10DX_Read], 633 (instrs 634 BCDADD_rec, 635 BCDS_rec, 636 BCDSUB_rec, 637 BCDTRUNC_rec, 638 VADDECUQ, 639 VADDEUQM, 640 VSUBECUQ, 641 VSUBEUQM 642)>; 643 644// 4 Cycles ALU2 operations, 0 input operands 645def : InstRW<[P10W_F2_4C, P10W_DISP_ANY], 646 (instrs 647 TRAP, TW 648)>; 649 650// 4 Cycles ALU2 operations, 1 input operands 651def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read], 652 (instrs 653 CNTLZD, 654 CNTLZD_rec, 655 CNTLZW, CNTLZW8, 656 CNTLZW8_rec, CNTLZW_rec, 657 CNTTZD, 658 CNTTZD_rec, 659 CNTTZW, CNTTZW8, 660 CNTTZW8_rec, CNTTZW_rec, 661 FTSQRT, 662 MTVSRBM, 663 MTVSRBMI, 664 MTVSRDM, 665 MTVSRHM, 666 MTVSRQM, 667 MTVSRWM, 668 POPCNTB, POPCNTB8, 669 POPCNTD, 670 POPCNTW, 671 VCLZB, 672 VCLZD, 673 VCLZH, 674 VCLZW, 675 VCTZB, 676 VCTZD, 677 VCTZH, 678 VCTZW, 679 VEXPANDBM, 680 VEXPANDDM, 681 VEXPANDHM, 682 VEXPANDQM, 683 VEXPANDWM, 684 VEXTRACTBM, 685 VEXTRACTDM, 686 VEXTRACTHM, 687 VEXTRACTQM, 688 VEXTRACTWM, 689 VPOPCNTB, 690 VPOPCNTD, 691 VPOPCNTH, 692 VPOPCNTW, 693 VPRTYBD, 694 VPRTYBW, 695 XSCVHPDP, 696 XSCVSPDPN, 697 XSTSQRTDP, 698 XVCVHPSP, 699 XVTLSBB, 700 XVTSQRTDP, 701 XVTSQRTSP 702)>; 703 704// 4 Cycles ALU2 operations, 2 input operands 705def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read], 706 (instrs 707 CMPEQB, 708 EXTSWSLI_32_64_rec, EXTSWSLI_rec, 709 FCMPOD, FCMPOS, 710 FCMPUD, FCMPUS, 711 FTDIV, 712 SLD_rec, 713 SLW8_rec, SLW_rec, 714 SRD_rec, 715 SRW8_rec, SRW_rec, 716 VABSDUB, 717 VABSDUH, 718 VABSDUW, 719 VADDCUW, 720 VADDSBS, 721 VADDSHS, 722 VADDSWS, 723 VADDUBS, 724 VADDUHS, 725 VADDUWS, 726 VAVGSB, 727 VAVGSH, 728 VAVGSW, 729 VAVGUB, 730 VAVGUH, 731 VAVGUW, 732 VCMPBFP, 733 VCMPBFP_rec, 734 VCMPEQFP, 735 VCMPEQFP_rec, 736 VCMPEQUB_rec, 737 VCMPEQUD_rec, 738 VCMPEQUH_rec, 739 VCMPEQUQ, 740 VCMPEQUQ_rec, 741 VCMPEQUW_rec, 742 VCMPGEFP, 743 VCMPGEFP_rec, 744 VCMPGTFP, 745 VCMPGTFP_rec, 746 VCMPGTSB_rec, 747 VCMPGTSD_rec, 748 VCMPGTSH_rec, 749 VCMPGTSQ, 750 VCMPGTSQ_rec, 751 VCMPGTSW_rec, 752 VCMPGTUB_rec, 753 VCMPGTUD_rec, 754 VCMPGTUH_rec, 755 VCMPGTUQ, 756 VCMPGTUQ_rec, 757 VCMPGTUW_rec, 758 VCMPNEB_rec, 759 VCMPNEH_rec, 760 VCMPNEW_rec, 761 VCMPNEZB_rec, 762 VCMPNEZH_rec, 763 VCMPNEZW_rec, 764 VCMPSQ, 765 VCMPUQ, 766 VCNTMBB, 767 VCNTMBD, 768 VCNTMBH, 769 VCNTMBW, 770 VMAXFP, 771 VMINFP, 772 VSUBCUW, 773 VSUBSBS, 774 VSUBSHS, 775 VSUBSWS, 776 VSUBUBS, 777 VSUBUHS, 778 VSUBUWS, 779 XSCMPEQDP, 780 XSCMPEXPDP, 781 XSCMPGEDP, 782 XSCMPGTDP, 783 XSCMPODP, 784 XSCMPUDP, 785 XSMAXCDP, 786 XSMAXDP, 787 XSMAXJDP, 788 XSMINCDP, 789 XSMINDP, 790 XSMINJDP, 791 XSTDIVDP, 792 XSTSTDCDP, 793 XSTSTDCSP, 794 XVCMPEQDP, 795 XVCMPEQDP_rec, 796 XVCMPEQSP, 797 XVCMPEQSP_rec, 798 XVCMPGEDP, 799 XVCMPGEDP_rec, 800 XVCMPGESP, 801 XVCMPGESP_rec, 802 XVCMPGTDP, 803 XVCMPGTDP_rec, 804 XVCMPGTSP, 805 XVCMPGTSP_rec, 806 XVMAXDP, 807 XVMAXSP, 808 XVMINDP, 809 XVMINSP, 810 XVTDIVDP, 811 XVTDIVSP, 812 XVTSTDCDP, 813 XVTSTDCSP 814)>; 815 816// 4 Cycles ALU2 operations, 3 input operands 817def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read, P10F2_Read], 818 (instrs 819 CMPRB, CMPRB8, 820 RLDCL_rec, 821 RLDCR_rec, 822 RLDIC_rec, 823 RLDICL_32_rec, RLDICL_rec, 824 RLDICR_rec, 825 TD, 826 TDI, 827 TWI, 828 VSHASIGMAD, 829 VSHASIGMAW 830)>; 831 832// 4 Cycles ALU2 operations, 4 input operands 833def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read, P10F2_Read, P10F2_Read], 834 (instrs 835 RLDIMI_rec, 836 RLWINM8_rec, RLWINM_rec, 837 RLWNM8_rec, RLWNM_rec 838)>; 839 840// 4 Cycles ALU2 operations, 5 input operands 841def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read, P10F2_Read, P10F2_Read, P10F2_Read], 842 (instrs 843 RLWIMI8_rec, RLWIMI_rec 844)>; 845 846// Single crack instructions 847// 4 Cycles ALU2 operations, 2 input operands 848def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_DISP_ANY, P10F2_Read, P10F2_Read], 849 (instrs 850 SRAD_rec, 851 SRADI_rec, 852 SRAW_rec, 853 SRAWI_rec 854)>; 855 856// Single crack instructions 857// 4 Cycles ALU2 operations, 3 input operands 858def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_DISP_ANY, P10F2_Read, P10F2_Read, P10F2_Read], 859 (instrs 860 TABORTDC, 861 TABORTDCI, 862 TABORTWC, 863 TABORTWCI 864)>; 865 866// 2-way crack instructions 867// 4 Cycles ALU2 operations, and 4 Cycles Permute operations, 2 input operands 868def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_PM_4C, P10W_DISP_ANY], 869 (instrs 870 VRLQ, 871 VRLQNM, 872 VSLQ, 873 VSRAQ, 874 VSRQ 875)>; 876 877// 2-way crack instructions 878// 4 Cycles ALU2 operations, and 4 Cycles Permute operations, 3 input operands 879def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_PM_4C, P10W_DISP_ANY], 880 (instrs 881 VRLQMI 882)>; 883 884// 2-way crack instructions 885// 4 Cycles ALU2 operations, and 4 Cycles ALU2 operations, 0 input operands 886def : InstRW<[P10W_F2_4C, P10W_DISP_PAIR, P10W_F2_4C], 887 (instrs 888 MFCR, MFCR8 889)>; 890 891// 2 Cycles ALU operations, 1 input operands 892def : InstRW<[P10W_FX_2C, P10W_DISP_ANY, P10FX_Read], 893 (instrs 894 MTCTR, MTCTR8, MTCTR8loop, MTCTRloop, 895 MTLR, MTLR8 896)>; 897 898// 3 Cycles ALU operations, 0 input operands 899def : InstRW<[P10W_FX_3C, P10W_DISP_ANY], 900 (instrs 901 CR6SET, CREQV, CRSET, 902 DSS, DSSALL, 903 MCRXRX, 904 MFCTR, MFCTR8, 905 MFLR, MFLR8, 906 NOP, NOP_GT_PWR6, NOP_GT_PWR7, ORI, ORI8, 907 VXOR, V_SET0, V_SET0B, V_SET0H, 908 XXLEQV, XXLEQVOnes, 909 XXLXOR, XXLXORdpz, XXLXORspz, XXLXORz 910)>; 911 912// 3 Cycles ALU operations, 1 input operands 913def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read], 914 (instrs 915 ADDI, ADDI8, ADDIdtprelL32, ADDItlsldLADDR32, ADDItocL, LI, LI8, 916 ADDIS, ADDIS8, ADDISdtprelHA32, ADDIStocHA, ADDIStocHA8, LIS, LIS8, 917 ADDME, ADDME8, 918 ADDME8O, ADDMEO, 919 ADDZE, ADDZE8, 920 ADDZE8O, ADDZEO, 921 EXTSB, EXTSB8, EXTSB8_32_64, 922 EXTSB8_rec, EXTSB_rec, 923 EXTSH, EXTSH8, EXTSH8_32_64, 924 EXTSH8_rec, EXTSH_rec, 925 EXTSW, EXTSW_32, EXTSW_32_64, 926 EXTSW_32_64_rec, EXTSW_rec, 927 FABSD, FABSS, 928 FMR, 929 FNABSD, FNABSS, 930 FNEGD, FNEGS, 931 MCRF, 932 MFOCRF, MFOCRF8, 933 MFVRD, MFVSRD, 934 MFVRWZ, MFVSRWZ, 935 MTOCRF, MTOCRF8, 936 MTVRD, MTVSRD, 937 MTVRWA, MTVSRWA, 938 MTVRWZ, MTVSRWZ, 939 NEG, NEG8, 940 NEG8_rec, NEG_rec, 941 NEG8O, NEGO, 942 SETB, SETB8, 943 SETBC, SETBC8, 944 SETBCR, SETBCR8, 945 SETNBC, SETNBC8, 946 SETNBCR, SETNBCR8, 947 SUBFME, SUBFME8, 948 SUBFME8O, SUBFMEO, 949 SUBFZE, SUBFZE8, 950 SUBFZE8O, SUBFZEO, 951 VEXTSB2D, VEXTSB2Ds, 952 VEXTSB2W, VEXTSB2Ws, 953 VEXTSD2Q, 954 VEXTSH2D, VEXTSH2Ds, 955 VEXTSH2W, VEXTSH2Ws, 956 VEXTSW2D, VEXTSW2Ds, 957 VNEGD, 958 VNEGW, 959 WAIT, 960 XSABSDP, 961 XSABSQP, 962 XSNABSDP, XSNABSDPs, 963 XSNABSQP, 964 XSNEGDP, 965 XSNEGQP, 966 XSXEXPDP, 967 XSXEXPQP, 968 XSXSIGDP, 969 XVABSDP, 970 XVABSSP, 971 XVNABSDP, 972 XVNABSSP, 973 XVNEGDP, 974 XVNEGSP, 975 XVXEXPDP, 976 XVXEXPSP, 977 XVXSIGDP, 978 XVXSIGSP 979)>; 980 981// 3 Cycles ALU operations, 2 input operands 982def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 983 (instrs 984 ADD4, ADD4TLS, ADD8, ADD8TLS, ADD8TLS_, 985 ADD4_rec, ADD8_rec, 986 ADDE, ADDE8, 987 ADDE8O, ADDEO, 988 ADDIC, ADDIC8, 989 ADD4O, ADD8O, 990 AND, AND8, 991 AND8_rec, AND_rec, 992 ANDC, ANDC8, 993 ANDC8_rec, ANDC_rec, 994 ANDI8_rec, ANDI_rec, 995 ANDIS8_rec, ANDIS_rec, 996 CMPD, CMPW, 997 CMPB, CMPB8, 998 CMPDI, CMPWI, 999 CMPLD, CMPLW, 1000 CMPLDI, CMPLWI, 1001 CRAND, 1002 CRANDC, 1003 CRNAND, 1004 CRNOR, 1005 CROR, 1006 CRORC, 1007 CR6UNSET, CRUNSET, CRXOR, 1008 EQV, EQV8, 1009 EQV8_rec, EQV_rec, 1010 EXTSWSLI, EXTSWSLI_32_64, 1011 FCPSGND, FCPSGNS, 1012 NAND, NAND8, 1013 NAND8_rec, NAND_rec, 1014 NOR, NOR8, 1015 NOR8_rec, NOR_rec, 1016 COPY, OR, OR8, 1017 OR8_rec, OR_rec, 1018 ORC, ORC8, 1019 ORC8_rec, ORC_rec, 1020 ORIS, ORIS8, 1021 SLD, 1022 SLW, SLW8, 1023 SRAD, 1024 SRADI, SRADI_32, 1025 SRAW, 1026 SRAWI, 1027 SRD, 1028 SRW, SRW8, 1029 SUBF, SUBF8, 1030 SUBF8_rec, SUBF_rec, 1031 SUBFE, SUBFE8, 1032 SUBFE8O, SUBFEO, 1033 SUBFIC, SUBFIC8, 1034 SUBF8O, SUBFO, 1035 VADDUBM, 1036 VADDUDM, 1037 VADDUHM, 1038 VADDUWM, 1039 VAND, 1040 VANDC, 1041 VCMPEQUB, 1042 VCMPEQUD, 1043 VCMPEQUH, 1044 VCMPEQUW, 1045 VCMPGTSB, 1046 VCMPGTSD, 1047 VCMPGTSH, 1048 VCMPGTSW, 1049 VCMPGTUB, 1050 VCMPGTUD, 1051 VCMPGTUH, 1052 VCMPGTUW, 1053 VCMPNEB, 1054 VCMPNEH, 1055 VCMPNEW, 1056 VCMPNEZB, 1057 VCMPNEZH, 1058 VCMPNEZW, 1059 VEQV, 1060 VMAXSB, 1061 VMAXSD, 1062 VMAXSH, 1063 VMAXSW, 1064 VMAXUB, 1065 VMAXUD, 1066 VMAXUH, 1067 VMAXUW, 1068 VMINSB, 1069 VMINSD, 1070 VMINSH, 1071 VMINSW, 1072 VMINUB, 1073 VMINUD, 1074 VMINUH, 1075 VMINUW, 1076 VMRGEW, 1077 VMRGOW, 1078 VNAND, 1079 VNOR, 1080 VOR, 1081 VORC, 1082 VRLB, 1083 VRLD, 1084 VRLDNM, 1085 VRLH, 1086 VRLW, 1087 VRLWNM, 1088 VSLB, 1089 VSLD, 1090 VSLH, 1091 VSLW, 1092 VSRAB, 1093 VSRAD, 1094 VSRAH, 1095 VSRAW, 1096 VSRB, 1097 VSRD, 1098 VSRH, 1099 VSRW, 1100 VSUBUBM, 1101 VSUBUDM, 1102 VSUBUHM, 1103 VSUBUWM, 1104 XOR, XOR8, 1105 XOR8_rec, XOR_rec, 1106 XORI, XORI8, 1107 XORIS, XORIS8, 1108 XSCPSGNDP, 1109 XSCPSGNQP, 1110 XSIEXPDP, 1111 XSIEXPQP, 1112 XVCPSGNDP, 1113 XVCPSGNSP, 1114 XVIEXPDP, 1115 XVIEXPSP, 1116 XXLAND, 1117 XXLANDC, 1118 XXLNAND, 1119 XXLNOR, 1120 XXLOR, XXLORf, 1121 XXLORC 1122)>; 1123 1124// 3 Cycles ALU operations, 3 input operands 1125def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read, P10FX_Read], 1126 (instrs 1127 ADDEX, ADDEX8, 1128 DST, DST64, DSTT, DSTT64, 1129 DSTST, DSTST64, DSTSTT, DSTSTT64, 1130 ISEL, ISEL8, 1131 RLDCL, 1132 RLDCR, 1133 RLDIC, 1134 RLDICL, RLDICL_32, RLDICL_32_64, 1135 RLDICR, RLDICR_32, 1136 VRLDMI, 1137 VRLWMI, 1138 VSEL, 1139 XXSEL 1140)>; 1141 1142// 3 Cycles ALU operations, 4 input operands 1143def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read, P10FX_Read, P10FX_Read], 1144 (instrs 1145 RLDIMI, 1146 RLWINM, RLWINM8, 1147 RLWNM, RLWNM8 1148)>; 1149 1150// 3 Cycles ALU operations, 5 input operands 1151def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read, P10FX_Read, P10FX_Read, P10FX_Read], 1152 (instrs 1153 RLWIMI, RLWIMI8 1154)>; 1155 1156// Single crack instructions 1157// 3 Cycles ALU operations, 0 input operands 1158def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_DISP_ANY], 1159 (instrs 1160 MFFS, 1161 MFFS_rec, 1162 MFFSL, 1163 MFVSCR, 1164 TRECHKPT 1165)>; 1166 1167// Single crack instructions 1168// 3 Cycles ALU operations, 1 input operands 1169def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10FX_Read], 1170 (instrs 1171 ADDME8_rec, ADDME_rec, 1172 ADDME8O_rec, ADDMEO_rec, 1173 ADDZE8_rec, ADDZE_rec, 1174 ADDZE8O_rec, ADDZEO_rec, 1175 MCRFS, 1176 MFFSCDRN, 1177 MFFSCDRNI, 1178 MFFSCRN, 1179 MFFSCRNI, 1180 MTFSB0, 1181 MTVSCR, 1182 NEG8O_rec, NEGO_rec, 1183 SUBFME8_rec, SUBFME_rec, 1184 SUBFME8O_rec, SUBFMEO_rec, 1185 SUBFZE8_rec, SUBFZE_rec, 1186 SUBFZE8O_rec, SUBFZEO_rec, 1187 TABORT, 1188 TBEGIN, 1189 TRECLAIM, 1190 TSR 1191)>; 1192 1193// Single crack instructions 1194// 3 Cycles ALU operations, 2 input operands 1195def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 1196 (instrs 1197 ADDE8_rec, ADDE_rec, 1198 ADDE8O_rec, ADDEO_rec, 1199 ADDIC_rec, 1200 ADD4O_rec, ADD8O_rec, 1201 SUBFE8_rec, SUBFE_rec, 1202 SUBFE8O_rec, SUBFEO_rec, 1203 SUBF8O_rec, SUBFO_rec 1204)>; 1205 1206// 2-way crack instructions 1207// 3 Cycles ALU operations, and 3 Cycles ALU operations, 0 input operands 1208def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1209 (instrs 1210 HRFID, 1211 MFFSCE, 1212 RFID, 1213 STOP 1214)>; 1215 1216// 2-way crack instructions 1217// 3 Cycles ALU operations, and 3 Cycles ALU operations, 1 input operands 1218def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read], 1219 (instrs 1220 FABSD_rec, FABSS_rec, 1221 FMR_rec, 1222 FNABSD_rec, FNABSS_rec, 1223 FNEGD_rec, FNEGS_rec, 1224 MTFSB1, 1225 RFEBB, 1226 SC 1227)>; 1228 1229// 2-way crack instructions 1230// 3 Cycles ALU operations, and 3 Cycles ALU operations, 2 input operands 1231def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 1232 (instrs 1233 ADDC, ADDC8, 1234 ADDC8_rec, ADDC_rec, 1235 ADDC8O, ADDCO, 1236 FCPSGND_rec, FCPSGNS_rec, 1237 MTFSF, MTFSFb, 1238 MTFSFI, MTFSFIb, 1239 SUBFC, SUBFC8, 1240 SUBFC8_rec, SUBFC_rec, 1241 SUBFC8O, SUBFCO 1242)>; 1243 1244// 2-way crack instructions 1245// 3 Cycles ALU operations, and 3 Cycles ALU operations, 3 input operands 1246def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read, P10FX_Read], 1247 (instrs 1248 MTFSFI_rec 1249)>; 1250 1251// 2-way crack instructions 1252// 3 Cycles ALU operations, and 3 Cycles ALU operations, 4 input operands 1253def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read, P10FX_Read, P10FX_Read], 1254 (instrs 1255 MTFSF_rec 1256)>; 1257 1258// 4-way crack instructions 1259// 3 Cycles ALU operations, 3 Cycles ALU operations, 3 Cycles ALU operations, and 3 Cycles ALU operations, 2 input operands 1260def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 1261 (instrs 1262 ADDC8O_rec, ADDCO_rec, 1263 SUBFC8O_rec, SUBFCO_rec 1264)>; 1265 1266// 2-way crack instructions 1267// 3 Cycles ALU operations, and 4 Cycles Permute operations, 1 input operands 1268def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_PM_4C, P10W_DISP_ANY], 1269 (instrs 1270 VSTRIBL_rec, 1271 VSTRIBR_rec, 1272 VSTRIHL_rec, 1273 VSTRIHR_rec 1274)>; 1275 1276// 2-way crack instructions 1277// 3 Cycles ALU operations, and 3 Cycles ALU operations, 2 input operands 1278def : InstRW<[P10W_FX_3C, P10W_DISP_PAIR, P10W_FX_3C, P10FX_Read, P10FX_Read], 1279 (instrs 1280 MTCRF, MTCRF8 1281)>; 1282 1283// 6 Cycles Load operations, 1 input operands 1284def : InstRW<[P10W_LD_6C, P10W_DISP_ANY, P10LD_Read], 1285 (instrs 1286 LBZ, LBZ8, 1287 LD, LDtoc, LDtocBA, LDtocCPT, LDtocJTI, LDtocL, SPILLTOVSR_LD, 1288 LDBRX, 1289 DFLOADf32, DFLOADf64, LFD, 1290 LFDX, XFLOADf32, XFLOADf64, 1291 LFIWAX, LIWAX, 1292 LFIWZX, LIWZX, 1293 LHA, LHA8, 1294 LHAX, LHAX8, 1295 LHBRX, LHBRX8, 1296 LHZ, LHZ8, 1297 LVEBX, 1298 LVEHX, 1299 LVEWX, 1300 LVX, 1301 LVXL, 1302 LWA, LWA_32, 1303 LWAX, LWAX_32, 1304 LWBRX, LWBRX8, 1305 LWZ, LWZ8, LWZtoc, LWZtocL, 1306 LXSD, 1307 LXSDX, 1308 LXSIBZX, 1309 LXSIHZX, 1310 LXSIWAX, 1311 LXSIWZX, 1312 LXV, 1313 LXVB16X, 1314 LXVD2X, 1315 LXVDSX, 1316 LXVH8X, 1317 LXVRBX, 1318 LXVRDX, 1319 LXVRHX, 1320 LXVRWX, 1321 LXVW4X, 1322 LXVWSX, 1323 LXVX 1324)>; 1325 1326// 6 Cycles Load operations, 2 input operands 1327def : InstRW<[P10W_LD_6C, P10W_DISP_ANY, P10LD_Read, P10LD_Read], 1328 (instrs 1329 DCBT, 1330 DCBTST, 1331 ICBT, 1332 LBZX, LBZX8, LBZXTLS, LBZXTLS_, LBZXTLS_32, 1333 LDX, LDXTLS, LDXTLS_, SPILLTOVSR_LDX, 1334 LHZX, LHZX8, LHZXTLS, LHZXTLS_, LHZXTLS_32, 1335 LWZX, LWZX8, LWZXTLS, LWZXTLS_, LWZXTLS_32, 1336 LXVL, 1337 LXVLL 1338)>; 1339 1340// 2-way crack instructions 1341// 6 Cycles Load operations, and 13 Cycles Decimal Floating Point operations, 2 input operands 1342def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DF_13C, P10W_DISP_ANY], 1343 (instrs 1344 HASHCHK, HASHCHK8, 1345 HASHCHKP, HASHCHKP8 1346)>; 1347 1348// Single crack instructions 1349// 6 Cycles Load operations, 0 input operands 1350def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DISP_ANY], 1351 (instrs 1352 SLBIA 1353)>; 1354 1355// Single crack instructions 1356// 6 Cycles Load operations, 1 input operands 1357def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DISP_ANY, P10LD_Read], 1358 (instrs 1359 DARN, 1360 LBARX, LBARXL, 1361 LDARX, LDARXL, 1362 LHARX, LHARXL, 1363 LWARX, LWARXL, 1364 SLBFEE_rec, 1365 SLBIE, 1366 SLBMFEE, 1367 SLBMFEV 1368)>; 1369 1370// Single crack instructions 1371// 6 Cycles Load operations, 2 input operands 1372def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DISP_ANY, P10LD_Read, P10LD_Read], 1373 (instrs 1374 LBZCIX, 1375 LDCIX, 1376 LHZCIX, 1377 LWZCIX, 1378 MTSPR, MTSPR8, MTSR, MTUDSCR, MTVRSAVE, MTVRSAVEv 1379)>; 1380 1381// Expand instructions 1382// 6 Cycles Load operations, 6 Cycles Load operations, 6 Cycles Load operations, and 6 Cycles Load operations, 1 input operands 1383def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10LD_Read], 1384 (instrs 1385 LMW 1386)>; 1387 1388// Expand instructions 1389// 6 Cycles Load operations, 6 Cycles Load operations, 6 Cycles Load operations, and 6 Cycles Load operations, 2 input operands 1390def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10LD_Read, P10LD_Read], 1391 (instrs 1392 LSWI 1393)>; 1394 1395// 2-way crack instructions 1396// 6 Cycles Load operations, and 3 Cycles Simple Fixed-point (SFX) operations, 1 input operands 1397def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_SX_3C, P10W_DISP_ANY], 1398 (instrs 1399 LBZU, LBZU8, 1400 LBZUX, LBZUX8, 1401 LDU, 1402 LDUX, 1403 LFDU, 1404 LFDUX, 1405 LHAU, LHAU8, 1406 LHAUX, LHAUX8, 1407 LHZU, LHZU8, 1408 LHZUX, LHZUX8, 1409 LWAUX, 1410 LWZU, LWZU8, 1411 LWZUX, LWZUX8 1412)>; 1413 1414// 6 Cycles Load operations, 1 input operands 1415def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10LD_Read], 1416 (instrs 1417 PLBZ, PLBZ8, PLBZ8pc, PLBZpc, 1418 PLD, PLDpc, 1419 PLFD, PLFDpc, 1420 PLFS, PLFSpc, 1421 PLHA, PLHA8, PLHA8pc, PLHApc, 1422 PLHZ, PLHZ8, PLHZ8pc, PLHZpc, 1423 PLWA, PLWA8, PLWA8pc, PLWApc, 1424 PLWZ, PLWZ8, PLWZ8pc, PLWZpc, 1425 PLXSD, PLXSDpc, 1426 PLXSSP, PLXSSPpc, 1427 PLXV, PLXVpc, 1428 PLXVP, PLXVPpc 1429)>; 1430 1431// 2-way crack instructions 1432// 6 Cycles Load operations, and 4 Cycles ALU2 operations, 1 input operands 1433def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C], 1434 (instrs 1435 LFS, 1436 LFSX, 1437 LXSSP, 1438 LXSSPX 1439)>; 1440 1441// 4-way crack instructions 1442// 6 Cycles Load operations, 4 Cycles ALU2 operations, 3 Cycles Simple Fixed-point (SFX) operations, and 3 Cycles ALU operations, 1 input operands 1443def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C, P10W_SX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY], 1444 (instrs 1445 LFSU, 1446 LFSUX 1447)>; 1448 1449// 2-way crack instructions 1450// 6 Cycles Load operations, and 6 Cycles Load operations, 1 input operands 1451def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_LD_6C, P10W_DISP_PAIR, P10LD_Read], 1452 (instrs 1453 TLBIEL 1454)>; 1455 1456// 2-way crack instructions 1457// 6 Cycles Load operations, and 6 Cycles Load operations, 2 input operands 1458def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_LD_6C, P10W_DISP_PAIR, P10LD_Read, P10LD_Read], 1459 (instrs 1460 SLBMTE 1461)>; 1462 1463// 2-way crack instructions 1464// 6 Cycles Load operations, and 3 Cycles Simple Fixed-point (SFX) operations, 1 input operands 1465def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_SX_3C], 1466 (instrs 1467 LXVP, 1468 LXVPX 1469)>; 1470 1471// Single crack instructions 1472// 13 Cycles Unknown operations, 1 input operands 1473def : InstRW<[P10W_MFL_13C, P10W_DISP_EVEN, P10W_DISP_ANY], 1474 (instrs 1475 MFSPR, MFSPR8, MFSR, MFTB8, MFUDSCR, MFVRSAVE, MFVRSAVEv 1476)>; 1477 1478// 10 Cycles SIMD Matrix Multiply Engine operations, 0 input operands 1479def : InstRW<[P10W_MM_10C, P10W_DISP_ANY], 1480 (instrs 1481 XXSETACCZ 1482)>; 1483 1484// 10 Cycles SIMD Matrix Multiply Engine operations, 2 input operands 1485def : InstRW<[P10W_MM_10C, P10W_DISP_ANY, P10MM_Read, P10MM_Read], 1486 (instrs 1487 XVBF16GER2, 1488 XVF16GER2, 1489 XVF32GER, 1490 XVF64GER, 1491 XVI16GER2, 1492 XVI16GER2S, 1493 XVI4GER8, 1494 XVI8GER4 1495)>; 1496 1497// 10 Cycles SIMD Matrix Multiply Engine operations, 3 input operands 1498def : InstRW<[P10W_MM_10C, P10W_DISP_ANY, P10MM_Read, P10MM_Read, P10MM_Read], 1499 (instrs 1500 XVBF16GER2NN, 1501 XVBF16GER2NP, 1502 XVBF16GER2PN, 1503 XVBF16GER2PP, 1504 XVF16GER2NN, 1505 XVF16GER2NP, 1506 XVF16GER2PN, 1507 XVF16GER2PP, 1508 XVF32GERNN, 1509 XVF32GERNP, 1510 XVF32GERPN, 1511 XVF32GERPP, 1512 XVF64GERNN, 1513 XVF64GERNP, 1514 XVF64GERPN, 1515 XVF64GERPP, 1516 XVI16GER2PP, 1517 XVI16GER2SPP, 1518 XVI4GER8PP, 1519 XVI8GER4PP, 1520 XVI8GER4SPP 1521)>; 1522 1523// 10 Cycles SIMD Matrix Multiply Engine operations, 4 input operands 1524def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10MM_Read, P10MM_Read, P10MM_Read, P10MM_Read], 1525 (instrs 1526 PMXVF32GER, 1527 PMXVF64GER 1528)>; 1529 1530// 10 Cycles SIMD Matrix Multiply Engine operations, 5 input operands 1531def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10MM_Read, P10MM_Read, P10MM_Read, P10MM_Read, P10MM_Read], 1532 (instrs 1533 PMXVBF16GER2, 1534 PMXVF16GER2, 1535 PMXVF32GERNN, 1536 PMXVF32GERNP, 1537 PMXVF32GERPN, 1538 PMXVF32GERPP, 1539 PMXVF64GERNN, 1540 PMXVF64GERNP, 1541 PMXVF64GERPN, 1542 PMXVF64GERPP, 1543 PMXVI16GER2, 1544 PMXVI16GER2S, 1545 PMXVI4GER8, 1546 PMXVI8GER4 1547)>; 1548 1549// 10 Cycles SIMD Matrix Multiply Engine operations, 6 input operands 1550def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10MM_Read, P10MM_Read, P10MM_Read, P10MM_Read, P10MM_Read, P10MM_Read], 1551 (instrs 1552 PMXVBF16GER2NN, 1553 PMXVBF16GER2NP, 1554 PMXVBF16GER2PN, 1555 PMXVBF16GER2PP, 1556 PMXVF16GER2NN, 1557 PMXVF16GER2NP, 1558 PMXVF16GER2PN, 1559 PMXVF16GER2PP, 1560 PMXVI16GER2PP, 1561 PMXVI16GER2SPP, 1562 PMXVI4GER8PP, 1563 PMXVI8GER4PP, 1564 PMXVI8GER4SPP 1565)>; 1566 1567// 2-way crack instructions 1568// 10 Cycles SIMD Matrix Multiply Engine operations, and 3 Cycles ALU operations, 1 input operands 1569def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10W_FX_3C], 1570 (instrs 1571 XXMTACC 1572)>; 1573 1574// 4-way crack instructions 1575// 10 Cycles SIMD Matrix Multiply Engine operations, 3 Cycles ALU operations, 10 Cycles SIMD Matrix Multiply Engine operations, and 3 Cycles ALU operations, 1 input operands 1576def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10W_FX_3C, P10W_MM_10C, P10W_DISP_PAIR, P10W_FX_3C], 1577 (instrs 1578 XXMFACC 1579)>; 1580 1581// 5 Cycles GPR Multiply operations, 2 input operands 1582def : InstRW<[P10W_MU_5C, P10W_DISP_ANY, P10MU_Read, P10MU_Read], 1583 (instrs 1584 MULHD, 1585 MULHDU, 1586 MULHW, 1587 MULHWU, 1588 MULLD, 1589 MULLDO, 1590 MULLI, MULLI8, 1591 MULLW, 1592 MULLWO, 1593 VMULHSD, 1594 VMULHUD, 1595 VMULLD 1596)>; 1597 1598// 5 Cycles GPR Multiply operations, 3 input operands 1599def : InstRW<[P10W_MU_5C, P10W_DISP_ANY, P10MU_Read, P10MU_Read, P10MU_Read], 1600 (instrs 1601 MADDHD, 1602 MADDHDU, 1603 MADDLD, MADDLD8 1604)>; 1605 1606// 2-way crack instructions 1607// 5 Cycles GPR Multiply operations, and 3 Cycles ALU operations, 2 input operands 1608def : InstRW<[P10W_MU_5C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1609 (instrs 1610 MULHD_rec, 1611 MULHDU_rec, 1612 MULHW_rec, 1613 MULHWU_rec, 1614 MULLD_rec, 1615 MULLDO_rec, 1616 MULLW_rec, 1617 MULLWO_rec 1618)>; 1619 1620// 4 Cycles Permute operations, 0 input operands 1621def : InstRW<[P10W_PM_4C, P10W_DISP_ANY], 1622 (instrs 1623 VSPLTISW, V_SETALLONES, V_SETALLONESB, V_SETALLONESH 1624)>; 1625 1626// 4 Cycles Permute operations, 1 input operands 1627def : InstRW<[P10W_PM_4C, P10W_DISP_ANY, P10PM_Read], 1628 (instrs 1629 BRD, 1630 BRH, BRH8, 1631 BRW, BRW8, 1632 LVSL, 1633 LVSR, 1634 LXVKQ, 1635 MFVSRLD, 1636 MTVSRWS, 1637 VCLZLSBB, 1638 VCTZLSBB, 1639 VGBBD, 1640 VPRTYBQ, 1641 VSPLTISB, 1642 VSPLTISH, 1643 VSTRIBL, 1644 VSTRIBR, 1645 VSTRIHL, 1646 VSTRIHR, 1647 VUPKHPX, 1648 VUPKHSB, 1649 VUPKHSH, 1650 VUPKHSW, 1651 VUPKLPX, 1652 VUPKLSB, 1653 VUPKLSH, 1654 VUPKLSW, 1655 XVCVBF16SPN, 1656 XXBRD, 1657 XXBRH, 1658 XXBRQ, 1659 XXBRW, 1660 XXSPLTIB 1661)>; 1662 1663// 4 Cycles Permute operations, 2 input operands 1664def : InstRW<[P10W_PM_4C, P10W_DISP_ANY, P10PM_Read, P10PM_Read], 1665 (instrs 1666 BPERMD, 1667 MTVSRDD, 1668 VBPERMD, 1669 VBPERMQ, 1670 VCLRLB, 1671 VCLRRB, 1672 VEXTRACTD, 1673 VEXTRACTUB, 1674 VEXTRACTUH, 1675 VEXTRACTUW, 1676 VEXTUBLX, 1677 VEXTUBRX, 1678 VEXTUHLX, 1679 VEXTUHRX, 1680 VEXTUWLX, 1681 VEXTUWRX, 1682 VINSERTD, 1683 VINSERTW, 1684 VMRGHB, 1685 VMRGHH, 1686 VMRGHW, 1687 VMRGLB, 1688 VMRGLH, 1689 VMRGLW, 1690 VPKPX, 1691 VPKSDSS, 1692 VPKSDUS, 1693 VPKSHSS, 1694 VPKSHUS, 1695 VPKSWSS, 1696 VPKSWUS, 1697 VPKUDUM, 1698 VPKUDUS, 1699 VPKUHUM, 1700 VPKUHUS, 1701 VPKUWUM, 1702 VPKUWUS, 1703 VSL, 1704 VSLO, 1705 VSLV, 1706 VSPLTB, VSPLTBs, 1707 VSPLTH, VSPLTHs, 1708 VSPLTW, 1709 VSR, 1710 VSRO, 1711 VSRV, 1712 XXEXTRACTUW, 1713 XXGENPCVDM, 1714 XXGENPCVHM, 1715 XXGENPCVWM, 1716 XXMRGHW, 1717 XXMRGLW, 1718 XXPERMDI, XXPERMDIs, 1719 XXSLDWI, XXSLDWIs, 1720 XXSPLTW, XXSPLTWs 1721)>; 1722 1723// 4 Cycles Permute operations, 3 input operands 1724def : InstRW<[P10W_PM_4C, P10W_DISP_ANY, P10PM_Read, P10PM_Read, P10PM_Read], 1725 (instrs 1726 VEXTDDVLX, 1727 VEXTDDVRX, 1728 VEXTDUBVLX, 1729 VEXTDUBVRX, 1730 VEXTDUHVLX, 1731 VEXTDUHVRX, 1732 VEXTDUWVLX, 1733 VEXTDUWVRX, 1734 VINSBLX, 1735 VINSBRX, 1736 VINSBVLX, 1737 VINSBVRX, 1738 VINSD, 1739 VINSDLX, 1740 VINSDRX, 1741 VINSERTB, 1742 VINSERTH, 1743 VINSHLX, 1744 VINSHRX, 1745 VINSHVLX, 1746 VINSHVRX, 1747 VINSW, 1748 VINSWLX, 1749 VINSWRX, 1750 VINSWVLX, 1751 VINSWVRX, 1752 VPERM, 1753 VPERMR, 1754 VPERMXOR, 1755 VSLDBI, 1756 VSLDOI, 1757 VSRDBI, 1758 XXINSERTW, 1759 XXPERM, 1760 XXPERMR 1761)>; 1762 1763// 2-way crack instructions 1764// 4 Cycles Permute operations, and 7 Cycles VMX Multiply operations, 2 input operands 1765def : InstRW<[P10W_PM_4C, P10W_DISP_EVEN, P10W_vMU_7C, P10W_DISP_ANY], 1766 (instrs 1767 VSUMSWS 1768)>; 1769 1770// 4 Cycles Permute operations, 1 input operands 1771def : InstRW<[P10W_PM_4C, P10W_DISP_PAIR, P10PM_Read], 1772 (instrs 1773 XXSPLTIDP, 1774 XXSPLTIW 1775)>; 1776 1777// 4 Cycles Permute operations, 3 input operands 1778def : InstRW<[P10W_PM_4C, P10W_DISP_PAIR, P10PM_Read, P10PM_Read, P10PM_Read], 1779 (instrs 1780 XXBLENDVB, 1781 XXBLENDVD, 1782 XXBLENDVH, 1783 XXBLENDVW, 1784 XXSPLTI32DX 1785)>; 1786 1787// 4 Cycles Permute operations, 4 input operands 1788def : InstRW<[P10W_PM_4C, P10W_DISP_PAIR, P10PM_Read, P10PM_Read, P10PM_Read, P10PM_Read], 1789 (instrs 1790 XXEVAL, 1791 XXPERMX 1792)>; 1793 1794// 3 Cycles Store operations, 1 input operands 1795def : InstRW<[P10W_ST_3C, P10W_DISP_ANY, P10ST_Read], 1796 (instrs 1797 DCBST, 1798 DCBZ, 1799 ICBI 1800)>; 1801 1802// 3 Cycles Store operations, 2 input operands 1803def : InstRW<[P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read], 1804 (instrs 1805 DCBF, 1806 PSTXVP, PSTXVPpc, 1807 STB, STB8, 1808 STBU, STBU8, 1809 STBUX, STBUX8, 1810 SPILLTOVSR_ST, STD, 1811 STDBRX, 1812 STDU, 1813 STDUX, 1814 DFSTOREf32, DFSTOREf64, STFD, 1815 STFDU, 1816 STFDUX, 1817 STFDX, 1818 STFIWX, STIWX, 1819 STFS, 1820 STFSU, 1821 STFSUX, 1822 STFSX, 1823 STH, STH8, 1824 STHBRX, 1825 STHU, STHU8, 1826 STHUX, STHUX8, 1827 STVEBX, 1828 STVEHX, 1829 STVEWX, 1830 STVX, 1831 STVXL, 1832 STW, STW8, 1833 STWBRX, 1834 STWU, STWU8, 1835 STWUX, STWUX8, 1836 STXSD, 1837 STXSDX, 1838 STXSIBX, STXSIBXv, 1839 STXSIHX, STXSIHXv, 1840 STXSIWX, 1841 STXSSP, 1842 STXSSPX, 1843 STXV, 1844 STXVB16X, 1845 STXVD2X, 1846 STXVH8X, 1847 STXVRBX, 1848 STXVRDX, 1849 STXVRHX, 1850 STXVRWX, 1851 STXVW4X, 1852 STXVX 1853)>; 1854 1855// 3 Cycles Store operations, 3 input operands 1856def : InstRW<[P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read, P10ST_Read], 1857 (instrs 1858 CP_COPY, CP_COPY8, 1859 STBX, STBX8, STBXTLS, STBXTLS_, STBXTLS_32, 1860 SPILLTOVSR_STX, STDX, STDXTLS, STDXTLS_, 1861 STHX, STHX8, STHXTLS, STHXTLS_, STHXTLS_32, 1862 STWX, STWX8, STWXTLS, STWXTLS_, STWXTLS_32, 1863 STXVL, 1864 STXVLL 1865)>; 1866 1867// Single crack instructions 1868// 3 Cycles Store operations, 0 input operands 1869def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY], 1870 (instrs 1871 EnforceIEIO, 1872 MSGSYNC, 1873 SLBSYNC, 1874 TCHECK, 1875 TLBSYNC 1876)>; 1877 1878// Single crack instructions 1879// 3 Cycles Store operations, 1 input operands 1880def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read], 1881 (instrs 1882 TEND 1883)>; 1884 1885// Single crack instructions 1886// 3 Cycles Store operations, 2 input operands 1887def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read, P10ST_Read], 1888 (instrs 1889 SLBIEG, 1890 STBCX, 1891 STDCX, 1892 STHCX, 1893 STWCX, 1894 TLBIE 1895)>; 1896 1897// Single crack instructions 1898// 3 Cycles Store operations, 3 input operands 1899def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read, P10ST_Read, P10ST_Read], 1900 (instrs 1901 CP_PASTE8_rec, CP_PASTE_rec, 1902 STBCIX, 1903 STDCIX, 1904 STHCIX, 1905 STWCIX 1906)>; 1907 1908// 2-way crack instructions 1909// 3 Cycles Store operations, and 3 Cycles ALU operations, 0 input operands 1910def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1911 (instrs 1912 ISYNC 1913)>; 1914 1915// 2-way crack instructions 1916// 3 Cycles Store operations, and 3 Cycles ALU operations, 1 input operands 1917def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1918 (instrs 1919 SYNC 1920)>; 1921 1922// Expand instructions 1923// 3 Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, 3 Cycles ALU operations, 6 Cycles Load operations, and 3 Cycles Store operations, 2 input operands 1924def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY], 1925 (instrs 1926 LDAT, 1927 LWAT 1928)>; 1929 1930// 4-way crack instructions 1931// 3 Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, and 3 Cycles Store operations, 3 input operands 1932def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY], 1933 (instrs 1934 STDAT, 1935 STWAT 1936)>; 1937 1938// Expand instructions 1939// 3 Cycles Store operations, 3 Cycles Store operations, 3 Cycles Store operations, and 3 Cycles Store operations, 2 input operands 1940def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read], 1941 (instrs 1942 STMW 1943)>; 1944 1945// Expand instructions 1946// 3 Cycles Store operations, 3 Cycles Store operations, 3 Cycles Store operations, and 3 Cycles Store operations, 3 input operands 1947def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read, P10ST_Read], 1948 (instrs 1949 STSWI 1950)>; 1951 1952// 3 Cycles Store operations, 2 input operands 1953def : InstRW<[P10W_ST_3C, P10W_DISP_PAIR, P10ST_Read, P10ST_Read], 1954 (instrs 1955 PSTB, PSTB8, PSTB8pc, PSTBpc, 1956 PSTD, PSTDpc, 1957 PSTFD, PSTFDpc, 1958 PSTFS, PSTFSpc, 1959 PSTH, PSTH8, PSTH8pc, PSTHpc, 1960 PSTW, PSTW8, PSTW8pc, PSTWpc, 1961 PSTXSD, PSTXSDpc, 1962 PSTXSSP, PSTXSSPpc, 1963 PSTXV, PSTXVpc 1964)>; 1965 1966// 2-way crack instructions 1967// 3 Cycles Store operations, and 3 Cycles Store operations, 2 input operands 1968def : InstRW<[P10W_ST_3C, P10W_DISP_PAIR, P10W_ST_3C, P10ST_Read, P10ST_Read], 1969 (instrs 1970 STXVP, 1971 STXVPX 1972)>; 1973 1974// FIXME - Miss scheduling information from datasheet 1975// Temporary set it as 1 Cycles Simple Fixed-point (SFX) operations, 0 input operands 1976def : InstRW<[P10W_SX, P10W_DISP_ANY], 1977 (instrs 1978 ATTN, 1979 CP_ABORT, 1980 CRNOT, 1981 DCBA, 1982 DCBI, 1983 DCBZL, 1984 DCCCI, 1985 ICBLC, 1986 ICBLQ, 1987 ICBTLS, 1988 ICCCI, 1989 LA, LA8, 1990 MFDCR, 1991 MFPMR, 1992 MFSRIN, 1993 MSYNC, 1994 MTDCR, 1995 MTPMR, 1996 MTSRIN, 1997 NAP, 1998 TLBIA, 1999 TLBLD, 2000 TLBLI, 2001 TLBRE2, 2002 TLBSX2, 2003 TLBSX2D, 2004 TLBWE2 2005)>; 2006 2007// Single crack instructions 2008// 3 Cycles Simple Fixed-point (SFX) operations, 0 input operands 2009def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_DISP_ANY], 2010 (instrs 2011 CLRBHRB, 2012 MFMSR 2013)>; 2014 2015// Single crack instructions 2016// 3 Cycles Simple Fixed-point (SFX) operations, 1 input operands 2017def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10SX_Read], 2018 (instrs 2019 MFTB 2020)>; 2021 2022// Single crack instructions 2023// 3 Cycles Simple Fixed-point (SFX) operations, 2 input operands 2024def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10SX_Read, P10SX_Read], 2025 (instrs 2026 MFBHRBE, 2027 MTMSR, 2028 MTMSRD 2029)>; 2030 2031// 2-way crack instructions 2032// 3 Cycles Simple Fixed-point (SFX) operations, and 3 Cycles ALU operations, 1 input operands 2033def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 2034 (instrs 2035 ADDPCIS 2036)>; 2037 2038// 3 Cycles Simple Fixed-point (SFX) operations, 1 input operands 2039def : InstRW<[P10W_SX_3C, P10W_DISP_PAIR, P10SX_Read], 2040 (instrs 2041 PADDI, PADDI8, PADDI8pc, PADDIpc, PLI, PLI8 2042)>; 2043 2044// 7 Cycles VMX Multiply operations, 2 input operands 2045def : InstRW<[P10W_vMU_7C, P10W_DISP_ANY, P10vMU_Read, P10vMU_Read], 2046 (instrs 2047 VMULESB, 2048 VMULESD, 2049 VMULESH, 2050 VMULESW, 2051 VMULEUB, 2052 VMULEUD, 2053 VMULEUH, 2054 VMULEUW, 2055 VMULHSW, 2056 VMULHUW, 2057 VMULOSB, 2058 VMULOSD, 2059 VMULOSH, 2060 VMULOSW, 2061 VMULOUB, 2062 VMULOUD, 2063 VMULOUH, 2064 VMULOUW, 2065 VMULUWM, 2066 VSUM2SWS, 2067 VSUM4SBS, 2068 VSUM4SHS, 2069 VSUM4UBS 2070)>; 2071 2072// 7 Cycles VMX Multiply operations, 3 input operands 2073def : InstRW<[P10W_vMU_7C, P10W_DISP_ANY, P10vMU_Read, P10vMU_Read, P10vMU_Read], 2074 (instrs 2075 VMHADDSHS, 2076 VMHRADDSHS, 2077 VMLADDUHM, 2078 VMSUMCUD, 2079 VMSUMMBM, 2080 VMSUMSHM, 2081 VMSUMSHS, 2082 VMSUMUBM, 2083 VMSUMUDM, 2084 VMSUMUHM, 2085 VMSUMUHS 2086)>; 2087 2088