1//===--- P10InstrResources.td - P10 Scheduling Definitions -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// Automatically generated file, do not edit! 9// 10// This file defines the itinerary class data for the POWER10 processor. 11// 12//===----------------------------------------------------------------------===// 13// 22 Cycles Binary Floating Point operations, 2 input operands 14def : InstRW<[P10W_BF_22C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 15 (instrs 16 FDIVS, 17 XSDIVSP 18)>; 19 20// 2-way crack instructions 21// 22 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands 22def : InstRW<[P10W_BF_22C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 23 (instrs 24 FDIVS_rec 25)>; 26 27// 24 Cycles Binary Floating Point operations, 2 input operands 28def : InstRW<[P10W_BF_24C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 29 (instrs 30 XVDIVSP 31)>; 32 33// 26 Cycles Binary Floating Point operations, 1 input operands 34def : InstRW<[P10W_BF_26C, P10W_DISP_ANY, P10BF_Read], 35 (instrs 36 FSQRTS, 37 XSSQRTSP 38)>; 39 40// 2-way crack instructions 41// 26 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands 42def : InstRW<[P10W_BF_26C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 43 (instrs 44 FSQRTS_rec 45)>; 46 47// 27 Cycles Binary Floating Point operations, 1 input operands 48def : InstRW<[P10W_BF_27C, P10W_DISP_ANY, P10BF_Read], 49 (instrs 50 XVSQRTSP 51)>; 52 53// 27 Cycles Binary Floating Point operations, 2 input operands 54def : InstRW<[P10W_BF_27C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 55 (instrs 56 FDIV, 57 XSDIVDP, 58 XVDIVDP 59)>; 60 61// 2-way crack instructions 62// 27 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands 63def : InstRW<[P10W_BF_27C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 64 (instrs 65 FDIV_rec 66)>; 67 68// 36 Cycles Binary Floating Point operations, 1 input operands 69def : InstRW<[P10W_BF_36C, P10W_DISP_ANY, P10BF_Read], 70 (instrs 71 FSQRT, 72 XSSQRTDP, 73 XVSQRTDP 74)>; 75 76// 2-way crack instructions 77// 36 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands 78def : InstRW<[P10W_BF_36C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 79 (instrs 80 FSQRT_rec 81)>; 82 83// 7 Cycles Binary Floating Point operations, 1 input operands 84def : InstRW<[P10W_BF_7C, P10W_DISP_ANY, P10BF_Read], 85 (instrs 86 FCFID, 87 FCFIDS, 88 FCFIDU, 89 FCFIDUS, 90 FCTID, 91 FCTIDU, 92 FCTIDUZ, 93 FCTIDZ, 94 FCTIW, 95 FCTIWU, 96 FCTIWUZ, 97 FCTIWZ, 98 FRE, 99 FRES, 100 FRIMD, FRIMS, 101 FRIND, FRINS, 102 FRIPD, FRIPS, 103 FRIZD, FRIZS, 104 FRSP, 105 FRSQRTE, 106 FRSQRTES, 107 VCFSX, VCFSX_0, 108 VCFUX, VCFUX_0, 109 VCTSXS, VCTSXS_0, 110 VCTUXS, VCTUXS_0, 111 VLOGEFP, 112 VREFP, 113 VRFIM, 114 VRFIN, 115 VRFIP, 116 VRFIZ, 117 VRSQRTEFP, 118 XSCVDPHP, 119 XSCVDPSP, 120 XSCVDPSPN, 121 XSCVDPSXDS, XSCVDPSXDSs, 122 XSCVDPSXWS, XSCVDPSXWSs, 123 XSCVDPUXDS, XSCVDPUXDSs, 124 XSCVDPUXWS, XSCVDPUXWSs, 125 XSCVSPDP, 126 XSCVSXDDP, 127 XSCVSXDSP, 128 XSCVUXDDP, 129 XSCVUXDSP, 130 XSRDPI, 131 XSRDPIC, 132 XSRDPIM, 133 XSRDPIP, 134 XSRDPIZ, 135 XSREDP, 136 XSRESP, 137 XSRSP, 138 XSRSQRTEDP, 139 XSRSQRTESP, 140 XVCVDPSP, 141 XVCVDPSXDS, 142 XVCVDPSXWS, 143 XVCVDPUXDS, 144 XVCVDPUXWS, 145 XVCVSPBF16, 146 XVCVSPDP, 147 XVCVSPHP, 148 XVCVSPSXDS, 149 XVCVSPSXWS, 150 XVCVSPUXDS, 151 XVCVSPUXWS, 152 XVCVSXDDP, 153 XVCVSXDSP, 154 XVCVSXWDP, 155 XVCVSXWSP, 156 XVCVUXDDP, 157 XVCVUXDSP, 158 XVCVUXWDP, 159 XVCVUXWSP, 160 XVRDPI, 161 XVRDPIC, 162 XVRDPIM, 163 XVRDPIP, 164 XVRDPIZ, 165 XVREDP, 166 XVRESP, 167 XVRSPI, 168 XVRSPIC, 169 XVRSPIM, 170 XVRSPIP, 171 XVRSPIZ, 172 XVRSQRTEDP, 173 XVRSQRTESP 174)>; 175 176// 7 Cycles Binary Floating Point operations, 2 input operands 177def : InstRW<[P10W_BF_7C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 178 (instrs 179 FADD, 180 FADDS, 181 FMUL, 182 FMULS, 183 FSUB, 184 FSUBS, 185 VADDFP, 186 VSUBFP, 187 XSADDDP, 188 XSADDSP, 189 XSMULDP, 190 XSMULSP, 191 XSSUBDP, 192 XSSUBSP, 193 XVADDDP, 194 XVADDSP, 195 XVMULDP, 196 XVMULSP, 197 XVSUBDP, 198 XVSUBSP 199)>; 200 201// 7 Cycles Binary Floating Point operations, 3 input operands 202def : InstRW<[P10W_BF_7C, P10W_DISP_ANY, P10BF_Read, P10BF_Read, P10BF_Read], 203 (instrs 204 FMADD, 205 FMADDS, 206 FMSUB, 207 FMSUBS, 208 FNMADD, 209 FNMADDS, 210 FNMSUB, 211 FNMSUBS, 212 FSELD, FSELS, 213 VMADDFP, 214 VNMSUBFP, 215 XSMADDADP, 216 XSMADDASP, 217 XSMADDMDP, 218 XSMADDMSP, 219 XSMSUBADP, 220 XSMSUBASP, 221 XSMSUBMDP, 222 XSMSUBMSP, 223 XSNMADDADP, 224 XSNMADDASP, 225 XSNMADDMDP, 226 XSNMADDMSP, 227 XSNMSUBADP, 228 XSNMSUBASP, 229 XSNMSUBMDP, 230 XSNMSUBMSP, 231 XVMADDADP, 232 XVMADDASP, 233 XVMADDMDP, 234 XVMADDMSP, 235 XVMSUBADP, 236 XVMSUBASP, 237 XVMSUBMDP, 238 XVMSUBMSP, 239 XVNMADDADP, 240 XVNMADDASP, 241 XVNMADDMDP, 242 XVNMADDMSP, 243 XVNMSUBADP, 244 XVNMSUBASP, 245 XVNMSUBMDP, 246 XVNMSUBMSP 247)>; 248 249// 2-way crack instructions 250// 7 Cycles Binary Floating Point operations, and 7 Cycles Binary Floating Point operations, 1 input operands 251def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_BF_7C, P10W_DISP_ANY, P10BF_Read], 252 (instrs 253 VEXPTEFP 254)>; 255 256// 2-way crack instructions 257// 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands 258def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 259 (instrs 260 FADD_rec, 261 FADDS_rec, 262 FMUL_rec, 263 FMULS_rec, 264 FSUB_rec, 265 FSUBS_rec 266)>; 267 268// 2-way crack instructions 269// 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands 270def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 271 (instrs 272 FCFID_rec, 273 FCFIDS_rec, 274 FCFIDU_rec, 275 FCFIDUS_rec, 276 FCTID_rec, 277 FCTIDU_rec, 278 FCTIDUZ_rec, 279 FCTIDZ_rec, 280 FCTIW_rec, 281 FCTIWU_rec, 282 FCTIWUZ_rec, 283 FCTIWZ_rec, 284 FRE_rec, 285 FRES_rec, 286 FRIMD_rec, FRIMS_rec, 287 FRIND_rec, FRINS_rec, 288 FRIPD_rec, FRIPS_rec, 289 FRIZD_rec, FRIZS_rec, 290 FRSP_rec, 291 FRSQRTE_rec, 292 FRSQRTES_rec 293)>; 294 295// 2-way crack instructions 296// 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 3 input operands 297def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 298 (instrs 299 FMADD_rec, 300 FMADDS_rec, 301 FMSUB_rec, 302 FMSUBS_rec, 303 FNMADD_rec, 304 FNMADDS_rec, 305 FNMSUB_rec, 306 FNMSUBS_rec, 307 FSELD_rec, FSELS_rec 308)>; 309 310// 2 Cycles Branch operations, 0 input operands 311def : InstRW<[P10W_BR_2C, P10W_DISP_ANY], 312 (instrs 313 BCLR, BCLRn, BDNZLR, BDNZLR8, BDNZLRm, BDNZLRp, BDZLR, BDZLR8, BDZLRm, BDZLRp, gBCLR, 314 BCLRL, BCLRLn, BDNZLRL, BDNZLRLm, BDNZLRLp, BDZLRL, BDZLRLm, BDZLRLp, gBCLRL, 315 BL, BL8, BL8_NOP, BL8_NOP_RM, BL8_NOP_TLS, BL8_NOTOC, BL8_NOTOC_RM, BL8_NOTOC_TLS, BL8_RM, BL8_TLS, BL8_TLS_, BLR, BLR8, BLRL, BL_NOP, BL_NOP_RM, BL_RM, BL_TLS 316)>; 317 318// 2 Cycles Branch operations, 1 input operands 319def : InstRW<[P10W_BR_2C, P10W_DISP_ANY, P10BR_Read], 320 (instrs 321 B, BCC, BCCA, BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL, BCCLA, BCCLR, BCCLRL, CTRL_DEP, TAILB, TAILB8, 322 BA, TAILBA, TAILBA8, 323 BC, BCTR, BCTR8, BCTRL, BCTRL8, BCTRL8_LDinto_toc, BCTRL8_LDinto_toc_RM, BCTRL8_RM, BCTRL_LWZinto_toc, BCTRL_LWZinto_toc_RM, BCTRL_RM, BCn, BDNZ, BDNZ8, BDNZm, BDNZp, BDZ, BDZ8, BDZm, BDZp, TAILBCTR, TAILBCTR8, gBC, gBCat, 324 BCL, BCLalways, BCLn, BDNZL, BDNZLm, BDNZLp, BDZL, BDZLm, BDZLp, gBCL, gBCLat, 325 BLA, BLA8, BLA8_NOP, BLA8_NOP_RM, BLA8_RM, BLA_RM 326)>; 327 328// 2 Cycles Branch operations, 3 input operands 329def : InstRW<[P10W_BR_2C, P10W_DISP_ANY, P10BR_Read, P10BR_Read, P10BR_Read], 330 (instrs 331 BCCTR, BCCTR8, BCCTR8n, BCCTRn, gBCCTR, 332 BCCTRL, BCCTRL8, BCCTRL8n, BCCTRLn, gBCCTRL 333)>; 334 335// 2 Cycles Branch operations, 4 input operands 336def : InstRW<[P10W_BR_2C, P10W_DISP_ANY, P10BR_Read, P10BR_Read, P10BR_Read, P10BR_Read], 337 (instrs 338 BDNZA, BDNZAm, BDNZAp, BDZA, BDZAm, BDZAp, gBCA, gBCAat, 339 BDNZLA, BDNZLAm, BDNZLAp, BDZLA, BDZLAm, BDZLAp, gBCLA, gBCLAat 340)>; 341 342// 7 Cycles Crypto operations, 1 input operands 343def : InstRW<[P10W_CY_7C, P10W_DISP_ANY, P10CY_Read], 344 (instrs 345 VSBOX 346)>; 347 348// 7 Cycles Crypto operations, 2 input operands 349def : InstRW<[P10W_CY_7C, P10W_DISP_ANY, P10CY_Read, P10CY_Read], 350 (instrs 351 CFUGED, 352 CNTLZDM, 353 CNTTZDM, 354 PDEPD, 355 PEXTD, 356 VCFUGED, 357 VCIPHER, 358 VCIPHERLAST, 359 VCLZDM, 360 VCTZDM, 361 VGNB, 362 VNCIPHER, 363 VNCIPHERLAST, 364 VPDEPD, 365 VPEXTD, 366 VPMSUMB, 367 VPMSUMD, 368 VPMSUMH, 369 VPMSUMW 370)>; 371 372// 13 Cycles Decimal Floating Point operations, 1 input operands 373def : InstRW<[P10W_DF_13C, P10W_DISP_ANY, P10DF_Read], 374 (instrs 375 XSCVDPQP, 376 XSCVQPDP, 377 XSCVQPDPO, 378 XSCVQPSDZ, 379 XSCVQPSQZ, 380 XSCVQPSWZ, 381 XSCVQPUDZ, 382 XSCVQPUQZ, 383 XSCVQPUWZ, 384 XSCVSDQP, 385 XSCVSQQP, 386 XSCVUDQP, 387 XSCVUQQP 388)>; 389 390// 13 Cycles Decimal Floating Point operations, 2 input operands 391def : InstRW<[P10W_DF_13C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 392 (instrs 393 XSADDQP, 394 XSADDQPO, 395 XSSUBQP, 396 XSSUBQPO 397)>; 398 399// 13 Cycles Decimal Floating Point operations, 3 input operands 400def : InstRW<[P10W_DF_13C, P10W_DISP_ANY, P10DF_Read, P10DF_Read, P10DF_Read], 401 (instrs 402 BCDSR_rec, 403 XSRQPI, 404 XSRQPIX, 405 XSRQPXP 406)>; 407 408// 2-way crack instructions 409// 13 Cycles Decimal Floating Point operations, and 3 Cycles Store operations, 2 input operands 410def : InstRW<[P10W_DF_13C, P10W_DISP_EVEN, P10W_ST_3C, P10W_DISP_ANY], 411 (instrs 412 HASHST, 413 HASHSTP 414)>; 415 416// 24 Cycles Decimal Floating Point operations, 1 input operands 417def : InstRW<[P10W_DF_24C, P10W_DISP_ANY, P10DF_Read], 418 (instrs 419 BCDCTSQ_rec 420)>; 421 422// 25 Cycles Decimal Floating Point operations, 2 input operands 423def : InstRW<[P10W_DF_25C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 424 (instrs 425 XSMULQP, 426 XSMULQPO 427)>; 428 429// 25 Cycles Decimal Floating Point operations, 3 input operands 430def : InstRW<[P10W_DF_25C, P10W_DISP_ANY, P10DF_Read, P10DF_Read, P10DF_Read], 431 (instrs 432 XSMADDQP, 433 XSMADDQPO, 434 XSMSUBQP, 435 XSMSUBQPO, 436 XSNMADDQP, 437 XSNMADDQPO, 438 XSNMSUBQP, 439 XSNMSUBQPO 440)>; 441 442// 38 Cycles Decimal Floating Point operations, 2 input operands 443def : InstRW<[P10W_DF_38C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 444 (instrs 445 BCDCFSQ_rec 446)>; 447 448// 59 Cycles Decimal Floating Point operations, 2 input operands 449def : InstRW<[P10W_DF_59C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 450 (instrs 451 XSDIVQP, 452 XSDIVQPO 453)>; 454 455// 61 Cycles Decimal Floating Point operations, 2 input operands 456def : InstRW<[P10W_DF_61C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 457 (instrs 458 VDIVESQ, 459 VDIVEUQ, 460 VDIVSQ, 461 VDIVUQ 462)>; 463 464// 68 Cycles Decimal Floating Point operations, 2 input operands 465def : InstRW<[P10W_DF_68C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 466 (instrs 467 VMODSQ, 468 VMODUQ 469)>; 470 471// 77 Cycles Decimal Floating Point operations, 1 input operands 472def : InstRW<[P10W_DF_77C, P10W_DISP_ANY, P10DF_Read], 473 (instrs 474 XSSQRTQP, 475 XSSQRTQPO 476)>; 477 478// 20 Cycles Scalar Fixed-Point Divide operations, 2 input operands 479def : InstRW<[P10W_DV_20C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 480 (instrs 481 DIVW, 482 DIVWO, 483 DIVWU, 484 DIVWUO, 485 MODSW 486)>; 487 488// 2-way crack instructions 489// 20 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands 490def : InstRW<[P10W_DV_20C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 491 (instrs 492 DIVW_rec, 493 DIVWO_rec, 494 DIVWU_rec, 495 DIVWUO_rec 496)>; 497 498// 25 Cycles Scalar Fixed-Point Divide operations, 2 input operands 499def : InstRW<[P10W_DV_25C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 500 (instrs 501 DIVD, 502 DIVDO, 503 DIVDU, 504 DIVDUO, 505 DIVWE, 506 DIVWEO, 507 DIVWEU, 508 DIVWEUO 509)>; 510 511// 2-way crack instructions 512// 25 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands 513def : InstRW<[P10W_DV_25C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 514 (instrs 515 DIVD_rec, 516 DIVDO_rec, 517 DIVDU_rec, 518 DIVDUO_rec, 519 DIVWE_rec, 520 DIVWEO_rec, 521 DIVWEU_rec, 522 DIVWEUO_rec 523)>; 524 525// 27 Cycles Scalar Fixed-Point Divide operations, 2 input operands 526def : InstRW<[P10W_DV_27C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 527 (instrs 528 MODSD, 529 MODUD, 530 MODUW 531)>; 532 533// 41 Cycles Scalar Fixed-Point Divide operations, 2 input operands 534def : InstRW<[P10W_DV_41C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 535 (instrs 536 DIVDE, 537 DIVDEO, 538 DIVDEU, 539 DIVDEUO 540)>; 541 542// 2-way crack instructions 543// 41 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands 544def : InstRW<[P10W_DV_41C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 545 (instrs 546 DIVDE_rec, 547 DIVDEO_rec, 548 DIVDEU_rec, 549 DIVDEUO_rec 550)>; 551 552// 43 Cycles Scalar Fixed-Point Divide operations, 2 input operands 553def : InstRW<[P10W_DV_43C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 554 (instrs 555 VDIVSD, 556 VDIVUD 557)>; 558 559// 47 Cycles Scalar Fixed-Point Divide operations, 2 input operands 560def : InstRW<[P10W_DV_47C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 561 (instrs 562 VMODSD, 563 VMODUD 564)>; 565 566// 54 Cycles Scalar Fixed-Point Divide operations, 2 input operands 567def : InstRW<[P10W_DV_54C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 568 (instrs 569 VDIVSW, 570 VDIVUW 571)>; 572 573// 60 Cycles Scalar Fixed-Point Divide operations, 2 input operands 574def : InstRW<[P10W_DV_60C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 575 (instrs 576 VMODSW, 577 VMODUW 578)>; 579 580// 75 Cycles Scalar Fixed-Point Divide operations, 2 input operands 581def : InstRW<[P10W_DV_75C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 582 (instrs 583 VDIVESD, 584 VDIVEUD 585)>; 586 587// 83 Cycles Scalar Fixed-Point Divide operations, 2 input operands 588def : InstRW<[P10W_DV_83C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 589 (instrs 590 VDIVESW, 591 VDIVEUW 592)>; 593 594// 5 Cycles Fixed-Point and BCD operations, 1 input operands 595def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read], 596 (instrs 597 BCDCTN_rec, 598 VMUL10CUQ, 599 VMUL10UQ, 600 XSXSIGQP 601)>; 602 603// 5 Cycles Fixed-Point and BCD operations, 2 input operands 604def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read, P10DX_Read], 605 (instrs 606 BCDCFN_rec, 607 BCDCFZ_rec, 608 BCDCPSGN_rec, 609 BCDCTZ_rec, 610 BCDSETSGN_rec, 611 BCDUS_rec, 612 BCDUTRUNC_rec, 613 VADDCUQ, 614 VADDUQM, 615 VMUL10ECUQ, 616 VMUL10EUQ, 617 VSUBCUQ, 618 VSUBUQM, 619 XSCMPEXPQP, 620 XSCMPOQP, 621 XSCMPUQP, 622 XSTSTDCQP, 623 XXGENPCVBM 624)>; 625 626// 5 Cycles Fixed-Point and BCD operations, 3 input operands 627def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read, P10DX_Read, P10DX_Read], 628 (instrs 629 BCDS_rec, 630 BCDTRUNC_rec, 631 VADDECUQ, 632 VADDEUQM, 633 VSUBECUQ, 634 VSUBEUQM 635)>; 636 637// 4 Cycles ALU2 operations, 0 input operands 638def : InstRW<[P10W_F2_4C, P10W_DISP_ANY], 639 (instrs 640 TRAP, TW 641)>; 642 643// 4 Cycles ALU2 operations, 1 input operands 644def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read], 645 (instrs 646 CNTLZD, 647 CNTLZD_rec, 648 CNTLZW, CNTLZW8, 649 CNTLZW8_rec, CNTLZW_rec, 650 CNTTZD, 651 CNTTZD_rec, 652 CNTTZW, CNTTZW8, 653 CNTTZW8_rec, CNTTZW_rec, 654 FTSQRT, 655 MTVSRBM, 656 MTVSRBMI, 657 MTVSRDM, 658 MTVSRHM, 659 MTVSRQM, 660 MTVSRWM, 661 POPCNTB, POPCNTB8, 662 POPCNTD, 663 POPCNTW, 664 VCLZB, 665 VCLZD, 666 VCLZH, 667 VCLZW, 668 VCTZB, 669 VCTZD, 670 VCTZH, 671 VCTZW, 672 VEXPANDBM, 673 VEXPANDDM, 674 VEXPANDHM, 675 VEXPANDQM, 676 VEXPANDWM, 677 VEXTRACTBM, 678 VEXTRACTDM, 679 VEXTRACTHM, 680 VEXTRACTQM, 681 VEXTRACTWM, 682 VPOPCNTB, 683 VPOPCNTD, 684 VPOPCNTH, 685 VPOPCNTW, 686 VPRTYBD, 687 VPRTYBW, 688 XSCVHPDP, 689 XSCVSPDPN, 690 XSTSQRTDP, 691 XVCVHPSP, 692 XVTLSBB, 693 XVTSQRTDP, 694 XVTSQRTSP 695)>; 696 697// 4 Cycles ALU2 operations, 2 input operands 698def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read], 699 (instrs 700 CMPEQB, 701 EXTSWSLI_32_64_rec, EXTSWSLI_rec, 702 FCMPOD, FCMPOS, 703 FCMPUD, FCMPUS, 704 FTDIV, 705 SLD_rec, 706 SLW8_rec, SLW_rec, 707 SRD_rec, 708 SRW8_rec, SRW_rec, 709 VABSDUB, 710 VABSDUH, 711 VABSDUW, 712 VADDCUW, 713 VADDSBS, 714 VADDSHS, 715 VADDSWS, 716 VADDUBS, 717 VADDUHS, 718 VADDUWS, 719 VAVGSB, 720 VAVGSH, 721 VAVGSW, 722 VAVGUB, 723 VAVGUH, 724 VAVGUW, 725 VCMPBFP, 726 VCMPBFP_rec, 727 VCMPEQFP, 728 VCMPEQFP_rec, 729 VCMPEQUB_rec, 730 VCMPEQUD_rec, 731 VCMPEQUH_rec, 732 VCMPEQUQ, 733 VCMPEQUQ_rec, 734 VCMPEQUW_rec, 735 VCMPGEFP, 736 VCMPGEFP_rec, 737 VCMPGTFP, 738 VCMPGTFP_rec, 739 VCMPGTSB_rec, 740 VCMPGTSD_rec, 741 VCMPGTSH_rec, 742 VCMPGTSQ, 743 VCMPGTSQ_rec, 744 VCMPGTSW_rec, 745 VCMPGTUB_rec, 746 VCMPGTUD_rec, 747 VCMPGTUH_rec, 748 VCMPGTUQ, 749 VCMPGTUQ_rec, 750 VCMPGTUW_rec, 751 VCMPNEB_rec, 752 VCMPNEH_rec, 753 VCMPNEW_rec, 754 VCMPNEZB_rec, 755 VCMPNEZH_rec, 756 VCMPNEZW_rec, 757 VCMPSQ, 758 VCMPUQ, 759 VCNTMBB, 760 VCNTMBD, 761 VCNTMBH, 762 VCNTMBW, 763 VMAXFP, 764 VMINFP, 765 VSUBCUW, 766 VSUBSBS, 767 VSUBSHS, 768 VSUBSWS, 769 VSUBUBS, 770 VSUBUHS, 771 VSUBUWS, 772 XSCMPEQDP, 773 XSCMPEXPDP, 774 XSCMPGEDP, 775 XSCMPGTDP, 776 XSCMPODP, 777 XSCMPUDP, 778 XSMAXCDP, 779 XSMAXDP, 780 XSMAXJDP, 781 XSMINCDP, 782 XSMINDP, 783 XSMINJDP, 784 XSTDIVDP, 785 XSTSTDCDP, 786 XSTSTDCSP, 787 XVCMPEQDP, 788 XVCMPEQDP_rec, 789 XVCMPEQSP, 790 XVCMPEQSP_rec, 791 XVCMPGEDP, 792 XVCMPGEDP_rec, 793 XVCMPGESP, 794 XVCMPGESP_rec, 795 XVCMPGTDP, 796 XVCMPGTDP_rec, 797 XVCMPGTSP, 798 XVCMPGTSP_rec, 799 XVMAXDP, 800 XVMAXSP, 801 XVMINDP, 802 XVMINSP, 803 XVTDIVDP, 804 XVTDIVSP, 805 XVTSTDCDP, 806 XVTSTDCSP 807)>; 808 809// 4 Cycles ALU2 operations, 3 input operands 810def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read, P10F2_Read], 811 (instrs 812 CMPRB, CMPRB8, 813 RLDCL_rec, 814 RLDCR_rec, 815 RLDIC_rec, 816 RLDICL_32_rec, RLDICL_rec, 817 RLDICR_rec, 818 TD, 819 TDI, 820 TWI, 821 VSHASIGMAD, 822 VSHASIGMAW 823)>; 824 825// 4 Cycles ALU2 operations, 4 input operands 826def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read, P10F2_Read, P10F2_Read], 827 (instrs 828 RLDIMI_rec, 829 RLWINM8_rec, RLWINM_rec, 830 RLWNM8_rec, RLWNM_rec 831)>; 832 833// 4 Cycles ALU2 operations, 5 input operands 834def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read, P10F2_Read, P10F2_Read, P10F2_Read], 835 (instrs 836 RLWIMI8_rec, RLWIMI_rec 837)>; 838 839// Single crack instructions 840// 4 Cycles ALU2 operations, 2 input operands 841def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_DISP_ANY, P10F2_Read, P10F2_Read], 842 (instrs 843 SRAD_rec, 844 SRADI_rec, 845 SRAW_rec, 846 SRAWI_rec 847)>; 848 849// Single crack instructions 850// 4 Cycles ALU2 operations, 3 input operands 851def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_DISP_ANY, P10F2_Read, P10F2_Read, P10F2_Read], 852 (instrs 853 TABORTDC, 854 TABORTDCI, 855 TABORTWC, 856 TABORTWCI 857)>; 858 859// 2-way crack instructions 860// 4 Cycles ALU2 operations, and 4 Cycles Permute operations, 2 input operands 861def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_PM_4C, P10W_DISP_ANY], 862 (instrs 863 VRLQ, 864 VRLQNM, 865 VSLQ, 866 VSRAQ, 867 VSRQ 868)>; 869 870// 2-way crack instructions 871// 4 Cycles ALU2 operations, and 4 Cycles Permute operations, 3 input operands 872def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_PM_4C, P10W_DISP_ANY], 873 (instrs 874 VRLQMI 875)>; 876 877// 2-way crack instructions 878// 4 Cycles ALU2 operations, and 4 Cycles ALU2 operations, 0 input operands 879def : InstRW<[P10W_F2_4C, P10W_DISP_PAIR, P10W_F2_4C], 880 (instrs 881 MFCR, MFCR8 882)>; 883 884// 2 Cycles ALU operations, 1 input operands 885def : InstRW<[P10W_FX_2C, P10W_DISP_ANY, P10FX_Read], 886 (instrs 887 MTCTR, MTCTR8, MTCTR8loop, MTCTRloop, 888 MTLR, MTLR8 889)>; 890 891// 3 Cycles ALU operations, 0 input operands 892def : InstRW<[P10W_FX_3C, P10W_DISP_ANY], 893 (instrs 894 CR6SET, CREQV, CRSET, 895 DSS, DSSALL, 896 MCRXRX, 897 MFCTR, MFCTR8, 898 MFLR, MFLR8, 899 NOP, NOP_GT_PWR6, NOP_GT_PWR7, ORI, ORI8, 900 VXOR, V_SET0, V_SET0B, V_SET0H, 901 XXLEQV, XXLEQVOnes, 902 XXLXOR, XXLXORdpz, XXLXORspz, XXLXORz 903)>; 904 905// 3 Cycles ALU operations, 1 input operands 906def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read], 907 (instrs 908 ADDI, ADDI8, ADDIdtprelL32, ADDItlsldLADDR32, ADDItocL, LI, LI8, 909 ADDIS, ADDIS8, ADDISdtprelHA32, ADDIStocHA, ADDIStocHA8, LIS, LIS8, 910 ADDME, ADDME8, 911 ADDME8O, ADDMEO, 912 ADDZE, ADDZE8, 913 ADDZE8O, ADDZEO, 914 EXTSB, EXTSB8, EXTSB8_32_64, 915 EXTSB8_rec, EXTSB_rec, 916 EXTSH, EXTSH8, EXTSH8_32_64, 917 EXTSH8_rec, EXTSH_rec, 918 EXTSW, EXTSW_32, EXTSW_32_64, 919 EXTSW_32_64_rec, EXTSW_rec, 920 FABSD, FABSS, 921 FMR, 922 FNABSD, FNABSS, 923 FNEGD, FNEGS, 924 MCRF, 925 MFOCRF, MFOCRF8, 926 MFVRD, MFVSRD, 927 MFVRWZ, MFVSRWZ, 928 MTOCRF, MTOCRF8, 929 MTVRD, MTVSRD, 930 MTVRWA, MTVSRWA, 931 MTVRWZ, MTVSRWZ, 932 NEG, NEG8, 933 NEG8_rec, NEG_rec, 934 NEG8O, NEGO, 935 SETB, SETB8, 936 SETBC, SETBC8, 937 SETBCR, SETBCR8, 938 SETNBC, SETNBC8, 939 SETNBCR, SETNBCR8, 940 SUBFME, SUBFME8, 941 SUBFME8O, SUBFMEO, 942 SUBFZE, SUBFZE8, 943 SUBFZE8O, SUBFZEO, 944 VEXTSB2D, VEXTSB2Ds, 945 VEXTSB2W, VEXTSB2Ws, 946 VEXTSD2Q, 947 VEXTSH2D, VEXTSH2Ds, 948 VEXTSH2W, VEXTSH2Ws, 949 VEXTSW2D, VEXTSW2Ds, 950 VNEGD, 951 VNEGW, 952 WAIT, 953 XSABSDP, 954 XSABSQP, 955 XSNABSDP, 956 XSNABSQP, 957 XSNEGDP, 958 XSNEGQP, 959 XSXEXPDP, 960 XSXEXPQP, 961 XSXSIGDP, 962 XVABSDP, 963 XVABSSP, 964 XVNABSDP, 965 XVNABSSP, 966 XVNEGDP, 967 XVNEGSP, 968 XVXEXPDP, 969 XVXEXPSP, 970 XVXSIGDP, 971 XVXSIGSP 972)>; 973 974// 3 Cycles ALU operations, 2 input operands 975def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 976 (instrs 977 ADD4, ADD4TLS, ADD8, ADD8TLS, ADD8TLS_, 978 ADD4_rec, ADD8_rec, 979 ADDE, ADDE8, 980 ADDE8O, ADDEO, 981 ADDIC, ADDIC8, 982 ADD4O, ADD8O, 983 AND, AND8, 984 AND8_rec, AND_rec, 985 ANDC, ANDC8, 986 ANDC8_rec, ANDC_rec, 987 ANDI8_rec, ANDI_rec, 988 ANDIS8_rec, ANDIS_rec, 989 CMPD, CMPW, 990 CMPB, CMPB8, 991 CMPDI, CMPWI, 992 CMPLD, CMPLW, 993 CMPLDI, CMPLWI, 994 CRAND, 995 CRANDC, 996 CRNAND, 997 CRNOR, 998 CROR, 999 CRORC, 1000 CR6UNSET, CRUNSET, CRXOR, 1001 EQV, EQV8, 1002 EQV8_rec, EQV_rec, 1003 EXTSWSLI, EXTSWSLI_32_64, 1004 FCPSGND, FCPSGNS, 1005 NAND, NAND8, 1006 NAND8_rec, NAND_rec, 1007 NOR, NOR8, 1008 NOR8_rec, NOR_rec, 1009 COPY, OR, OR8, 1010 OR8_rec, OR_rec, 1011 ORC, ORC8, 1012 ORC8_rec, ORC_rec, 1013 ORIS, ORIS8, 1014 SLD, 1015 SLW, SLW8, 1016 SRAD, 1017 SRADI, SRADI_32, 1018 SRAW, 1019 SRAWI, 1020 SRD, 1021 SRW, SRW8, 1022 SUBF, SUBF8, 1023 SUBF8_rec, SUBF_rec, 1024 SUBFE, SUBFE8, 1025 SUBFE8O, SUBFEO, 1026 SUBFIC, SUBFIC8, 1027 SUBF8O, SUBFO, 1028 VADDUBM, 1029 VADDUDM, 1030 VADDUHM, 1031 VADDUWM, 1032 VAND, 1033 VANDC, 1034 VCMPEQUB, 1035 VCMPEQUD, 1036 VCMPEQUH, 1037 VCMPEQUW, 1038 VCMPGTSB, 1039 VCMPGTSD, 1040 VCMPGTSH, 1041 VCMPGTSW, 1042 VCMPGTUB, 1043 VCMPGTUD, 1044 VCMPGTUH, 1045 VCMPGTUW, 1046 VCMPNEB, 1047 VCMPNEH, 1048 VCMPNEW, 1049 VCMPNEZB, 1050 VCMPNEZH, 1051 VCMPNEZW, 1052 VEQV, 1053 VMAXSB, 1054 VMAXSD, 1055 VMAXSH, 1056 VMAXSW, 1057 VMAXUB, 1058 VMAXUD, 1059 VMAXUH, 1060 VMAXUW, 1061 VMINSB, 1062 VMINSD, 1063 VMINSH, 1064 VMINSW, 1065 VMINUB, 1066 VMINUD, 1067 VMINUH, 1068 VMINUW, 1069 VMRGEW, 1070 VMRGOW, 1071 VNAND, 1072 VNOR, 1073 VOR, 1074 VORC, 1075 VRLB, 1076 VRLD, 1077 VRLDNM, 1078 VRLH, 1079 VRLW, 1080 VRLWNM, 1081 VSLB, 1082 VSLD, 1083 VSLH, 1084 VSLW, 1085 VSRAB, 1086 VSRAD, 1087 VSRAH, 1088 VSRAW, 1089 VSRB, 1090 VSRD, 1091 VSRH, 1092 VSRW, 1093 VSUBUBM, 1094 VSUBUDM, 1095 VSUBUHM, 1096 VSUBUWM, 1097 XOR, XOR8, 1098 XOR8_rec, XOR_rec, 1099 XORI, XORI8, 1100 XORIS, XORIS8, 1101 XSCPSGNDP, 1102 XSCPSGNQP, 1103 XSIEXPDP, 1104 XSIEXPQP, 1105 XVCPSGNDP, 1106 XVCPSGNSP, 1107 XVIEXPDP, 1108 XVIEXPSP, 1109 XXLAND, 1110 XXLANDC, 1111 XXLNAND, 1112 XXLNOR, 1113 XXLOR, XXLORf, 1114 XXLORC 1115)>; 1116 1117// 3 Cycles ALU operations, 3 input operands 1118def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read, P10FX_Read], 1119 (instrs 1120 ADDEX, ADDEX8, 1121 DST, DST64, DSTT, DSTT64, 1122 DSTST, DSTST64, DSTSTT, DSTSTT64, 1123 ISEL, ISEL8, 1124 RLDCL, 1125 RLDCR, 1126 RLDIC, 1127 RLDICL, RLDICL_32, RLDICL_32_64, 1128 RLDICR, RLDICR_32, 1129 VRLDMI, 1130 VRLWMI, 1131 VSEL, 1132 XXSEL 1133)>; 1134 1135// 3 Cycles ALU operations, 4 input operands 1136def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read, P10FX_Read, P10FX_Read], 1137 (instrs 1138 RLDIMI, 1139 RLWINM, RLWINM8, 1140 RLWNM, RLWNM8 1141)>; 1142 1143// 3 Cycles ALU operations, 5 input operands 1144def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read, P10FX_Read, P10FX_Read, P10FX_Read], 1145 (instrs 1146 RLWIMI, RLWIMI8 1147)>; 1148 1149// Single crack instructions 1150// 3 Cycles ALU operations, 0 input operands 1151def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_DISP_ANY], 1152 (instrs 1153 MFFS, 1154 MFFS_rec, 1155 MFFSL, 1156 MFVSCR, 1157 TRECHKPT 1158)>; 1159 1160// Single crack instructions 1161// 3 Cycles ALU operations, 1 input operands 1162def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10FX_Read], 1163 (instrs 1164 ADDME8_rec, ADDME_rec, 1165 ADDME8O_rec, ADDMEO_rec, 1166 ADDZE8_rec, ADDZE_rec, 1167 ADDZE8O_rec, ADDZEO_rec, 1168 MCRFS, 1169 MFFSCDRN, 1170 MFFSCDRNI, 1171 MFFSCRN, 1172 MFFSCRNI, 1173 MTFSB0, 1174 MTVSCR, 1175 NEG8O_rec, NEGO_rec, 1176 SUBFME8_rec, SUBFME_rec, 1177 SUBFME8O_rec, SUBFMEO_rec, 1178 SUBFZE8_rec, SUBFZE_rec, 1179 SUBFZE8O_rec, SUBFZEO_rec, 1180 TABORT, 1181 TBEGIN, 1182 TRECLAIM, 1183 TSR 1184)>; 1185 1186// Single crack instructions 1187// 3 Cycles ALU operations, 2 input operands 1188def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 1189 (instrs 1190 ADDE8_rec, ADDE_rec, 1191 ADDE8O_rec, ADDEO_rec, 1192 ADDIC_rec, 1193 ADD4O_rec, ADD8O_rec, 1194 SUBFE8_rec, SUBFE_rec, 1195 SUBFE8O_rec, SUBFEO_rec, 1196 SUBF8O_rec, SUBFO_rec 1197)>; 1198 1199// 2-way crack instructions 1200// 3 Cycles ALU operations, and 3 Cycles ALU operations, 0 input operands 1201def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1202 (instrs 1203 HRFID, 1204 MFFSCE, 1205 RFID, 1206 STOP 1207)>; 1208 1209// 2-way crack instructions 1210// 3 Cycles ALU operations, and 3 Cycles ALU operations, 1 input operands 1211def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read], 1212 (instrs 1213 FABSD_rec, FABSS_rec, 1214 FMR_rec, 1215 FNABSD_rec, FNABSS_rec, 1216 FNEGD_rec, FNEGS_rec, 1217 MTFSB1, 1218 RFEBB, 1219 SC 1220)>; 1221 1222// 2-way crack instructions 1223// 3 Cycles ALU operations, and 3 Cycles ALU operations, 2 input operands 1224def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 1225 (instrs 1226 ADDC, ADDC8, 1227 ADDC8_rec, ADDC_rec, 1228 ADDC8O, ADDCO, 1229 FCPSGND_rec, FCPSGNS_rec, 1230 MTFSF, MTFSFb, 1231 MTFSFI, MTFSFIb, 1232 SUBFC, SUBFC8, 1233 SUBFC8_rec, SUBFC_rec, 1234 SUBFC8O, SUBFCO 1235)>; 1236 1237// 2-way crack instructions 1238// 3 Cycles ALU operations, and 3 Cycles ALU operations, 3 input operands 1239def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read, P10FX_Read], 1240 (instrs 1241 MTFSFI_rec 1242)>; 1243 1244// 2-way crack instructions 1245// 3 Cycles ALU operations, and 3 Cycles ALU operations, 4 input operands 1246def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read, P10FX_Read, P10FX_Read], 1247 (instrs 1248 MTFSF_rec 1249)>; 1250 1251// 4-way crack instructions 1252// 3 Cycles ALU operations, 3 Cycles ALU operations, 3 Cycles ALU operations, and 3 Cycles ALU operations, 2 input operands 1253def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 1254 (instrs 1255 ADDC8O_rec, ADDCO_rec, 1256 SUBFC8O_rec, SUBFCO_rec 1257)>; 1258 1259// 2-way crack instructions 1260// 3 Cycles ALU operations, and 4 Cycles Permute operations, 1 input operands 1261def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_PM_4C, P10W_DISP_ANY], 1262 (instrs 1263 VSTRIBL_rec, 1264 VSTRIBR_rec, 1265 VSTRIHL_rec, 1266 VSTRIHR_rec 1267)>; 1268 1269// 2-way crack instructions 1270// 3 Cycles ALU operations, and 3 Cycles ALU operations, 2 input operands 1271def : InstRW<[P10W_FX_3C, P10W_DISP_PAIR, P10W_FX_3C, P10FX_Read, P10FX_Read], 1272 (instrs 1273 MTCRF, MTCRF8 1274)>; 1275 1276// 6 Cycles Load operations, 1 input operands 1277def : InstRW<[P10W_LD_6C, P10W_DISP_ANY, P10LD_Read], 1278 (instrs 1279 LBZ, LBZ8, 1280 LD, LDtoc, LDtocBA, LDtocCPT, LDtocJTI, LDtocL, SPILLTOVSR_LD, 1281 LDBRX, 1282 DFLOADf32, DFLOADf64, LFD, 1283 LFDX, XFLOADf32, XFLOADf64, 1284 LFIWAX, LIWAX, 1285 LFIWZX, LIWZX, 1286 LHA, LHA8, 1287 LHAX, LHAX8, 1288 LHBRX, LHBRX8, 1289 LHZ, LHZ8, 1290 LVEBX, 1291 LVEHX, 1292 LVEWX, 1293 LVX, 1294 LVXL, 1295 LWA, LWA_32, 1296 LWAX, LWAX_32, 1297 LWBRX, LWBRX8, 1298 LWZ, LWZ8, LWZtoc, LWZtocL, 1299 LXSD, 1300 LXSDX, 1301 LXSIBZX, 1302 LXSIHZX, 1303 LXSIWAX, 1304 LXSIWZX, 1305 LXV, 1306 LXVB16X, 1307 LXVD2X, 1308 LXVDSX, 1309 LXVH8X, 1310 LXVRBX, 1311 LXVRDX, 1312 LXVRHX, 1313 LXVRWX, 1314 LXVW4X, 1315 LXVWSX, 1316 LXVX 1317)>; 1318 1319// 6 Cycles Load operations, 2 input operands 1320def : InstRW<[P10W_LD_6C, P10W_DISP_ANY, P10LD_Read, P10LD_Read], 1321 (instrs 1322 DCBT, 1323 DCBTST, 1324 ICBT, 1325 LBZX, LBZX8, LBZXTLS, LBZXTLS_, LBZXTLS_32, 1326 LDX, LDXTLS, LDXTLS_, SPILLTOVSR_LDX, 1327 LHZX, LHZX8, LHZXTLS, LHZXTLS_, LHZXTLS_32, 1328 LWZX, LWZX8, LWZXTLS, LWZXTLS_, LWZXTLS_32, 1329 LXVL, 1330 LXVLL 1331)>; 1332 1333// 2-way crack instructions 1334// 6 Cycles Load operations, and 13 Cycles Decimal Floating Point operations, 2 input operands 1335def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DF_13C, P10W_DISP_ANY], 1336 (instrs 1337 HASHCHK, 1338 HASHCHKP 1339)>; 1340 1341// Single crack instructions 1342// 6 Cycles Load operations, 0 input operands 1343def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DISP_ANY], 1344 (instrs 1345 SLBIA 1346)>; 1347 1348// Single crack instructions 1349// 6 Cycles Load operations, 1 input operands 1350def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DISP_ANY, P10LD_Read], 1351 (instrs 1352 DARN, 1353 LBARX, LBARXL, 1354 LDARX, LDARXL, 1355 LHARX, LHARXL, 1356 LWARX, LWARXL, 1357 SLBFEE_rec, 1358 SLBIE, 1359 SLBMFEE, 1360 SLBMFEV 1361)>; 1362 1363// Single crack instructions 1364// 6 Cycles Load operations, 2 input operands 1365def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DISP_ANY, P10LD_Read, P10LD_Read], 1366 (instrs 1367 LBZCIX, 1368 LDCIX, 1369 LHZCIX, 1370 LWZCIX, 1371 MTSPR, MTSPR8, MTSR, MTVRSAVE, MTVRSAVEv 1372)>; 1373 1374// Expand instructions 1375// 6 Cycles Load operations, 6 Cycles Load operations, 6 Cycles Load operations, and 6 Cycles Load operations, 1 input operands 1376def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10LD_Read], 1377 (instrs 1378 LMW 1379)>; 1380 1381// Expand instructions 1382// 6 Cycles Load operations, 6 Cycles Load operations, 6 Cycles Load operations, and 6 Cycles Load operations, 2 input operands 1383def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10LD_Read, P10LD_Read], 1384 (instrs 1385 LSWI 1386)>; 1387 1388// 2-way crack instructions 1389// 6 Cycles Load operations, and 3 Cycles Simple Fixed-point (SFX) operations, 1 input operands 1390def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_SX_3C, P10W_DISP_ANY], 1391 (instrs 1392 LBZU, LBZU8, 1393 LBZUX, LBZUX8, 1394 LDU, 1395 LDUX, 1396 LFDU, 1397 LFDUX, 1398 LHAU, LHAU8, 1399 LHAUX, LHAUX8, 1400 LHZU, LHZU8, 1401 LHZUX, LHZUX8, 1402 LWAUX, 1403 LWZU, LWZU8, 1404 LWZUX, LWZUX8 1405)>; 1406 1407// 6 Cycles Load operations, 1 input operands 1408def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10LD_Read], 1409 (instrs 1410 PLBZ, PLBZ8, PLBZ8pc, PLBZpc, 1411 PLD, PLDpc, 1412 PLFD, PLFDpc, 1413 PLFS, PLFSpc, 1414 PLHA, PLHA8, PLHA8pc, PLHApc, 1415 PLHZ, PLHZ8, PLHZ8pc, PLHZpc, 1416 PLWA, PLWA8, PLWA8pc, PLWApc, 1417 PLWZ, PLWZ8, PLWZ8pc, PLWZpc, 1418 PLXSD, PLXSDpc, 1419 PLXSSP, PLXSSPpc, 1420 PLXV, PLXVpc, 1421 PLXVP, PLXVPpc 1422)>; 1423 1424// 2-way crack instructions 1425// 6 Cycles Load operations, and 4 Cycles ALU2 operations, 1 input operands 1426def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C], 1427 (instrs 1428 LFS, 1429 LFSX, 1430 LXSSP, 1431 LXSSPX 1432)>; 1433 1434// 4-way crack instructions 1435// 6 Cycles Load operations, 4 Cycles ALU2 operations, 3 Cycles Simple Fixed-point (SFX) operations, and 3 Cycles ALU operations, 1 input operands 1436def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C, P10W_SX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY], 1437 (instrs 1438 LFSU, 1439 LFSUX 1440)>; 1441 1442// 2-way crack instructions 1443// 6 Cycles Load operations, and 6 Cycles Load operations, 1 input operands 1444def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_LD_6C, P10W_DISP_PAIR, P10LD_Read], 1445 (instrs 1446 TLBIEL 1447)>; 1448 1449// 2-way crack instructions 1450// 6 Cycles Load operations, and 6 Cycles Load operations, 2 input operands 1451def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_LD_6C, P10W_DISP_PAIR, P10LD_Read, P10LD_Read], 1452 (instrs 1453 SLBMTE 1454)>; 1455 1456// 2-way crack instructions 1457// 6 Cycles Load operations, and 3 Cycles Simple Fixed-point (SFX) operations, 1 input operands 1458def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_SX_3C], 1459 (instrs 1460 LXVP, 1461 LXVPX 1462)>; 1463 1464// Single crack instructions 1465// 13 Cycles Unknown operations, 1 input operands 1466def : InstRW<[P10W_MFL_13C, P10W_DISP_EVEN, P10W_DISP_ANY], 1467 (instrs 1468 MFSPR, MFSPR8, MFSR, MFTB8, MFVRSAVE, MFVRSAVEv 1469)>; 1470 1471// 10 Cycles SIMD Matrix Multiply Engine operations, 0 input operands 1472def : InstRW<[P10W_MM_10C, P10W_DISP_ANY], 1473 (instrs 1474 XXSETACCZ 1475)>; 1476 1477// 10 Cycles SIMD Matrix Multiply Engine operations, 2 input operands 1478def : InstRW<[P10W_MM_10C, P10W_DISP_ANY, P10MM_Read, P10MM_Read], 1479 (instrs 1480 XVBF16GER2, 1481 XVF16GER2, 1482 XVF32GER, 1483 XVF64GER, 1484 XVI16GER2, 1485 XVI16GER2S, 1486 XVI4GER8, 1487 XVI8GER4 1488)>; 1489 1490// 10 Cycles SIMD Matrix Multiply Engine operations, 3 input operands 1491def : InstRW<[P10W_MM_10C, P10W_DISP_ANY, P10MM_Read, P10MM_Read, P10MM_Read], 1492 (instrs 1493 XVBF16GER2NN, 1494 XVBF16GER2NP, 1495 XVBF16GER2PN, 1496 XVBF16GER2PP, 1497 XVF16GER2NN, 1498 XVF16GER2NP, 1499 XVF16GER2PN, 1500 XVF16GER2PP, 1501 XVF32GERNN, 1502 XVF32GERNP, 1503 XVF32GERPN, 1504 XVF32GERPP, 1505 XVF64GERNN, 1506 XVF64GERNP, 1507 XVF64GERPN, 1508 XVF64GERPP, 1509 XVI16GER2PP, 1510 XVI16GER2SPP, 1511 XVI4GER8PP, 1512 XVI8GER4PP, 1513 XVI8GER4SPP 1514)>; 1515 1516// 10 Cycles SIMD Matrix Multiply Engine operations, 4 input operands 1517def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10MM_Read, P10MM_Read, P10MM_Read, P10MM_Read], 1518 (instrs 1519 PMXVF32GER, 1520 PMXVF64GER 1521)>; 1522 1523// 10 Cycles SIMD Matrix Multiply Engine operations, 5 input operands 1524def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10MM_Read, P10MM_Read, P10MM_Read, P10MM_Read, P10MM_Read], 1525 (instrs 1526 PMXVBF16GER2, 1527 PMXVF16GER2, 1528 PMXVF32GERNN, 1529 PMXVF32GERNP, 1530 PMXVF32GERPN, 1531 PMXVF32GERPP, 1532 PMXVF64GERNN, 1533 PMXVF64GERNP, 1534 PMXVF64GERPN, 1535 PMXVF64GERPP, 1536 PMXVI16GER2, 1537 PMXVI16GER2S, 1538 PMXVI4GER8, 1539 PMXVI8GER4 1540)>; 1541 1542// 10 Cycles SIMD Matrix Multiply Engine operations, 6 input operands 1543def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10MM_Read, P10MM_Read, P10MM_Read, P10MM_Read, P10MM_Read, P10MM_Read], 1544 (instrs 1545 PMXVBF16GER2NN, 1546 PMXVBF16GER2NP, 1547 PMXVBF16GER2PN, 1548 PMXVBF16GER2PP, 1549 PMXVF16GER2NN, 1550 PMXVF16GER2NP, 1551 PMXVF16GER2PN, 1552 PMXVF16GER2PP, 1553 PMXVI16GER2PP, 1554 PMXVI16GER2SPP, 1555 PMXVI4GER8PP, 1556 PMXVI8GER4PP, 1557 PMXVI8GER4SPP 1558)>; 1559 1560// 2-way crack instructions 1561// 10 Cycles SIMD Matrix Multiply Engine operations, and 3 Cycles ALU operations, 1 input operands 1562def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10W_FX_3C], 1563 (instrs 1564 XXMTACC 1565)>; 1566 1567// 4-way crack instructions 1568// 10 Cycles SIMD Matrix Multiply Engine operations, 3 Cycles ALU operations, 10 Cycles SIMD Matrix Multiply Engine operations, and 3 Cycles ALU operations, 1 input operands 1569def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10W_FX_3C, P10W_MM_10C, P10W_DISP_PAIR, P10W_FX_3C], 1570 (instrs 1571 XXMFACC 1572)>; 1573 1574// 5 Cycles GPR Multiply operations, 2 input operands 1575def : InstRW<[P10W_MU_5C, P10W_DISP_ANY, P10MU_Read, P10MU_Read], 1576 (instrs 1577 MULHD, 1578 MULHDU, 1579 MULHW, 1580 MULHWU, 1581 MULLD, 1582 MULLDO, 1583 MULLI, MULLI8, 1584 MULLW, 1585 MULLWO, 1586 VMULHSD, 1587 VMULHUD, 1588 VMULLD 1589)>; 1590 1591// 5 Cycles GPR Multiply operations, 3 input operands 1592def : InstRW<[P10W_MU_5C, P10W_DISP_ANY, P10MU_Read, P10MU_Read, P10MU_Read], 1593 (instrs 1594 MADDHD, 1595 MADDHDU, 1596 MADDLD, MADDLD8 1597)>; 1598 1599// 2-way crack instructions 1600// 5 Cycles GPR Multiply operations, and 3 Cycles ALU operations, 2 input operands 1601def : InstRW<[P10W_MU_5C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1602 (instrs 1603 MULHD_rec, 1604 MULHDU_rec, 1605 MULHW_rec, 1606 MULHWU_rec, 1607 MULLD_rec, 1608 MULLDO_rec, 1609 MULLW_rec, 1610 MULLWO_rec 1611)>; 1612 1613// 4 Cycles Permute operations, 0 input operands 1614def : InstRW<[P10W_PM_4C, P10W_DISP_ANY], 1615 (instrs 1616 VSPLTISW, V_SETALLONES, V_SETALLONESB, V_SETALLONESH 1617)>; 1618 1619// 4 Cycles Permute operations, 1 input operands 1620def : InstRW<[P10W_PM_4C, P10W_DISP_ANY, P10PM_Read], 1621 (instrs 1622 LVSL, 1623 LVSR, 1624 MFVSRLD, 1625 MTVSRWS, 1626 VCLZLSBB, 1627 VCTZLSBB, 1628 VGBBD, 1629 VPRTYBQ, 1630 VSPLTISB, 1631 VSPLTISH, 1632 VSTRIBL, 1633 VSTRIBR, 1634 VSTRIHL, 1635 VSTRIHR, 1636 VUPKHPX, 1637 VUPKHSB, 1638 VUPKHSH, 1639 VUPKHSW, 1640 VUPKLPX, 1641 VUPKLSB, 1642 VUPKLSH, 1643 VUPKLSW, 1644 XVCVBF16SPN, 1645 XXBRD, 1646 XXBRH, 1647 XXBRQ, 1648 XXBRW, 1649 XXSPLTIB 1650)>; 1651 1652// 4 Cycles Permute operations, 2 input operands 1653def : InstRW<[P10W_PM_4C, P10W_DISP_ANY, P10PM_Read, P10PM_Read], 1654 (instrs 1655 BPERMD, 1656 MTVSRDD, 1657 VBPERMD, 1658 VBPERMQ, 1659 VCLRLB, 1660 VCLRRB, 1661 VEXTRACTD, 1662 VEXTRACTUB, 1663 VEXTRACTUH, 1664 VEXTRACTUW, 1665 VEXTUBLX, 1666 VEXTUBRX, 1667 VEXTUHLX, 1668 VEXTUHRX, 1669 VEXTUWLX, 1670 VEXTUWRX, 1671 VINSERTD, 1672 VINSERTW, 1673 VMRGHB, 1674 VMRGHH, 1675 VMRGHW, 1676 VMRGLB, 1677 VMRGLH, 1678 VMRGLW, 1679 VPKPX, 1680 VPKSDSS, 1681 VPKSDUS, 1682 VPKSHSS, 1683 VPKSHUS, 1684 VPKSWSS, 1685 VPKSWUS, 1686 VPKUDUM, 1687 VPKUDUS, 1688 VPKUHUM, 1689 VPKUHUS, 1690 VPKUWUM, 1691 VPKUWUS, 1692 VSL, 1693 VSLO, 1694 VSLV, 1695 VSPLTB, VSPLTBs, 1696 VSPLTH, VSPLTHs, 1697 VSPLTW, 1698 VSR, 1699 VSRO, 1700 VSRV, 1701 XXEXTRACTUW, 1702 XXGENPCVDM, 1703 XXGENPCVHM, 1704 XXGENPCVWM, 1705 XXMRGHW, 1706 XXMRGLW, 1707 XXPERM, 1708 XXPERMDI, XXPERMDIs, 1709 XXPERMR, 1710 XXSLDWI, XXSLDWIs, 1711 XXSPLTW, XXSPLTWs 1712)>; 1713 1714// 4 Cycles Permute operations, 3 input operands 1715def : InstRW<[P10W_PM_4C, P10W_DISP_ANY, P10PM_Read, P10PM_Read, P10PM_Read], 1716 (instrs 1717 VEXTDDVLX, 1718 VEXTDDVRX, 1719 VEXTDUBVLX, 1720 VEXTDUBVRX, 1721 VEXTDUHVLX, 1722 VEXTDUHVRX, 1723 VEXTDUWVLX, 1724 VEXTDUWVRX, 1725 VINSBLX, 1726 VINSBRX, 1727 VINSBVLX, 1728 VINSBVRX, 1729 VINSD, 1730 VINSDLX, 1731 VINSDRX, 1732 VINSERTB, 1733 VINSERTH, 1734 VINSHLX, 1735 VINSHRX, 1736 VINSHVLX, 1737 VINSHVRX, 1738 VINSW, 1739 VINSWLX, 1740 VINSWRX, 1741 VINSWVLX, 1742 VINSWVRX, 1743 VPERM, 1744 VPERMR, 1745 VPERMXOR, 1746 VSLDBI, 1747 VSLDOI, 1748 VSRDBI, 1749 XXINSERTW 1750)>; 1751 1752// 2-way crack instructions 1753// 4 Cycles Permute operations, and 7 Cycles VMX Multiply operations, 2 input operands 1754def : InstRW<[P10W_PM_4C, P10W_DISP_EVEN, P10W_vMU_7C, P10W_DISP_ANY], 1755 (instrs 1756 VSUMSWS 1757)>; 1758 1759// 4 Cycles Permute operations, 1 input operands 1760def : InstRW<[P10W_PM_4C, P10W_DISP_PAIR, P10PM_Read], 1761 (instrs 1762 XXSPLTIDP, 1763 XXSPLTIW 1764)>; 1765 1766// 4 Cycles Permute operations, 3 input operands 1767def : InstRW<[P10W_PM_4C, P10W_DISP_PAIR, P10PM_Read, P10PM_Read, P10PM_Read], 1768 (instrs 1769 XXBLENDVB, 1770 XXBLENDVD, 1771 XXBLENDVH, 1772 XXBLENDVW, 1773 XXSPLTI32DX 1774)>; 1775 1776// 4 Cycles Permute operations, 4 input operands 1777def : InstRW<[P10W_PM_4C, P10W_DISP_PAIR, P10PM_Read, P10PM_Read, P10PM_Read, P10PM_Read], 1778 (instrs 1779 XXEVAL, 1780 XXPERMX 1781)>; 1782 1783// 3 Cycles Store operations, 1 input operands 1784def : InstRW<[P10W_ST_3C, P10W_DISP_ANY, P10ST_Read], 1785 (instrs 1786 DCBST, 1787 DCBZ, 1788 ICBI 1789)>; 1790 1791// 3 Cycles Store operations, 2 input operands 1792def : InstRW<[P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read], 1793 (instrs 1794 DCBF, 1795 PSTXVP, PSTXVPpc, 1796 STB, STB8, 1797 STBU, STBU8, 1798 STBUX, STBUX8, 1799 SPILLTOVSR_ST, STD, 1800 STDBRX, 1801 STDU, 1802 STDUX, 1803 DFSTOREf32, DFSTOREf64, STFD, 1804 STFDU, 1805 STFDUX, 1806 STFDX, 1807 STFIWX, STIWX, 1808 STFS, 1809 STFSU, 1810 STFSUX, 1811 STFSX, 1812 STH, STH8, 1813 STHBRX, 1814 STHU, STHU8, 1815 STHUX, STHUX8, 1816 STVEBX, 1817 STVEHX, 1818 STVEWX, 1819 STVX, 1820 STVXL, 1821 STW, STW8, 1822 STWBRX, 1823 STWU, STWU8, 1824 STWUX, STWUX8, 1825 STXSD, 1826 STXSDX, 1827 STXSIBX, STXSIBXv, 1828 STXSIHX, STXSIHXv, 1829 STXSIWX, 1830 STXSSP, 1831 STXSSPX, 1832 STXV, 1833 STXVB16X, 1834 STXVD2X, 1835 STXVH8X, 1836 STXVRBX, 1837 STXVRDX, 1838 STXVRHX, 1839 STXVRWX, 1840 STXVW4X, 1841 STXVX 1842)>; 1843 1844// 3 Cycles Store operations, 3 input operands 1845def : InstRW<[P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read, P10ST_Read], 1846 (instrs 1847 CP_COPY, CP_COPY8, 1848 STBX, STBX8, STBXTLS, STBXTLS_, STBXTLS_32, 1849 SPILLTOVSR_STX, STDX, STDXTLS, STDXTLS_, 1850 STHX, STHX8, STHXTLS, STHXTLS_, STHXTLS_32, 1851 STWX, STWX8, STWXTLS, STWXTLS_, STWXTLS_32, 1852 STXVL, 1853 STXVLL 1854)>; 1855 1856// Single crack instructions 1857// 3 Cycles Store operations, 0 input operands 1858def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY], 1859 (instrs 1860 EnforceIEIO, 1861 MSGSYNC, 1862 SLBSYNC, 1863 TCHECK, 1864 TLBSYNC 1865)>; 1866 1867// Single crack instructions 1868// 3 Cycles Store operations, 1 input operands 1869def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read], 1870 (instrs 1871 TEND 1872)>; 1873 1874// Single crack instructions 1875// 3 Cycles Store operations, 2 input operands 1876def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read, P10ST_Read], 1877 (instrs 1878 SLBIEG, 1879 STBCX, 1880 STDCX, 1881 STHCX, 1882 STWCX, 1883 TLBIE 1884)>; 1885 1886// Single crack instructions 1887// 3 Cycles Store operations, 3 input operands 1888def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read, P10ST_Read, P10ST_Read], 1889 (instrs 1890 CP_PASTE8_rec, CP_PASTE_rec, 1891 STBCIX, 1892 STDCIX, 1893 STHCIX, 1894 STWCIX 1895)>; 1896 1897// 2-way crack instructions 1898// 3 Cycles Store operations, and 3 Cycles ALU operations, 0 input operands 1899def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1900 (instrs 1901 ISYNC 1902)>; 1903 1904// 2-way crack instructions 1905// 3 Cycles Store operations, and 3 Cycles ALU operations, 1 input operands 1906def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1907 (instrs 1908 SYNC 1909)>; 1910 1911// Expand instructions 1912// 3 Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, 3 Cycles ALU operations, 6 Cycles Load operations, and 3 Cycles Store operations, 2 input operands 1913def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY], 1914 (instrs 1915 LDAT, 1916 LWAT 1917)>; 1918 1919// 4-way crack instructions 1920// 3 Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, and 3 Cycles Store operations, 3 input operands 1921def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY], 1922 (instrs 1923 STDAT, 1924 STWAT 1925)>; 1926 1927// Expand instructions 1928// 3 Cycles Store operations, 3 Cycles Store operations, 3 Cycles Store operations, and 3 Cycles Store operations, 2 input operands 1929def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read], 1930 (instrs 1931 STMW 1932)>; 1933 1934// Expand instructions 1935// 3 Cycles Store operations, 3 Cycles Store operations, 3 Cycles Store operations, and 3 Cycles Store operations, 3 input operands 1936def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read, P10ST_Read], 1937 (instrs 1938 STSWI 1939)>; 1940 1941// 3 Cycles Store operations, 2 input operands 1942def : InstRW<[P10W_ST_3C, P10W_DISP_PAIR, P10ST_Read, P10ST_Read], 1943 (instrs 1944 PSTB, PSTB8, PSTB8pc, PSTBpc, 1945 PSTD, PSTDpc, 1946 PSTFD, PSTFDpc, 1947 PSTFS, PSTFSpc, 1948 PSTH, PSTH8, PSTH8pc, PSTHpc, 1949 PSTW, PSTW8, PSTW8pc, PSTWpc, 1950 PSTXSD, PSTXSDpc, 1951 PSTXSSP, PSTXSSPpc, 1952 PSTXV, PSTXVpc 1953)>; 1954 1955// 2-way crack instructions 1956// 3 Cycles Store operations, and 3 Cycles Store operations, 2 input operands 1957def : InstRW<[P10W_ST_3C, P10W_DISP_PAIR, P10W_ST_3C, P10ST_Read, P10ST_Read], 1958 (instrs 1959 STXVP, 1960 STXVPX 1961)>; 1962 1963// FIXME - Miss scheduling information from datasheet 1964// Temporary set it as 1 Cycles Simple Fixed-point (SFX) operations, 0 input operands 1965def : InstRW<[P10W_SX, P10W_DISP_ANY], 1966 (instrs 1967 ATTN, 1968 CP_ABORT, 1969 DCBA, 1970 DCBI, 1971 DCBZL, 1972 DCCCI, 1973 ICBLC, 1974 ICBLQ, 1975 ICBTLS, 1976 ICCCI, 1977 LA, 1978 LDMX, 1979 MFDCR, 1980 MFPMR, 1981 MFSRIN, 1982 MSYNC, 1983 MTDCR, 1984 MTPMR, 1985 MTSRIN, 1986 NAP, 1987 TLBIA, 1988 TLBLD, 1989 TLBLI, 1990 TLBRE2, 1991 TLBSX2, 1992 TLBSX2D, 1993 TLBWE2 1994)>; 1995 1996// Single crack instructions 1997// 3 Cycles Simple Fixed-point (SFX) operations, 0 input operands 1998def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_DISP_ANY], 1999 (instrs 2000 CLRBHRB, 2001 MFMSR 2002)>; 2003 2004// Single crack instructions 2005// 3 Cycles Simple Fixed-point (SFX) operations, 1 input operands 2006def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10SX_Read], 2007 (instrs 2008 MFTB 2009)>; 2010 2011// Single crack instructions 2012// 3 Cycles Simple Fixed-point (SFX) operations, 2 input operands 2013def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10SX_Read, P10SX_Read], 2014 (instrs 2015 MFBHRBE, 2016 MTMSR, 2017 MTMSRD 2018)>; 2019 2020// 2-way crack instructions 2021// 3 Cycles Simple Fixed-point (SFX) operations, and 3 Cycles ALU operations, 1 input operands 2022def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 2023 (instrs 2024 ADDPCIS 2025)>; 2026 2027// 3 Cycles Simple Fixed-point (SFX) operations, 1 input operands 2028def : InstRW<[P10W_SX_3C, P10W_DISP_PAIR, P10SX_Read], 2029 (instrs 2030 PADDI, PADDI8, PADDI8pc, PADDIpc, PLI, PLI8 2031)>; 2032 2033// 7 Cycles VMX Multiply operations, 2 input operands 2034def : InstRW<[P10W_vMU_7C, P10W_DISP_ANY, P10vMU_Read, P10vMU_Read], 2035 (instrs 2036 VMULESB, 2037 VMULESD, 2038 VMULESH, 2039 VMULESW, 2040 VMULEUB, 2041 VMULEUD, 2042 VMULEUH, 2043 VMULEUW, 2044 VMULHSW, 2045 VMULHUW, 2046 VMULOSB, 2047 VMULOSD, 2048 VMULOSH, 2049 VMULOSW, 2050 VMULOUB, 2051 VMULOUD, 2052 VMULOUH, 2053 VMULOUW, 2054 VMULUWM, 2055 VSUM2SWS, 2056 VSUM4SBS, 2057 VSUM4SHS, 2058 VSUM4UBS 2059)>; 2060 2061// 7 Cycles VMX Multiply operations, 3 input operands 2062def : InstRW<[P10W_vMU_7C, P10W_DISP_ANY, P10vMU_Read, P10vMU_Read, P10vMU_Read], 2063 (instrs 2064 VMHADDSHS, 2065 VMHRADDSHS, 2066 VMLADDUHM, 2067 VMSUMCUD, 2068 VMSUMMBM, 2069 VMSUMSHM, 2070 VMSUMSHS, 2071 VMSUMUBM, 2072 VMSUMUDM, 2073 VMSUMUHM, 2074 VMSUMUHS 2075)>; 2076