1//===--- P10InstrResources.td - P10 Scheduling Definitions -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// Automatically generated file, do not edit! 9// 10// This file defines the itinerary class data for the POWER10 processor. 11// 12//===----------------------------------------------------------------------===// 13// 22 Cycles Binary Floating Point operations, 2 input operands 14def : InstRW<[P10W_BF_22C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 15 (instrs 16 FDIVS, 17 XSDIVSP 18)>; 19 20// 2-way crack instructions 21// 22 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands 22def : InstRW<[P10W_BF_22C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 23 (instrs 24 FDIVS_rec 25)>; 26 27// 24 Cycles Binary Floating Point operations, 2 input operands 28def : InstRW<[P10W_BF_24C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 29 (instrs 30 XVDIVSP 31)>; 32 33// 26 Cycles Binary Floating Point operations, 1 input operands 34def : InstRW<[P10W_BF_26C, P10W_DISP_ANY, P10BF_Read], 35 (instrs 36 FSQRTS, 37 XSSQRTSP 38)>; 39 40// 2-way crack instructions 41// 26 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands 42def : InstRW<[P10W_BF_26C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 43 (instrs 44 FSQRTS_rec 45)>; 46 47// 27 Cycles Binary Floating Point operations, 1 input operands 48def : InstRW<[P10W_BF_27C, P10W_DISP_ANY, P10BF_Read], 49 (instrs 50 XVSQRTSP 51)>; 52 53// 27 Cycles Binary Floating Point operations, 2 input operands 54def : InstRW<[P10W_BF_27C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 55 (instrs 56 FDIV, 57 XSDIVDP, 58 XVDIVDP 59)>; 60 61// 2-way crack instructions 62// 27 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands 63def : InstRW<[P10W_BF_27C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 64 (instrs 65 FDIV_rec 66)>; 67 68// 36 Cycles Binary Floating Point operations, 1 input operands 69def : InstRW<[P10W_BF_36C, P10W_DISP_ANY, P10BF_Read], 70 (instrs 71 FSQRT, 72 XSSQRTDP, 73 XVSQRTDP 74)>; 75 76// 2-way crack instructions 77// 36 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands 78def : InstRW<[P10W_BF_36C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 79 (instrs 80 FSQRT_rec 81)>; 82 83// 7 Cycles Binary Floating Point operations, 1 input operands 84def : InstRW<[P10W_BF_7C, P10W_DISP_ANY, P10BF_Read], 85 (instrs 86 FCFID, 87 FCFIDS, 88 FCFIDU, 89 FCFIDUS, 90 FCTID, 91 FCTIDU, 92 FCTIDUZ, 93 FCTIDZ, 94 FCTIW, 95 FCTIWU, 96 FCTIWUZ, 97 FCTIWZ, 98 FRE, 99 FRES, 100 FRIMD, FRIMS, 101 FRIND, FRINS, 102 FRIPD, FRIPS, 103 FRIZD, FRIZS, 104 FRSP, 105 FRSQRTE, 106 FRSQRTES, 107 VCFSX, VCFSX_0, 108 VCFUX, VCFUX_0, 109 VCTSXS, VCTSXS_0, 110 VCTUXS, VCTUXS_0, 111 VLOGEFP, 112 VREFP, 113 VRFIM, 114 VRFIN, 115 VRFIP, 116 VRFIZ, 117 VRSQRTEFP, 118 XSCVDPHP, 119 XSCVDPSP, 120 XSCVDPSPN, 121 XSCVDPSXDS, XSCVDPSXDSs, 122 XSCVDPSXWS, XSCVDPSXWSs, 123 XSCVDPUXDS, XSCVDPUXDSs, 124 XSCVDPUXWS, XSCVDPUXWSs, 125 XSCVSPDP, 126 XSCVSXDDP, 127 XSCVSXDSP, 128 XSCVUXDDP, 129 XSCVUXDSP, 130 XSRDPI, 131 XSRDPIC, 132 XSRDPIM, 133 XSRDPIP, 134 XSRDPIZ, 135 XSREDP, 136 XSRESP, 137 XSRSP, 138 XSRSQRTEDP, 139 XSRSQRTESP, 140 XVCVDPSP, 141 XVCVDPSXDS, 142 XVCVDPSXWS, 143 XVCVDPUXDS, 144 XVCVDPUXWS, 145 XVCVSPBF16, 146 XVCVSPDP, 147 XVCVSPHP, 148 XVCVSPSXDS, 149 XVCVSPSXWS, 150 XVCVSPUXDS, 151 XVCVSPUXWS, 152 XVCVSXDDP, 153 XVCVSXDSP, 154 XVCVSXWDP, 155 XVCVSXWSP, 156 XVCVUXDDP, 157 XVCVUXDSP, 158 XVCVUXWDP, 159 XVCVUXWSP, 160 XVRDPI, 161 XVRDPIC, 162 XVRDPIM, 163 XVRDPIP, 164 XVRDPIZ, 165 XVREDP, 166 XVRESP, 167 XVRSPI, 168 XVRSPIC, 169 XVRSPIM, 170 XVRSPIP, 171 XVRSPIZ, 172 XVRSQRTEDP, 173 XVRSQRTESP 174)>; 175 176// 7 Cycles Binary Floating Point operations, 2 input operands 177def : InstRW<[P10W_BF_7C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 178 (instrs 179 FADD, 180 FADDS, 181 FMUL, 182 FMULS, 183 FSUB, 184 FSUBS, 185 VADDFP, 186 VSUBFP, 187 XSADDDP, 188 XSADDSP, 189 XSMULDP, 190 XSMULSP, 191 XSSUBDP, 192 XSSUBSP, 193 XVADDDP, 194 XVADDSP, 195 XVMULDP, 196 XVMULSP, 197 XVSUBDP, 198 XVSUBSP 199)>; 200 201// 7 Cycles Binary Floating Point operations, 3 input operands 202def : InstRW<[P10W_BF_7C, P10W_DISP_ANY, P10BF_Read, P10BF_Read, P10BF_Read], 203 (instrs 204 FMADD, 205 FMADDS, 206 FMSUB, 207 FMSUBS, 208 FNMADD, 209 FNMADDS, 210 FNMSUB, 211 FNMSUBS, 212 FSELD, FSELS, 213 VMADDFP, 214 VNMSUBFP, 215 XSMADDADP, 216 XSMADDASP, 217 XSMADDMDP, 218 XSMADDMSP, 219 XSMSUBADP, 220 XSMSUBASP, 221 XSMSUBMDP, 222 XSMSUBMSP, 223 XSNMADDADP, 224 XSNMADDASP, 225 XSNMADDMDP, 226 XSNMADDMSP, 227 XSNMSUBADP, 228 XSNMSUBASP, 229 XSNMSUBMDP, 230 XSNMSUBMSP, 231 XVMADDADP, 232 XVMADDASP, 233 XVMADDMDP, 234 XVMADDMSP, 235 XVMSUBADP, 236 XVMSUBASP, 237 XVMSUBMDP, 238 XVMSUBMSP, 239 XVNMADDADP, 240 XVNMADDASP, 241 XVNMADDMDP, 242 XVNMADDMSP, 243 XVNMSUBADP, 244 XVNMSUBASP, 245 XVNMSUBMDP, 246 XVNMSUBMSP 247)>; 248 249// 2-way crack instructions 250// 7 Cycles Binary Floating Point operations, and 7 Cycles Binary Floating Point operations, 1 input operands 251def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_BF_7C, P10W_DISP_ANY, P10BF_Read], 252 (instrs 253 VEXPTEFP 254)>; 255 256// 2-way crack instructions 257// 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands 258def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 259 (instrs 260 FADD_rec, 261 FADDS_rec, 262 FMUL_rec, 263 FMULS_rec, 264 FSUB_rec, 265 FSUBS_rec 266)>; 267 268// 2-way crack instructions 269// 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands 270def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 271 (instrs 272 FCFID_rec, 273 FCFIDS_rec, 274 FCFIDU_rec, 275 FCFIDUS_rec, 276 FCTID_rec, 277 FCTIDU_rec, 278 FCTIDUZ_rec, 279 FCTIDZ_rec, 280 FCTIW_rec, 281 FCTIWU_rec, 282 FCTIWUZ_rec, 283 FCTIWZ_rec, 284 FRE_rec, 285 FRES_rec, 286 FRIMD_rec, FRIMS_rec, 287 FRIND_rec, FRINS_rec, 288 FRIPD_rec, FRIPS_rec, 289 FRIZD_rec, FRIZS_rec, 290 FRSP_rec, 291 FRSQRTE_rec, 292 FRSQRTES_rec 293)>; 294 295// 2-way crack instructions 296// 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 3 input operands 297def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 298 (instrs 299 FMADD_rec, 300 FMADDS_rec, 301 FMSUB_rec, 302 FMSUBS_rec, 303 FNMADD_rec, 304 FNMADDS_rec, 305 FNMSUB_rec, 306 FNMSUBS_rec, 307 FSELD_rec, FSELS_rec 308)>; 309 310// 2 Cycles Branch operations, 0 input operands 311def : InstRW<[P10W_BR_2C, P10W_DISP_ANY], 312 (instrs 313 BCLR, BCLRn, BDNZLR, BDNZLR8, BDNZLRm, BDNZLRp, BDZLR, BDZLR8, BDZLRm, BDZLRp, gBCLR, 314 BCLRL, BCLRLn, BDNZLRL, BDNZLRLm, BDNZLRLp, BDZLRL, BDZLRLm, BDZLRLp, gBCLRL, 315 BL, BL8, BL8_NOP, BL8_NOP_RM, BL8_NOP_TLS, BL8_NOTOC, BL8_NOTOC_RM, BL8_NOTOC_TLS, BL8_RM, BL8_TLS, BL8_TLS_, BLR, BLR8, BLRL, BL_NOP, BL_NOP_RM, BL_RM, BL_TLS 316)>; 317 318// 2 Cycles Branch operations, 1 input operands 319def : InstRW<[P10W_BR_2C, P10W_DISP_ANY, P10BR_Read], 320 (instrs 321 B, BCC, BCCA, BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL, BCCLA, BCCLR, BCCLRL, CTRL_DEP, TAILB, TAILB8, 322 BA, TAILBA, TAILBA8, 323 BC, BCTR, BCTR8, BCTRL, BCTRL8, BCTRL8_LDinto_toc, BCTRL8_LDinto_toc_RM, BCTRL8_RM, BCTRL_LWZinto_toc, BCTRL_LWZinto_toc_RM, BCTRL_RM, BCn, BDNZ, BDNZ8, BDNZm, BDNZp, BDZ, BDZ8, BDZm, BDZp, TAILBCTR, TAILBCTR8, gBC, gBCat, 324 BCL, BCLalways, BCLn, BDNZL, BDNZLm, BDNZLp, BDZL, BDZLm, BDZLp, gBCL, gBCLat, 325 BLA, BLA8, BLA8_NOP, BLA8_NOP_RM, BLA8_RM, BLA_RM 326)>; 327 328// 2 Cycles Branch operations, 3 input operands 329def : InstRW<[P10W_BR_2C, P10W_DISP_ANY, P10BR_Read, P10BR_Read, P10BR_Read], 330 (instrs 331 BCCTR, BCCTR8, BCCTR8n, BCCTRn, gBCCTR, 332 BCCTRL, BCCTRL8, BCCTRL8n, BCCTRLn, gBCCTRL 333)>; 334 335// 2 Cycles Branch operations, 4 input operands 336def : InstRW<[P10W_BR_2C, P10W_DISP_ANY, P10BR_Read, P10BR_Read, P10BR_Read, P10BR_Read], 337 (instrs 338 BDNZA, BDNZAm, BDNZAp, BDZA, BDZAm, BDZAp, gBCA, gBCAat, 339 BDNZLA, BDNZLAm, BDNZLAp, BDZLA, BDZLAm, BDZLAp, gBCLA, gBCLAat 340)>; 341 342// 7 Cycles Crypto operations, 1 input operands 343def : InstRW<[P10W_CY_7C, P10W_DISP_ANY, P10CY_Read], 344 (instrs 345 VSBOX 346)>; 347 348// 7 Cycles Crypto operations, 2 input operands 349def : InstRW<[P10W_CY_7C, P10W_DISP_ANY, P10CY_Read, P10CY_Read], 350 (instrs 351 CFUGED, 352 CNTLZDM, 353 CNTTZDM, 354 PDEPD, 355 PEXTD, 356 VCFUGED, 357 VCIPHER, 358 VCIPHERLAST, 359 VCLZDM, 360 VCTZDM, 361 VGNB, 362 VNCIPHER, 363 VNCIPHERLAST, 364 VPDEPD, 365 VPEXTD, 366 VPMSUMB, 367 VPMSUMD, 368 VPMSUMH, 369 VPMSUMW 370)>; 371 372// 13 Cycles Decimal Floating Point operations, 1 input operands 373def : InstRW<[P10W_DF_13C, P10W_DISP_ANY, P10DF_Read], 374 (instrs 375 XSCVDPQP, 376 XSCVQPDP, 377 XSCVQPDPO, 378 XSCVQPSDZ, 379 XSCVQPSQZ, 380 XSCVQPSWZ, 381 XSCVQPUDZ, 382 XSCVQPUQZ, 383 XSCVQPUWZ, 384 XSCVSDQP, 385 XSCVSQQP, 386 XSCVUDQP, 387 XSCVUQQP 388)>; 389 390// 13 Cycles Decimal Floating Point operations, 2 input operands 391def : InstRW<[P10W_DF_13C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 392 (instrs 393 XSADDQP, 394 XSADDQPO, 395 XSSUBQP, 396 XSSUBQPO 397)>; 398 399// 13 Cycles Decimal Floating Point operations, 3 input operands 400def : InstRW<[P10W_DF_13C, P10W_DISP_ANY, P10DF_Read, P10DF_Read, P10DF_Read], 401 (instrs 402 BCDSR_rec, 403 XSRQPI, 404 XSRQPIX, 405 XSRQPXP 406)>; 407 408// 2-way crack instructions 409// 13 Cycles Decimal Floating Point operations, and 3 Cycles Store operations, 2 input operands 410def : InstRW<[P10W_DF_13C, P10W_DISP_EVEN, P10W_ST_3C, P10W_DISP_ANY], 411 (instrs 412 HASHST, HASHST8, 413 HASHSTP, HASHSTP8 414)>; 415 416// 24 Cycles Decimal Floating Point operations, 1 input operands 417def : InstRW<[P10W_DF_24C, P10W_DISP_ANY, P10DF_Read], 418 (instrs 419 BCDCTSQ_rec 420)>; 421 422// 25 Cycles Decimal Floating Point operations, 2 input operands 423def : InstRW<[P10W_DF_25C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 424 (instrs 425 XSMULQP, 426 XSMULQPO 427)>; 428 429// 25 Cycles Decimal Floating Point operations, 3 input operands 430def : InstRW<[P10W_DF_25C, P10W_DISP_ANY, P10DF_Read, P10DF_Read, P10DF_Read], 431 (instrs 432 XSMADDQP, 433 XSMADDQPO, 434 XSMSUBQP, 435 XSMSUBQPO, 436 XSNMADDQP, 437 XSNMADDQPO, 438 XSNMSUBQP, 439 XSNMSUBQPO 440)>; 441 442// 38 Cycles Decimal Floating Point operations, 2 input operands 443def : InstRW<[P10W_DF_38C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 444 (instrs 445 BCDCFSQ_rec 446)>; 447 448// 59 Cycles Decimal Floating Point operations, 2 input operands 449def : InstRW<[P10W_DF_59C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 450 (instrs 451 XSDIVQP, 452 XSDIVQPO 453)>; 454 455// 61 Cycles Decimal Floating Point operations, 2 input operands 456def : InstRW<[P10W_DF_61C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 457 (instrs 458 VDIVESQ, 459 VDIVEUQ, 460 VDIVSQ, 461 VDIVUQ 462)>; 463 464// 68 Cycles Decimal Floating Point operations, 2 input operands 465def : InstRW<[P10W_DF_68C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 466 (instrs 467 VMODSQ, 468 VMODUQ 469)>; 470 471// 77 Cycles Decimal Floating Point operations, 1 input operands 472def : InstRW<[P10W_DF_77C, P10W_DISP_ANY, P10DF_Read], 473 (instrs 474 XSSQRTQP, 475 XSSQRTQPO 476)>; 477 478// 20 Cycles Scalar Fixed-Point Divide operations, 2 input operands 479def : InstRW<[P10W_DV_20C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 480 (instrs 481 DIVW, 482 DIVWO, 483 DIVWU, 484 DIVWUO, 485 MODSW 486)>; 487 488// 2-way crack instructions 489// 20 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands 490def : InstRW<[P10W_DV_20C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 491 (instrs 492 DIVW_rec, 493 DIVWO_rec, 494 DIVWU_rec, 495 DIVWUO_rec 496)>; 497 498// 25 Cycles Scalar Fixed-Point Divide operations, 2 input operands 499def : InstRW<[P10W_DV_25C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 500 (instrs 501 DIVD, 502 DIVDO, 503 DIVDU, 504 DIVDUO, 505 DIVWE, 506 DIVWEO, 507 DIVWEU, 508 DIVWEUO 509)>; 510 511// 2-way crack instructions 512// 25 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands 513def : InstRW<[P10W_DV_25C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 514 (instrs 515 DIVD_rec, 516 DIVDO_rec, 517 DIVDU_rec, 518 DIVDUO_rec, 519 DIVWE_rec, 520 DIVWEO_rec, 521 DIVWEU_rec, 522 DIVWEUO_rec 523)>; 524 525// 27 Cycles Scalar Fixed-Point Divide operations, 2 input operands 526def : InstRW<[P10W_DV_27C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 527 (instrs 528 MODSD, 529 MODUD, 530 MODUW 531)>; 532 533// 41 Cycles Scalar Fixed-Point Divide operations, 2 input operands 534def : InstRW<[P10W_DV_41C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 535 (instrs 536 DIVDE, 537 DIVDEO, 538 DIVDEU, 539 DIVDEUO 540)>; 541 542// 2-way crack instructions 543// 41 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands 544def : InstRW<[P10W_DV_41C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 545 (instrs 546 DIVDE_rec, 547 DIVDEO_rec, 548 DIVDEU_rec, 549 DIVDEUO_rec 550)>; 551 552// 43 Cycles Scalar Fixed-Point Divide operations, 2 input operands 553def : InstRW<[P10W_DV_43C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 554 (instrs 555 VDIVSD, 556 VDIVUD 557)>; 558 559// 47 Cycles Scalar Fixed-Point Divide operations, 2 input operands 560def : InstRW<[P10W_DV_47C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 561 (instrs 562 VMODSD, 563 VMODUD 564)>; 565 566// 54 Cycles Scalar Fixed-Point Divide operations, 2 input operands 567def : InstRW<[P10W_DV_54C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 568 (instrs 569 VDIVSW, 570 VDIVUW 571)>; 572 573// 60 Cycles Scalar Fixed-Point Divide operations, 2 input operands 574def : InstRW<[P10W_DV_60C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 575 (instrs 576 VMODSW, 577 VMODUW 578)>; 579 580// 75 Cycles Scalar Fixed-Point Divide operations, 2 input operands 581def : InstRW<[P10W_DV_75C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 582 (instrs 583 VDIVESD, 584 VDIVEUD 585)>; 586 587// 83 Cycles Scalar Fixed-Point Divide operations, 2 input operands 588def : InstRW<[P10W_DV_83C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 589 (instrs 590 VDIVESW, 591 VDIVEUW 592)>; 593 594// 5 Cycles Fixed-Point and BCD operations, 1 input operands 595def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read], 596 (instrs 597 BCDCTN_rec, 598 VMUL10CUQ, 599 VMUL10UQ, 600 XSXSIGQP 601)>; 602 603// 5 Cycles Fixed-Point and BCD operations, 2 input operands 604def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read, P10DX_Read], 605 (instrs 606 BCDCFN_rec, 607 BCDCFZ_rec, 608 BCDCPSGN_rec, 609 BCDCTZ_rec, 610 BCDSETSGN_rec, 611 BCDUS_rec, 612 BCDUTRUNC_rec, 613 VADDCUQ, 614 VADDUQM, 615 VMUL10ECUQ, 616 VMUL10EUQ, 617 VSUBCUQ, 618 VSUBUQM, 619 XSCMPEXPQP, 620 XSCMPOQP, 621 XSCMPUQP, 622 XSMAXCQP, 623 XSMINCQP, 624 XSTSTDCQP, 625 XXGENPCVBM 626)>; 627 628// 5 Cycles Fixed-Point and BCD operations, 3 input operands 629def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read, P10DX_Read, P10DX_Read], 630 (instrs 631 BCDADD_rec, 632 BCDS_rec, 633 BCDSUB_rec, 634 BCDTRUNC_rec, 635 VADDECUQ, 636 VADDEUQM, 637 VSUBECUQ, 638 VSUBEUQM 639)>; 640 641// 4 Cycles ALU2 operations, 0 input operands 642def : InstRW<[P10W_F2_4C, P10W_DISP_ANY], 643 (instrs 644 TRAP, TW 645)>; 646 647// 4 Cycles ALU2 operations, 1 input operands 648def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read], 649 (instrs 650 CNTLZD, 651 CNTLZD_rec, 652 CNTLZW, CNTLZW8, 653 CNTLZW8_rec, CNTLZW_rec, 654 CNTTZD, 655 CNTTZD_rec, 656 CNTTZW, CNTTZW8, 657 CNTTZW8_rec, CNTTZW_rec, 658 FTSQRT, 659 MTVSRBM, 660 MTVSRBMI, 661 MTVSRDM, 662 MTVSRHM, 663 MTVSRQM, 664 MTVSRWM, 665 POPCNTB, POPCNTB8, 666 POPCNTD, 667 POPCNTW, 668 VCLZB, 669 VCLZD, 670 VCLZH, 671 VCLZW, 672 VCTZB, 673 VCTZD, 674 VCTZH, 675 VCTZW, 676 VEXPANDBM, 677 VEXPANDDM, 678 VEXPANDHM, 679 VEXPANDQM, 680 VEXPANDWM, 681 VEXTRACTBM, 682 VEXTRACTDM, 683 VEXTRACTHM, 684 VEXTRACTQM, 685 VEXTRACTWM, 686 VPOPCNTB, 687 VPOPCNTD, 688 VPOPCNTH, 689 VPOPCNTW, 690 VPRTYBD, 691 VPRTYBW, 692 XSCVHPDP, 693 XSCVSPDPN, 694 XSTSQRTDP, 695 XVCVHPSP, 696 XVTLSBB, 697 XVTSQRTDP, 698 XVTSQRTSP 699)>; 700 701// 4 Cycles ALU2 operations, 2 input operands 702def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read], 703 (instrs 704 CMPEQB, 705 EXTSWSLI_32_64_rec, EXTSWSLI_rec, 706 FCMPOD, FCMPOS, 707 FCMPUD, FCMPUS, 708 FTDIV, 709 SLD_rec, 710 SLW8_rec, SLW_rec, 711 SRD_rec, 712 SRW8_rec, SRW_rec, 713 VABSDUB, 714 VABSDUH, 715 VABSDUW, 716 VADDCUW, 717 VADDSBS, 718 VADDSHS, 719 VADDSWS, 720 VADDUBS, 721 VADDUHS, 722 VADDUWS, 723 VAVGSB, 724 VAVGSH, 725 VAVGSW, 726 VAVGUB, 727 VAVGUH, 728 VAVGUW, 729 VCMPBFP, 730 VCMPBFP_rec, 731 VCMPEQFP, 732 VCMPEQFP_rec, 733 VCMPEQUB_rec, 734 VCMPEQUD_rec, 735 VCMPEQUH_rec, 736 VCMPEQUQ, 737 VCMPEQUQ_rec, 738 VCMPEQUW_rec, 739 VCMPGEFP, 740 VCMPGEFP_rec, 741 VCMPGTFP, 742 VCMPGTFP_rec, 743 VCMPGTSB_rec, 744 VCMPGTSD_rec, 745 VCMPGTSH_rec, 746 VCMPGTSQ, 747 VCMPGTSQ_rec, 748 VCMPGTSW_rec, 749 VCMPGTUB_rec, 750 VCMPGTUD_rec, 751 VCMPGTUH_rec, 752 VCMPGTUQ, 753 VCMPGTUQ_rec, 754 VCMPGTUW_rec, 755 VCMPNEB_rec, 756 VCMPNEH_rec, 757 VCMPNEW_rec, 758 VCMPNEZB_rec, 759 VCMPNEZH_rec, 760 VCMPNEZW_rec, 761 VCMPSQ, 762 VCMPUQ, 763 VCNTMBB, 764 VCNTMBD, 765 VCNTMBH, 766 VCNTMBW, 767 VMAXFP, 768 VMINFP, 769 VSUBCUW, 770 VSUBSBS, 771 VSUBSHS, 772 VSUBSWS, 773 VSUBUBS, 774 VSUBUHS, 775 VSUBUWS, 776 XSCMPEQDP, 777 XSCMPEXPDP, 778 XSCMPGEDP, 779 XSCMPGTDP, 780 XSCMPODP, 781 XSCMPUDP, 782 XSMAXCDP, 783 XSMAXDP, 784 XSMAXJDP, 785 XSMINCDP, 786 XSMINDP, 787 XSMINJDP, 788 XSTDIVDP, 789 XSTSTDCDP, 790 XSTSTDCSP, 791 XVCMPEQDP, 792 XVCMPEQDP_rec, 793 XVCMPEQSP, 794 XVCMPEQSP_rec, 795 XVCMPGEDP, 796 XVCMPGEDP_rec, 797 XVCMPGESP, 798 XVCMPGESP_rec, 799 XVCMPGTDP, 800 XVCMPGTDP_rec, 801 XVCMPGTSP, 802 XVCMPGTSP_rec, 803 XVMAXDP, 804 XVMAXSP, 805 XVMINDP, 806 XVMINSP, 807 XVTDIVDP, 808 XVTDIVSP, 809 XVTSTDCDP, 810 XVTSTDCSP 811)>; 812 813// 4 Cycles ALU2 operations, 3 input operands 814def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read, P10F2_Read], 815 (instrs 816 CMPRB, CMPRB8, 817 RLDCL_rec, 818 RLDCR_rec, 819 RLDIC_rec, 820 RLDICL_32_rec, RLDICL_rec, 821 RLDICR_rec, 822 TD, 823 TDI, 824 TWI, 825 VSHASIGMAD, 826 VSHASIGMAW 827)>; 828 829// 4 Cycles ALU2 operations, 4 input operands 830def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read, P10F2_Read, P10F2_Read], 831 (instrs 832 RLDIMI_rec, 833 RLWINM8_rec, RLWINM_rec, 834 RLWNM8_rec, RLWNM_rec 835)>; 836 837// 4 Cycles ALU2 operations, 5 input operands 838def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read, P10F2_Read, P10F2_Read, P10F2_Read], 839 (instrs 840 RLWIMI8_rec, RLWIMI_rec 841)>; 842 843// Single crack instructions 844// 4 Cycles ALU2 operations, 2 input operands 845def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_DISP_ANY, P10F2_Read, P10F2_Read], 846 (instrs 847 SRAD_rec, 848 SRADI_rec, 849 SRAW_rec, 850 SRAWI_rec 851)>; 852 853// Single crack instructions 854// 4 Cycles ALU2 operations, 3 input operands 855def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_DISP_ANY, P10F2_Read, P10F2_Read, P10F2_Read], 856 (instrs 857 TABORTDC, 858 TABORTDCI, 859 TABORTWC, 860 TABORTWCI 861)>; 862 863// 2-way crack instructions 864// 4 Cycles ALU2 operations, and 4 Cycles Permute operations, 2 input operands 865def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_PM_4C, P10W_DISP_ANY], 866 (instrs 867 VRLQ, 868 VRLQNM, 869 VSLQ, 870 VSRAQ, 871 VSRQ 872)>; 873 874// 2-way crack instructions 875// 4 Cycles ALU2 operations, and 4 Cycles Permute operations, 3 input operands 876def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_PM_4C, P10W_DISP_ANY], 877 (instrs 878 VRLQMI 879)>; 880 881// 2-way crack instructions 882// 4 Cycles ALU2 operations, and 4 Cycles ALU2 operations, 0 input operands 883def : InstRW<[P10W_F2_4C, P10W_DISP_PAIR, P10W_F2_4C], 884 (instrs 885 MFCR, MFCR8 886)>; 887 888// 2 Cycles ALU operations, 1 input operands 889def : InstRW<[P10W_FX_2C, P10W_DISP_ANY, P10FX_Read], 890 (instrs 891 MTCTR, MTCTR8, MTCTR8loop, MTCTRloop, 892 MTLR, MTLR8 893)>; 894 895// 3 Cycles ALU operations, 0 input operands 896def : InstRW<[P10W_FX_3C, P10W_DISP_ANY], 897 (instrs 898 CR6SET, CREQV, CRSET, 899 DSS, DSSALL, 900 MCRXRX, 901 MFCTR, MFCTR8, 902 MFLR, MFLR8, 903 NOP, NOP_GT_PWR6, NOP_GT_PWR7, ORI, ORI8, 904 VXOR, V_SET0, V_SET0B, V_SET0H, 905 XXLEQV, XXLEQVOnes, 906 XXLXOR, XXLXORdpz, XXLXORspz, XXLXORz 907)>; 908 909// 3 Cycles ALU operations, 1 input operands 910def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read], 911 (instrs 912 ADDI, ADDI8, ADDIdtprelL32, ADDItlsldLADDR32, ADDItocL, LI, LI8, 913 ADDIS, ADDIS8, ADDISdtprelHA32, ADDIStocHA, ADDIStocHA8, LIS, LIS8, 914 ADDME, ADDME8, 915 ADDME8O, ADDMEO, 916 ADDZE, ADDZE8, 917 ADDZE8O, ADDZEO, 918 EXTSB, EXTSB8, EXTSB8_32_64, 919 EXTSB8_rec, EXTSB_rec, 920 EXTSH, EXTSH8, EXTSH8_32_64, 921 EXTSH8_rec, EXTSH_rec, 922 EXTSW, EXTSW_32, EXTSW_32_64, 923 EXTSW_32_64_rec, EXTSW_rec, 924 FABSD, FABSS, 925 FMR, 926 FNABSD, FNABSS, 927 FNEGD, FNEGS, 928 MCRF, 929 MFOCRF, MFOCRF8, 930 MFVRD, MFVSRD, 931 MFVRWZ, MFVSRWZ, 932 MTOCRF, MTOCRF8, 933 MTVRD, MTVSRD, 934 MTVRWA, MTVSRWA, 935 MTVRWZ, MTVSRWZ, 936 NEG, NEG8, 937 NEG8_rec, NEG_rec, 938 NEG8O, NEGO, 939 SETB, SETB8, 940 SETBC, SETBC8, 941 SETBCR, SETBCR8, 942 SETNBC, SETNBC8, 943 SETNBCR, SETNBCR8, 944 SUBFME, SUBFME8, 945 SUBFME8O, SUBFMEO, 946 SUBFZE, SUBFZE8, 947 SUBFZE8O, SUBFZEO, 948 VEXTSB2D, VEXTSB2Ds, 949 VEXTSB2W, VEXTSB2Ws, 950 VEXTSD2Q, 951 VEXTSH2D, VEXTSH2Ds, 952 VEXTSH2W, VEXTSH2Ws, 953 VEXTSW2D, VEXTSW2Ds, 954 VNEGD, 955 VNEGW, 956 WAIT, 957 XSABSDP, 958 XSABSQP, 959 XSNABSDP, XSNABSDPs, 960 XSNABSQP, 961 XSNEGDP, 962 XSNEGQP, 963 XSXEXPDP, 964 XSXEXPQP, 965 XSXSIGDP, 966 XVABSDP, 967 XVABSSP, 968 XVNABSDP, 969 XVNABSSP, 970 XVNEGDP, 971 XVNEGSP, 972 XVXEXPDP, 973 XVXEXPSP, 974 XVXSIGDP, 975 XVXSIGSP 976)>; 977 978// 3 Cycles ALU operations, 2 input operands 979def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 980 (instrs 981 ADD4, ADD4TLS, ADD8, ADD8TLS, ADD8TLS_, 982 ADD4_rec, ADD8_rec, 983 ADDE, ADDE8, 984 ADDE8O, ADDEO, 985 ADDIC, ADDIC8, 986 ADD4O, ADD8O, 987 AND, AND8, 988 AND8_rec, AND_rec, 989 ANDC, ANDC8, 990 ANDC8_rec, ANDC_rec, 991 ANDI8_rec, ANDI_rec, 992 ANDIS8_rec, ANDIS_rec, 993 CMPD, CMPW, 994 CMPB, CMPB8, 995 CMPDI, CMPWI, 996 CMPLD, CMPLW, 997 CMPLDI, CMPLWI, 998 CRAND, 999 CRANDC, 1000 CRNAND, 1001 CRNOR, 1002 CROR, 1003 CRORC, 1004 CR6UNSET, CRUNSET, CRXOR, 1005 EQV, EQV8, 1006 EQV8_rec, EQV_rec, 1007 EXTSWSLI, EXTSWSLI_32_64, 1008 FCPSGND, FCPSGNS, 1009 NAND, NAND8, 1010 NAND8_rec, NAND_rec, 1011 NOR, NOR8, 1012 NOR8_rec, NOR_rec, 1013 COPY, OR, OR8, 1014 OR8_rec, OR_rec, 1015 ORC, ORC8, 1016 ORC8_rec, ORC_rec, 1017 ORIS, ORIS8, 1018 SLD, 1019 SLW, SLW8, 1020 SRAD, 1021 SRADI, SRADI_32, 1022 SRAW, 1023 SRAWI, 1024 SRD, 1025 SRW, SRW8, 1026 SUBF, SUBF8, 1027 SUBF8_rec, SUBF_rec, 1028 SUBFE, SUBFE8, 1029 SUBFE8O, SUBFEO, 1030 SUBFIC, SUBFIC8, 1031 SUBF8O, SUBFO, 1032 VADDUBM, 1033 VADDUDM, 1034 VADDUHM, 1035 VADDUWM, 1036 VAND, 1037 VANDC, 1038 VCMPEQUB, 1039 VCMPEQUD, 1040 VCMPEQUH, 1041 VCMPEQUW, 1042 VCMPGTSB, 1043 VCMPGTSD, 1044 VCMPGTSH, 1045 VCMPGTSW, 1046 VCMPGTUB, 1047 VCMPGTUD, 1048 VCMPGTUH, 1049 VCMPGTUW, 1050 VCMPNEB, 1051 VCMPNEH, 1052 VCMPNEW, 1053 VCMPNEZB, 1054 VCMPNEZH, 1055 VCMPNEZW, 1056 VEQV, 1057 VMAXSB, 1058 VMAXSD, 1059 VMAXSH, 1060 VMAXSW, 1061 VMAXUB, 1062 VMAXUD, 1063 VMAXUH, 1064 VMAXUW, 1065 VMINSB, 1066 VMINSD, 1067 VMINSH, 1068 VMINSW, 1069 VMINUB, 1070 VMINUD, 1071 VMINUH, 1072 VMINUW, 1073 VMRGEW, 1074 VMRGOW, 1075 VNAND, 1076 VNOR, 1077 VOR, 1078 VORC, 1079 VRLB, 1080 VRLD, 1081 VRLDNM, 1082 VRLH, 1083 VRLW, 1084 VRLWNM, 1085 VSLB, 1086 VSLD, 1087 VSLH, 1088 VSLW, 1089 VSRAB, 1090 VSRAD, 1091 VSRAH, 1092 VSRAW, 1093 VSRB, 1094 VSRD, 1095 VSRH, 1096 VSRW, 1097 VSUBUBM, 1098 VSUBUDM, 1099 VSUBUHM, 1100 VSUBUWM, 1101 XOR, XOR8, 1102 XOR8_rec, XOR_rec, 1103 XORI, XORI8, 1104 XORIS, XORIS8, 1105 XSCPSGNDP, 1106 XSCPSGNQP, 1107 XSIEXPDP, 1108 XSIEXPQP, 1109 XVCPSGNDP, 1110 XVCPSGNSP, 1111 XVIEXPDP, 1112 XVIEXPSP, 1113 XXLAND, 1114 XXLANDC, 1115 XXLNAND, 1116 XXLNOR, 1117 XXLOR, XXLORf, 1118 XXLORC 1119)>; 1120 1121// 3 Cycles ALU operations, 3 input operands 1122def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read, P10FX_Read], 1123 (instrs 1124 ADDEX, ADDEX8, 1125 DST, DST64, DSTT, DSTT64, 1126 DSTST, DSTST64, DSTSTT, DSTSTT64, 1127 ISEL, ISEL8, 1128 RLDCL, 1129 RLDCR, 1130 RLDIC, 1131 RLDICL, RLDICL_32, RLDICL_32_64, 1132 RLDICR, RLDICR_32, 1133 VRLDMI, 1134 VRLWMI, 1135 VSEL, 1136 XXSEL 1137)>; 1138 1139// 3 Cycles ALU operations, 4 input operands 1140def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read, P10FX_Read, P10FX_Read], 1141 (instrs 1142 RLDIMI, 1143 RLWINM, RLWINM8, 1144 RLWNM, RLWNM8 1145)>; 1146 1147// 3 Cycles ALU operations, 5 input operands 1148def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read, P10FX_Read, P10FX_Read, P10FX_Read], 1149 (instrs 1150 RLWIMI, RLWIMI8 1151)>; 1152 1153// Single crack instructions 1154// 3 Cycles ALU operations, 0 input operands 1155def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_DISP_ANY], 1156 (instrs 1157 MFFS, 1158 MFFS_rec, 1159 MFFSL, 1160 MFVSCR, 1161 TRECHKPT 1162)>; 1163 1164// Single crack instructions 1165// 3 Cycles ALU operations, 1 input operands 1166def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10FX_Read], 1167 (instrs 1168 ADDME8_rec, ADDME_rec, 1169 ADDME8O_rec, ADDMEO_rec, 1170 ADDZE8_rec, ADDZE_rec, 1171 ADDZE8O_rec, ADDZEO_rec, 1172 MCRFS, 1173 MFFSCDRN, 1174 MFFSCDRNI, 1175 MFFSCRN, 1176 MFFSCRNI, 1177 MTFSB0, 1178 MTVSCR, 1179 NEG8O_rec, NEGO_rec, 1180 SUBFME8_rec, SUBFME_rec, 1181 SUBFME8O_rec, SUBFMEO_rec, 1182 SUBFZE8_rec, SUBFZE_rec, 1183 SUBFZE8O_rec, SUBFZEO_rec, 1184 TABORT, 1185 TBEGIN, 1186 TRECLAIM, 1187 TSR 1188)>; 1189 1190// Single crack instructions 1191// 3 Cycles ALU operations, 2 input operands 1192def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 1193 (instrs 1194 ADDE8_rec, ADDE_rec, 1195 ADDE8O_rec, ADDEO_rec, 1196 ADDIC_rec, 1197 ADD4O_rec, ADD8O_rec, 1198 SUBFE8_rec, SUBFE_rec, 1199 SUBFE8O_rec, SUBFEO_rec, 1200 SUBF8O_rec, SUBFO_rec 1201)>; 1202 1203// 2-way crack instructions 1204// 3 Cycles ALU operations, and 3 Cycles ALU operations, 0 input operands 1205def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1206 (instrs 1207 HRFID, 1208 MFFSCE, 1209 RFID, 1210 STOP 1211)>; 1212 1213// 2-way crack instructions 1214// 3 Cycles ALU operations, and 3 Cycles ALU operations, 1 input operands 1215def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read], 1216 (instrs 1217 FABSD_rec, FABSS_rec, 1218 FMR_rec, 1219 FNABSD_rec, FNABSS_rec, 1220 FNEGD_rec, FNEGS_rec, 1221 MTFSB1, 1222 RFEBB, 1223 SC 1224)>; 1225 1226// 2-way crack instructions 1227// 3 Cycles ALU operations, and 3 Cycles ALU operations, 2 input operands 1228def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 1229 (instrs 1230 ADDC, ADDC8, 1231 ADDC8_rec, ADDC_rec, 1232 ADDC8O, ADDCO, 1233 FCPSGND_rec, FCPSGNS_rec, 1234 MTFSF, MTFSFb, 1235 MTFSFI, MTFSFIb, 1236 SUBFC, SUBFC8, 1237 SUBFC8_rec, SUBFC_rec, 1238 SUBFC8O, SUBFCO 1239)>; 1240 1241// 2-way crack instructions 1242// 3 Cycles ALU operations, and 3 Cycles ALU operations, 3 input operands 1243def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read, P10FX_Read], 1244 (instrs 1245 MTFSFI_rec 1246)>; 1247 1248// 2-way crack instructions 1249// 3 Cycles ALU operations, and 3 Cycles ALU operations, 4 input operands 1250def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read, P10FX_Read, P10FX_Read], 1251 (instrs 1252 MTFSF_rec 1253)>; 1254 1255// 4-way crack instructions 1256// 3 Cycles ALU operations, 3 Cycles ALU operations, 3 Cycles ALU operations, and 3 Cycles ALU operations, 2 input operands 1257def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 1258 (instrs 1259 ADDC8O_rec, ADDCO_rec, 1260 SUBFC8O_rec, SUBFCO_rec 1261)>; 1262 1263// 2-way crack instructions 1264// 3 Cycles ALU operations, and 4 Cycles Permute operations, 1 input operands 1265def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_PM_4C, P10W_DISP_ANY], 1266 (instrs 1267 VSTRIBL_rec, 1268 VSTRIBR_rec, 1269 VSTRIHL_rec, 1270 VSTRIHR_rec 1271)>; 1272 1273// 2-way crack instructions 1274// 3 Cycles ALU operations, and 3 Cycles ALU operations, 2 input operands 1275def : InstRW<[P10W_FX_3C, P10W_DISP_PAIR, P10W_FX_3C, P10FX_Read, P10FX_Read], 1276 (instrs 1277 MTCRF, MTCRF8 1278)>; 1279 1280// 6 Cycles Load operations, 1 input operands 1281def : InstRW<[P10W_LD_6C, P10W_DISP_ANY, P10LD_Read], 1282 (instrs 1283 LBZ, LBZ8, 1284 LD, LDtoc, LDtocBA, LDtocCPT, LDtocJTI, LDtocL, SPILLTOVSR_LD, 1285 LDBRX, 1286 DFLOADf32, DFLOADf64, LFD, 1287 LFDX, XFLOADf32, XFLOADf64, 1288 LFIWAX, LIWAX, 1289 LFIWZX, LIWZX, 1290 LHA, LHA8, 1291 LHAX, LHAX8, 1292 LHBRX, LHBRX8, 1293 LHZ, LHZ8, 1294 LVEBX, 1295 LVEHX, 1296 LVEWX, 1297 LVX, 1298 LVXL, 1299 LWA, LWA_32, 1300 LWAX, LWAX_32, 1301 LWBRX, LWBRX8, 1302 LWZ, LWZ8, LWZtoc, LWZtocL, 1303 LXSD, 1304 LXSDX, 1305 LXSIBZX, 1306 LXSIHZX, 1307 LXSIWAX, 1308 LXSIWZX, 1309 LXV, 1310 LXVB16X, 1311 LXVD2X, 1312 LXVDSX, 1313 LXVH8X, 1314 LXVRBX, 1315 LXVRDX, 1316 LXVRHX, 1317 LXVRWX, 1318 LXVW4X, 1319 LXVWSX, 1320 LXVX 1321)>; 1322 1323// 6 Cycles Load operations, 2 input operands 1324def : InstRW<[P10W_LD_6C, P10W_DISP_ANY, P10LD_Read, P10LD_Read], 1325 (instrs 1326 DCBT, 1327 DCBTST, 1328 ICBT, 1329 LBZX, LBZX8, LBZXTLS, LBZXTLS_, LBZXTLS_32, 1330 LDX, LDXTLS, LDXTLS_, SPILLTOVSR_LDX, 1331 LHZX, LHZX8, LHZXTLS, LHZXTLS_, LHZXTLS_32, 1332 LWZX, LWZX8, LWZXTLS, LWZXTLS_, LWZXTLS_32, 1333 LXVL, 1334 LXVLL 1335)>; 1336 1337// 2-way crack instructions 1338// 6 Cycles Load operations, and 13 Cycles Decimal Floating Point operations, 2 input operands 1339def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DF_13C, P10W_DISP_ANY], 1340 (instrs 1341 HASHCHK, HASHCHK8, 1342 HASHCHKP, HASHCHKP8 1343)>; 1344 1345// Single crack instructions 1346// 6 Cycles Load operations, 0 input operands 1347def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DISP_ANY], 1348 (instrs 1349 SLBIA 1350)>; 1351 1352// Single crack instructions 1353// 6 Cycles Load operations, 1 input operands 1354def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DISP_ANY, P10LD_Read], 1355 (instrs 1356 DARN, 1357 LBARX, LBARXL, 1358 LDARX, LDARXL, 1359 LHARX, LHARXL, 1360 LWARX, LWARXL, 1361 SLBFEE_rec, 1362 SLBIE, 1363 SLBMFEE, 1364 SLBMFEV 1365)>; 1366 1367// Single crack instructions 1368// 6 Cycles Load operations, 2 input operands 1369def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DISP_ANY, P10LD_Read, P10LD_Read], 1370 (instrs 1371 LBZCIX, 1372 LDCIX, 1373 LHZCIX, 1374 LWZCIX, 1375 MTSPR, MTSPR8, MTSR, MTUDSCR, MTVRSAVE, MTVRSAVEv 1376)>; 1377 1378// Expand instructions 1379// 6 Cycles Load operations, 6 Cycles Load operations, 6 Cycles Load operations, and 6 Cycles Load operations, 1 input operands 1380def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10LD_Read], 1381 (instrs 1382 LMW 1383)>; 1384 1385// Expand instructions 1386// 6 Cycles Load operations, 6 Cycles Load operations, 6 Cycles Load operations, and 6 Cycles Load operations, 2 input operands 1387def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10LD_Read, P10LD_Read], 1388 (instrs 1389 LSWI 1390)>; 1391 1392// 2-way crack instructions 1393// 6 Cycles Load operations, and 3 Cycles Simple Fixed-point (SFX) operations, 1 input operands 1394def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_SX_3C, P10W_DISP_ANY], 1395 (instrs 1396 LBZU, LBZU8, 1397 LBZUX, LBZUX8, 1398 LDU, 1399 LDUX, 1400 LFDU, 1401 LFDUX, 1402 LHAU, LHAU8, 1403 LHAUX, LHAUX8, 1404 LHZU, LHZU8, 1405 LHZUX, LHZUX8, 1406 LWAUX, 1407 LWZU, LWZU8, 1408 LWZUX, LWZUX8 1409)>; 1410 1411// 6 Cycles Load operations, 1 input operands 1412def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10LD_Read], 1413 (instrs 1414 PLBZ, PLBZ8, PLBZ8pc, PLBZpc, 1415 PLD, PLDpc, 1416 PLFD, PLFDpc, 1417 PLFS, PLFSpc, 1418 PLHA, PLHA8, PLHA8pc, PLHApc, 1419 PLHZ, PLHZ8, PLHZ8pc, PLHZpc, 1420 PLWA, PLWA8, PLWA8pc, PLWApc, 1421 PLWZ, PLWZ8, PLWZ8pc, PLWZpc, 1422 PLXSD, PLXSDpc, 1423 PLXSSP, PLXSSPpc, 1424 PLXV, PLXVpc, 1425 PLXVP, PLXVPpc 1426)>; 1427 1428// 2-way crack instructions 1429// 6 Cycles Load operations, and 4 Cycles ALU2 operations, 1 input operands 1430def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C], 1431 (instrs 1432 LFS, 1433 LFSX, 1434 LXSSP, 1435 LXSSPX 1436)>; 1437 1438// 4-way crack instructions 1439// 6 Cycles Load operations, 4 Cycles ALU2 operations, 3 Cycles Simple Fixed-point (SFX) operations, and 3 Cycles ALU operations, 1 input operands 1440def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C, P10W_SX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY], 1441 (instrs 1442 LFSU, 1443 LFSUX 1444)>; 1445 1446// 2-way crack instructions 1447// 6 Cycles Load operations, and 6 Cycles Load operations, 1 input operands 1448def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_LD_6C, P10W_DISP_PAIR, P10LD_Read], 1449 (instrs 1450 TLBIEL 1451)>; 1452 1453// 2-way crack instructions 1454// 6 Cycles Load operations, and 6 Cycles Load operations, 2 input operands 1455def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_LD_6C, P10W_DISP_PAIR, P10LD_Read, P10LD_Read], 1456 (instrs 1457 SLBMTE 1458)>; 1459 1460// 2-way crack instructions 1461// 6 Cycles Load operations, and 3 Cycles Simple Fixed-point (SFX) operations, 1 input operands 1462def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_SX_3C], 1463 (instrs 1464 LXVP, 1465 LXVPX 1466)>; 1467 1468// Single crack instructions 1469// 13 Cycles Unknown operations, 1 input operands 1470def : InstRW<[P10W_MFL_13C, P10W_DISP_EVEN, P10W_DISP_ANY], 1471 (instrs 1472 MFSPR, MFSPR8, MFSR, MFTB8, MFUDSCR, MFVRSAVE, MFVRSAVEv 1473)>; 1474 1475// 10 Cycles SIMD Matrix Multiply Engine operations, 0 input operands 1476def : InstRW<[P10W_MM_10C, P10W_DISP_ANY], 1477 (instrs 1478 XXSETACCZ 1479)>; 1480 1481// 10 Cycles SIMD Matrix Multiply Engine operations, 2 input operands 1482def : InstRW<[P10W_MM_10C, P10W_DISP_ANY, P10MM_Read, P10MM_Read], 1483 (instrs 1484 XVBF16GER2, 1485 XVF16GER2, 1486 XVF32GER, 1487 XVF64GER, 1488 XVI16GER2, 1489 XVI16GER2S, 1490 XVI4GER8, 1491 XVI8GER4 1492)>; 1493 1494// 10 Cycles SIMD Matrix Multiply Engine operations, 3 input operands 1495def : InstRW<[P10W_MM_10C, P10W_DISP_ANY, P10MM_Read, P10MM_Read, P10MM_Read], 1496 (instrs 1497 XVBF16GER2NN, 1498 XVBF16GER2NP, 1499 XVBF16GER2PN, 1500 XVBF16GER2PP, 1501 XVF16GER2NN, 1502 XVF16GER2NP, 1503 XVF16GER2PN, 1504 XVF16GER2PP, 1505 XVF32GERNN, 1506 XVF32GERNP, 1507 XVF32GERPN, 1508 XVF32GERPP, 1509 XVF64GERNN, 1510 XVF64GERNP, 1511 XVF64GERPN, 1512 XVF64GERPP, 1513 XVI16GER2PP, 1514 XVI16GER2SPP, 1515 XVI4GER8PP, 1516 XVI8GER4PP, 1517 XVI8GER4SPP 1518)>; 1519 1520// 10 Cycles SIMD Matrix Multiply Engine operations, 4 input operands 1521def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10MM_Read, P10MM_Read, P10MM_Read, P10MM_Read], 1522 (instrs 1523 PMXVF32GER, 1524 PMXVF64GER 1525)>; 1526 1527// 10 Cycles SIMD Matrix Multiply Engine operations, 5 input operands 1528def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10MM_Read, P10MM_Read, P10MM_Read, P10MM_Read, P10MM_Read], 1529 (instrs 1530 PMXVBF16GER2, 1531 PMXVF16GER2, 1532 PMXVF32GERNN, 1533 PMXVF32GERNP, 1534 PMXVF32GERPN, 1535 PMXVF32GERPP, 1536 PMXVF64GERNN, 1537 PMXVF64GERNP, 1538 PMXVF64GERPN, 1539 PMXVF64GERPP, 1540 PMXVI16GER2, 1541 PMXVI16GER2S, 1542 PMXVI4GER8, 1543 PMXVI8GER4 1544)>; 1545 1546// 10 Cycles SIMD Matrix Multiply Engine operations, 6 input operands 1547def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10MM_Read, P10MM_Read, P10MM_Read, P10MM_Read, P10MM_Read, P10MM_Read], 1548 (instrs 1549 PMXVBF16GER2NN, 1550 PMXVBF16GER2NP, 1551 PMXVBF16GER2PN, 1552 PMXVBF16GER2PP, 1553 PMXVF16GER2NN, 1554 PMXVF16GER2NP, 1555 PMXVF16GER2PN, 1556 PMXVF16GER2PP, 1557 PMXVI16GER2PP, 1558 PMXVI16GER2SPP, 1559 PMXVI4GER8PP, 1560 PMXVI8GER4PP, 1561 PMXVI8GER4SPP 1562)>; 1563 1564// 2-way crack instructions 1565// 10 Cycles SIMD Matrix Multiply Engine operations, and 3 Cycles ALU operations, 1 input operands 1566def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10W_FX_3C], 1567 (instrs 1568 XXMTACC 1569)>; 1570 1571// 4-way crack instructions 1572// 10 Cycles SIMD Matrix Multiply Engine operations, 3 Cycles ALU operations, 10 Cycles SIMD Matrix Multiply Engine operations, and 3 Cycles ALU operations, 1 input operands 1573def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10W_FX_3C, P10W_MM_10C, P10W_DISP_PAIR, P10W_FX_3C], 1574 (instrs 1575 XXMFACC 1576)>; 1577 1578// 5 Cycles GPR Multiply operations, 2 input operands 1579def : InstRW<[P10W_MU_5C, P10W_DISP_ANY, P10MU_Read, P10MU_Read], 1580 (instrs 1581 MULHD, 1582 MULHDU, 1583 MULHW, 1584 MULHWU, 1585 MULLD, 1586 MULLDO, 1587 MULLI, MULLI8, 1588 MULLW, 1589 MULLWO, 1590 VMULHSD, 1591 VMULHUD, 1592 VMULLD 1593)>; 1594 1595// 5 Cycles GPR Multiply operations, 3 input operands 1596def : InstRW<[P10W_MU_5C, P10W_DISP_ANY, P10MU_Read, P10MU_Read, P10MU_Read], 1597 (instrs 1598 MADDHD, 1599 MADDHDU, 1600 MADDLD, MADDLD8 1601)>; 1602 1603// 2-way crack instructions 1604// 5 Cycles GPR Multiply operations, and 3 Cycles ALU operations, 2 input operands 1605def : InstRW<[P10W_MU_5C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1606 (instrs 1607 MULHD_rec, 1608 MULHDU_rec, 1609 MULHW_rec, 1610 MULHWU_rec, 1611 MULLD_rec, 1612 MULLDO_rec, 1613 MULLW_rec, 1614 MULLWO_rec 1615)>; 1616 1617// 4 Cycles Permute operations, 0 input operands 1618def : InstRW<[P10W_PM_4C, P10W_DISP_ANY], 1619 (instrs 1620 VSPLTISW, V_SETALLONES, V_SETALLONESB, V_SETALLONESH 1621)>; 1622 1623// 4 Cycles Permute operations, 1 input operands 1624def : InstRW<[P10W_PM_4C, P10W_DISP_ANY, P10PM_Read], 1625 (instrs 1626 LVSL, 1627 LVSR, 1628 LXVKQ, 1629 MFVSRLD, 1630 MTVSRWS, 1631 VCLZLSBB, 1632 VCTZLSBB, 1633 VGBBD, 1634 VPRTYBQ, 1635 VSPLTISB, 1636 VSPLTISH, 1637 VSTRIBL, 1638 VSTRIBR, 1639 VSTRIHL, 1640 VSTRIHR, 1641 VUPKHPX, 1642 VUPKHSB, 1643 VUPKHSH, 1644 VUPKHSW, 1645 VUPKLPX, 1646 VUPKLSB, 1647 VUPKLSH, 1648 VUPKLSW, 1649 XVCVBF16SPN, 1650 XXBRD, 1651 XXBRH, 1652 XXBRQ, 1653 XXBRW, 1654 XXSPLTIB 1655)>; 1656 1657// 4 Cycles Permute operations, 2 input operands 1658def : InstRW<[P10W_PM_4C, P10W_DISP_ANY, P10PM_Read, P10PM_Read], 1659 (instrs 1660 BPERMD, 1661 MTVSRDD, 1662 VBPERMD, 1663 VBPERMQ, 1664 VCLRLB, 1665 VCLRRB, 1666 VEXTRACTD, 1667 VEXTRACTUB, 1668 VEXTRACTUH, 1669 VEXTRACTUW, 1670 VEXTUBLX, 1671 VEXTUBRX, 1672 VEXTUHLX, 1673 VEXTUHRX, 1674 VEXTUWLX, 1675 VEXTUWRX, 1676 VINSERTD, 1677 VINSERTW, 1678 VMRGHB, 1679 VMRGHH, 1680 VMRGHW, 1681 VMRGLB, 1682 VMRGLH, 1683 VMRGLW, 1684 VPKPX, 1685 VPKSDSS, 1686 VPKSDUS, 1687 VPKSHSS, 1688 VPKSHUS, 1689 VPKSWSS, 1690 VPKSWUS, 1691 VPKUDUM, 1692 VPKUDUS, 1693 VPKUHUM, 1694 VPKUHUS, 1695 VPKUWUM, 1696 VPKUWUS, 1697 VSL, 1698 VSLO, 1699 VSLV, 1700 VSPLTB, VSPLTBs, 1701 VSPLTH, VSPLTHs, 1702 VSPLTW, 1703 VSR, 1704 VSRO, 1705 VSRV, 1706 XXEXTRACTUW, 1707 XXGENPCVDM, 1708 XXGENPCVHM, 1709 XXGENPCVWM, 1710 XXMRGHW, 1711 XXMRGLW, 1712 XXPERM, 1713 XXPERMDI, XXPERMDIs, 1714 XXPERMR, 1715 XXSLDWI, XXSLDWIs, 1716 XXSPLTW, XXSPLTWs 1717)>; 1718 1719// 4 Cycles Permute operations, 3 input operands 1720def : InstRW<[P10W_PM_4C, P10W_DISP_ANY, P10PM_Read, P10PM_Read, P10PM_Read], 1721 (instrs 1722 VEXTDDVLX, 1723 VEXTDDVRX, 1724 VEXTDUBVLX, 1725 VEXTDUBVRX, 1726 VEXTDUHVLX, 1727 VEXTDUHVRX, 1728 VEXTDUWVLX, 1729 VEXTDUWVRX, 1730 VINSBLX, 1731 VINSBRX, 1732 VINSBVLX, 1733 VINSBVRX, 1734 VINSD, 1735 VINSDLX, 1736 VINSDRX, 1737 VINSERTB, 1738 VINSERTH, 1739 VINSHLX, 1740 VINSHRX, 1741 VINSHVLX, 1742 VINSHVRX, 1743 VINSW, 1744 VINSWLX, 1745 VINSWRX, 1746 VINSWVLX, 1747 VINSWVRX, 1748 VPERM, 1749 VPERMR, 1750 VPERMXOR, 1751 VSLDBI, 1752 VSLDOI, 1753 VSRDBI, 1754 XXINSERTW 1755)>; 1756 1757// 2-way crack instructions 1758// 4 Cycles Permute operations, and 7 Cycles VMX Multiply operations, 2 input operands 1759def : InstRW<[P10W_PM_4C, P10W_DISP_EVEN, P10W_vMU_7C, P10W_DISP_ANY], 1760 (instrs 1761 VSUMSWS 1762)>; 1763 1764// 4 Cycles Permute operations, 1 input operands 1765def : InstRW<[P10W_PM_4C, P10W_DISP_PAIR, P10PM_Read], 1766 (instrs 1767 XXSPLTIDP, 1768 XXSPLTIW 1769)>; 1770 1771// 4 Cycles Permute operations, 3 input operands 1772def : InstRW<[P10W_PM_4C, P10W_DISP_PAIR, P10PM_Read, P10PM_Read, P10PM_Read], 1773 (instrs 1774 XXBLENDVB, 1775 XXBLENDVD, 1776 XXBLENDVH, 1777 XXBLENDVW, 1778 XXSPLTI32DX 1779)>; 1780 1781// 4 Cycles Permute operations, 4 input operands 1782def : InstRW<[P10W_PM_4C, P10W_DISP_PAIR, P10PM_Read, P10PM_Read, P10PM_Read, P10PM_Read], 1783 (instrs 1784 XXEVAL, 1785 XXPERMX 1786)>; 1787 1788// 3 Cycles Store operations, 1 input operands 1789def : InstRW<[P10W_ST_3C, P10W_DISP_ANY, P10ST_Read], 1790 (instrs 1791 DCBST, 1792 DCBZ, 1793 ICBI 1794)>; 1795 1796// 3 Cycles Store operations, 2 input operands 1797def : InstRW<[P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read], 1798 (instrs 1799 DCBF, 1800 PSTXVP, PSTXVPpc, 1801 STB, STB8, 1802 STBU, STBU8, 1803 STBUX, STBUX8, 1804 SPILLTOVSR_ST, STD, 1805 STDBRX, 1806 STDU, 1807 STDUX, 1808 DFSTOREf32, DFSTOREf64, STFD, 1809 STFDU, 1810 STFDUX, 1811 STFDX, 1812 STFIWX, STIWX, 1813 STFS, 1814 STFSU, 1815 STFSUX, 1816 STFSX, 1817 STH, STH8, 1818 STHBRX, 1819 STHU, STHU8, 1820 STHUX, STHUX8, 1821 STVEBX, 1822 STVEHX, 1823 STVEWX, 1824 STVX, 1825 STVXL, 1826 STW, STW8, 1827 STWBRX, 1828 STWU, STWU8, 1829 STWUX, STWUX8, 1830 STXSD, 1831 STXSDX, 1832 STXSIBX, STXSIBXv, 1833 STXSIHX, STXSIHXv, 1834 STXSIWX, 1835 STXSSP, 1836 STXSSPX, 1837 STXV, 1838 STXVB16X, 1839 STXVD2X, 1840 STXVH8X, 1841 STXVRBX, 1842 STXVRDX, 1843 STXVRHX, 1844 STXVRWX, 1845 STXVW4X, 1846 STXVX 1847)>; 1848 1849// 3 Cycles Store operations, 3 input operands 1850def : InstRW<[P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read, P10ST_Read], 1851 (instrs 1852 CP_COPY, CP_COPY8, 1853 STBX, STBX8, STBXTLS, STBXTLS_, STBXTLS_32, 1854 SPILLTOVSR_STX, STDX, STDXTLS, STDXTLS_, 1855 STHX, STHX8, STHXTLS, STHXTLS_, STHXTLS_32, 1856 STWX, STWX8, STWXTLS, STWXTLS_, STWXTLS_32, 1857 STXVL, 1858 STXVLL 1859)>; 1860 1861// Single crack instructions 1862// 3 Cycles Store operations, 0 input operands 1863def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY], 1864 (instrs 1865 EnforceIEIO, 1866 MSGSYNC, 1867 SLBSYNC, 1868 TCHECK, 1869 TLBSYNC 1870)>; 1871 1872// Single crack instructions 1873// 3 Cycles Store operations, 1 input operands 1874def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read], 1875 (instrs 1876 TEND 1877)>; 1878 1879// Single crack instructions 1880// 3 Cycles Store operations, 2 input operands 1881def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read, P10ST_Read], 1882 (instrs 1883 SLBIEG, 1884 STBCX, 1885 STDCX, 1886 STHCX, 1887 STWCX, 1888 TLBIE 1889)>; 1890 1891// Single crack instructions 1892// 3 Cycles Store operations, 3 input operands 1893def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read, P10ST_Read, P10ST_Read], 1894 (instrs 1895 CP_PASTE8_rec, CP_PASTE_rec, 1896 STBCIX, 1897 STDCIX, 1898 STHCIX, 1899 STWCIX 1900)>; 1901 1902// 2-way crack instructions 1903// 3 Cycles Store operations, and 3 Cycles ALU operations, 0 input operands 1904def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1905 (instrs 1906 ISYNC 1907)>; 1908 1909// 2-way crack instructions 1910// 3 Cycles Store operations, and 3 Cycles ALU operations, 1 input operands 1911def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1912 (instrs 1913 SYNC 1914)>; 1915 1916// Expand instructions 1917// 3 Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, 3 Cycles ALU operations, 6 Cycles Load operations, and 3 Cycles Store operations, 2 input operands 1918def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY], 1919 (instrs 1920 LDAT, 1921 LWAT 1922)>; 1923 1924// 4-way crack instructions 1925// 3 Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, and 3 Cycles Store operations, 3 input operands 1926def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY], 1927 (instrs 1928 STDAT, 1929 STWAT 1930)>; 1931 1932// Expand instructions 1933// 3 Cycles Store operations, 3 Cycles Store operations, 3 Cycles Store operations, and 3 Cycles Store operations, 2 input operands 1934def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read], 1935 (instrs 1936 STMW 1937)>; 1938 1939// Expand instructions 1940// 3 Cycles Store operations, 3 Cycles Store operations, 3 Cycles Store operations, and 3 Cycles Store operations, 3 input operands 1941def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read, P10ST_Read], 1942 (instrs 1943 STSWI 1944)>; 1945 1946// 3 Cycles Store operations, 2 input operands 1947def : InstRW<[P10W_ST_3C, P10W_DISP_PAIR, P10ST_Read, P10ST_Read], 1948 (instrs 1949 PSTB, PSTB8, PSTB8pc, PSTBpc, 1950 PSTD, PSTDpc, 1951 PSTFD, PSTFDpc, 1952 PSTFS, PSTFSpc, 1953 PSTH, PSTH8, PSTH8pc, PSTHpc, 1954 PSTW, PSTW8, PSTW8pc, PSTWpc, 1955 PSTXSD, PSTXSDpc, 1956 PSTXSSP, PSTXSSPpc, 1957 PSTXV, PSTXVpc 1958)>; 1959 1960// 2-way crack instructions 1961// 3 Cycles Store operations, and 3 Cycles Store operations, 2 input operands 1962def : InstRW<[P10W_ST_3C, P10W_DISP_PAIR, P10W_ST_3C, P10ST_Read, P10ST_Read], 1963 (instrs 1964 STXVP, 1965 STXVPX 1966)>; 1967 1968// FIXME - Miss scheduling information from datasheet 1969// Temporary set it as 1 Cycles Simple Fixed-point (SFX) operations, 0 input operands 1970def : InstRW<[P10W_SX, P10W_DISP_ANY], 1971 (instrs 1972 ATTN, 1973 CP_ABORT, 1974 DCBA, 1975 DCBI, 1976 DCBZL, 1977 DCCCI, 1978 ICBLC, 1979 ICBLQ, 1980 ICBTLS, 1981 ICCCI, 1982 LA, LA8, 1983 MFDCR, 1984 MFPMR, 1985 MFSRIN, 1986 MSYNC, 1987 MTDCR, 1988 MTPMR, 1989 MTSRIN, 1990 NAP, 1991 TLBIA, 1992 TLBLD, 1993 TLBLI, 1994 TLBRE2, 1995 TLBSX2, 1996 TLBSX2D, 1997 TLBWE2 1998)>; 1999 2000// Single crack instructions 2001// 3 Cycles Simple Fixed-point (SFX) operations, 0 input operands 2002def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_DISP_ANY], 2003 (instrs 2004 CLRBHRB, 2005 MFMSR 2006)>; 2007 2008// Single crack instructions 2009// 3 Cycles Simple Fixed-point (SFX) operations, 1 input operands 2010def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10SX_Read], 2011 (instrs 2012 MFTB 2013)>; 2014 2015// Single crack instructions 2016// 3 Cycles Simple Fixed-point (SFX) operations, 2 input operands 2017def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10SX_Read, P10SX_Read], 2018 (instrs 2019 MFBHRBE, 2020 MTMSR, 2021 MTMSRD 2022)>; 2023 2024// 2-way crack instructions 2025// 3 Cycles Simple Fixed-point (SFX) operations, and 3 Cycles ALU operations, 1 input operands 2026def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 2027 (instrs 2028 ADDPCIS 2029)>; 2030 2031// 3 Cycles Simple Fixed-point (SFX) operations, 1 input operands 2032def : InstRW<[P10W_SX_3C, P10W_DISP_PAIR, P10SX_Read], 2033 (instrs 2034 PADDI, PADDI8, PADDI8pc, PADDIpc, PLI, PLI8 2035)>; 2036 2037// 7 Cycles VMX Multiply operations, 2 input operands 2038def : InstRW<[P10W_vMU_7C, P10W_DISP_ANY, P10vMU_Read, P10vMU_Read], 2039 (instrs 2040 VMULESB, 2041 VMULESD, 2042 VMULESH, 2043 VMULESW, 2044 VMULEUB, 2045 VMULEUD, 2046 VMULEUH, 2047 VMULEUW, 2048 VMULHSW, 2049 VMULHUW, 2050 VMULOSB, 2051 VMULOSD, 2052 VMULOSH, 2053 VMULOSW, 2054 VMULOUB, 2055 VMULOUD, 2056 VMULOUH, 2057 VMULOUW, 2058 VMULUWM, 2059 VSUM2SWS, 2060 VSUM4SBS, 2061 VSUM4SHS, 2062 VSUM4UBS 2063)>; 2064 2065// 7 Cycles VMX Multiply operations, 3 input operands 2066def : InstRW<[P10W_vMU_7C, P10W_DISP_ANY, P10vMU_Read, P10vMU_Read, P10vMU_Read], 2067 (instrs 2068 VMHADDSHS, 2069 VMHRADDSHS, 2070 VMLADDUHM, 2071 VMSUMCUD, 2072 VMSUMMBM, 2073 VMSUMSHM, 2074 VMSUMSHS, 2075 VMSUMUBM, 2076 VMSUMUDM, 2077 VMSUMUHM, 2078 VMSUMUHS 2079)>; 2080 2081