1//===--- P10InstrResources.td - P10 Scheduling Definitions -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// Automatically generated file, do not edit! 9// 10// This file defines instruction data for SchedModel of the POWER10 processor. 11// 12//===----------------------------------------------------------------------===// 13// 22 Cycles Binary Floating Point operations, 2 input operands 14def : InstRW<[P10W_BF_22C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 15 (instrs 16 FDIVS, 17 XSDIVSP 18)>; 19 20// 2-way crack instructions 21// 22 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands 22def : InstRW<[P10W_BF_22C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 23 (instrs 24 FDIVS_rec 25)>; 26 27// 24 Cycles Binary Floating Point operations, 2 input operands 28def : InstRW<[P10W_BF_24C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 29 (instrs 30 XVDIVSP 31)>; 32 33// 26 Cycles Binary Floating Point operations, 1 input operands 34def : InstRW<[P10W_BF_26C, P10W_DISP_ANY, P10BF_Read], 35 (instrs 36 FSQRTS, 37 XSSQRTSP 38)>; 39 40// 2-way crack instructions 41// 26 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands 42def : InstRW<[P10W_BF_26C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 43 (instrs 44 FSQRTS_rec 45)>; 46 47// 27 Cycles Binary Floating Point operations, 1 input operands 48def : InstRW<[P10W_BF_27C, P10W_DISP_ANY, P10BF_Read], 49 (instrs 50 XVSQRTSP 51)>; 52 53// 27 Cycles Binary Floating Point operations, 2 input operands 54def : InstRW<[P10W_BF_27C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 55 (instrs 56 FDIV, 57 XSDIVDP, 58 XVDIVDP 59)>; 60 61// 2-way crack instructions 62// 27 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands 63def : InstRW<[P10W_BF_27C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 64 (instrs 65 FDIV_rec 66)>; 67 68// 36 Cycles Binary Floating Point operations, 1 input operands 69def : InstRW<[P10W_BF_36C, P10W_DISP_ANY, P10BF_Read], 70 (instrs 71 FSQRT, 72 XSSQRTDP, 73 XVSQRTDP 74)>; 75 76// 2-way crack instructions 77// 36 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands 78def : InstRW<[P10W_BF_36C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 79 (instrs 80 FSQRT_rec 81)>; 82 83// 7 Cycles Binary Floating Point operations, 1 input operands 84def : InstRW<[P10W_BF_7C, P10W_DISP_ANY, P10BF_Read], 85 (instrs 86 FCFID, 87 FCFIDS, 88 FCFIDU, 89 FCFIDUS, 90 FCTID, 91 FCTIDU, 92 FCTIDUZ, 93 FCTIDZ, 94 FCTIW, 95 FCTIWU, 96 FCTIWUZ, 97 FCTIWZ, 98 FRE, 99 FRES, 100 FRIMD, FRIMS, 101 FRIND, FRINS, 102 FRIPD, FRIPS, 103 FRIZD, FRIZS, 104 FRSP, 105 FRSQRTE, 106 FRSQRTES, 107 VCFSX, VCFSX_0, 108 VCFUX, VCFUX_0, 109 VCTSXS, VCTSXS_0, 110 VCTUXS, VCTUXS_0, 111 VLOGEFP, 112 VREFP, 113 VRFIM, 114 VRFIN, 115 VRFIP, 116 VRFIZ, 117 VRSQRTEFP, 118 XSCVDPHP, 119 XSCVDPSP, 120 XSCVDPSPN, 121 XSCVDPSXDS, XSCVDPSXDSs, 122 XSCVDPSXWS, XSCVDPSXWSs, 123 XSCVDPUXDS, XSCVDPUXDSs, 124 XSCVDPUXWS, XSCVDPUXWSs, 125 XSCVSPDP, 126 XSCVSXDDP, 127 XSCVSXDSP, 128 XSCVUXDDP, 129 XSCVUXDSP, 130 XSRDPI, 131 XSRDPIC, 132 XSRDPIM, 133 XSRDPIP, 134 XSRDPIZ, 135 XSREDP, 136 XSRESP, 137 XSRSP, 138 XSRSQRTEDP, 139 XSRSQRTESP, 140 XVCVDPSP, 141 XVCVDPSXDS, 142 XVCVDPSXWS, 143 XVCVDPUXDS, 144 XVCVDPUXWS, 145 XVCVSPBF16, 146 XVCVSPDP, 147 XVCVSPHP, 148 XVCVSPSXDS, 149 XVCVSPSXWS, 150 XVCVSPUXDS, 151 XVCVSPUXWS, 152 XVCVSXDDP, 153 XVCVSXDSP, 154 XVCVSXWDP, 155 XVCVSXWSP, 156 XVCVUXDDP, 157 XVCVUXDSP, 158 XVCVUXWDP, 159 XVCVUXWSP, 160 XVRDPI, 161 XVRDPIC, 162 XVRDPIM, 163 XVRDPIP, 164 XVRDPIZ, 165 XVREDP, 166 XVRESP, 167 XVRSPI, 168 XVRSPIC, 169 XVRSPIM, 170 XVRSPIP, 171 XVRSPIZ, 172 XVRSQRTEDP, 173 XVRSQRTESP 174)>; 175 176// 7 Cycles Binary Floating Point operations, 2 input operands 177def : InstRW<[P10W_BF_7C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 178 (instrs 179 FADD, 180 FADDS, 181 FMUL, 182 FMULS, 183 FSUB, 184 FSUBS, 185 VADDFP, 186 VSUBFP, 187 XSADDDP, 188 XSADDSP, 189 XSMULDP, 190 XSMULSP, 191 XSSUBDP, 192 XSSUBSP, 193 XVADDDP, 194 XVADDSP, 195 XVMULDP, 196 XVMULSP, 197 XVSUBDP, 198 XVSUBSP 199)>; 200 201// 7 Cycles Binary Floating Point operations, 3 input operands 202def : InstRW<[P10W_BF_7C, P10W_DISP_ANY, P10BF_Read, P10BF_Read, P10BF_Read], 203 (instrs 204 FMADD, 205 FMADDS, 206 FMSUB, 207 FMSUBS, 208 FNMADD, 209 FNMADDS, 210 FNMSUB, 211 FNMSUBS, 212 FSELD, FSELS, 213 VMADDFP, 214 VNMSUBFP, 215 XSMADDADP, 216 XSMADDASP, 217 XSMADDMDP, 218 XSMADDMSP, 219 XSMSUBADP, 220 XSMSUBASP, 221 XSMSUBMDP, 222 XSMSUBMSP, 223 XSNMADDADP, 224 XSNMADDASP, 225 XSNMADDMDP, 226 XSNMADDMSP, 227 XSNMSUBADP, 228 XSNMSUBASP, 229 XSNMSUBMDP, 230 XSNMSUBMSP, 231 XVMADDADP, 232 XVMADDASP, 233 XVMADDMDP, 234 XVMADDMSP, 235 XVMSUBADP, 236 XVMSUBASP, 237 XVMSUBMDP, 238 XVMSUBMSP, 239 XVNMADDADP, 240 XVNMADDASP, 241 XVNMADDMDP, 242 XVNMADDMSP, 243 XVNMSUBADP, 244 XVNMSUBASP, 245 XVNMSUBMDP, 246 XVNMSUBMSP 247)>; 248 249// 2-way crack instructions 250// 7 Cycles Binary Floating Point operations, and 7 Cycles Binary Floating Point operations, 1 input operands 251def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_BF_7C, P10W_DISP_ANY, P10BF_Read], 252 (instrs 253 VEXPTEFP 254)>; 255 256// 2-way crack instructions 257// 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands 258def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 259 (instrs 260 FADD_rec, 261 FADDS_rec, 262 FMUL_rec, 263 FMULS_rec, 264 FSUB_rec, 265 FSUBS_rec 266)>; 267 268// 2-way crack instructions 269// 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands 270def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 271 (instrs 272 FCFID_rec, 273 FCFIDS_rec, 274 FCFIDU_rec, 275 FCFIDUS_rec, 276 FCTID_rec, 277 FCTIDU_rec, 278 FCTIDUZ_rec, 279 FCTIDZ_rec, 280 FCTIW_rec, 281 FCTIWU_rec, 282 FCTIWUZ_rec, 283 FCTIWZ_rec, 284 FRE_rec, 285 FRES_rec, 286 FRIMD_rec, FRIMS_rec, 287 FRIND_rec, FRINS_rec, 288 FRIPD_rec, FRIPS_rec, 289 FRIZD_rec, FRIZS_rec, 290 FRSP_rec, 291 FRSQRTE_rec, 292 FRSQRTES_rec 293)>; 294 295// 2-way crack instructions 296// 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 3 input operands 297def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 298 (instrs 299 FMADD_rec, 300 FMADDS_rec, 301 FMSUB_rec, 302 FMSUBS_rec, 303 FNMADD_rec, 304 FNMADDS_rec, 305 FNMSUB_rec, 306 FNMSUBS_rec, 307 FSELD_rec, FSELS_rec 308)>; 309 310// 2 Cycles Branch operations, 1 input operands 311def : InstRW<[P10W_BR_2C, P10W_DISP_ANY, P10BR_Read], 312 (instrs 313 B, BCC, BCCA, BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL, BCCLA, BCCLR, BCCLRL, CTRL_DEP, TAILB, TAILB8, 314 BA, TAILBA, TAILBA8, 315 BCCTR, BCCTR8, BCCTR8n, BCCTRn, gBCCTR, 316 BCCTRL, BCCTRL8, BCCTRL8n, BCCTRLn, gBCCTRL, 317 BCLR, BCLRn, BDNZLR, BDNZLR8, BDNZLRm, BDNZLRp, BDZLR, BDZLR8, BDZLRm, BDZLRp, gBCLR, 318 BCLRL, BCLRLn, BDNZLRL, BDNZLRLm, BDNZLRLp, BDZLRL, BDZLRLm, BDZLRLp, gBCLRL, 319 BL, BL8, BL8_NOP, BL8_NOP_RM, BL8_NOP_TLS, BL8_NOTOC, BL8_NOTOC_RM, BL8_NOTOC_TLS, BL8_RM, BL8_TLS, BL8_TLS_, BLR, BLR8, BLRL, BL_NOP, BL_NOP_RM, BL_RM, BL_TLS, 320 BLA, BLA8, BLA8_NOP, BLA8_NOP_RM, BLA8_RM, BLA_RM 321)>; 322 323// 2 Cycles Branch operations, 2 input operands 324def : InstRW<[P10W_BR_2C, P10W_DISP_ANY, P10BR_Read, P10BR_Read], 325 (instrs 326 BC, BCTR, BCTR8, BCTRL, BCTRL8, BCTRL8_LDinto_toc, BCTRL8_LDinto_toc_RM, BCTRL8_RM, BCTRL_LWZinto_toc, BCTRL_LWZinto_toc_RM, BCTRL_RM, BCn, BDNZ, BDNZ8, BDNZm, BDNZp, BDZ, BDZ8, BDZm, BDZp, TAILBCTR, TAILBCTR8, gBC, gBCat, 327 BDNZA, BDNZAm, BDNZAp, BDZA, BDZAm, BDZAp, gBCA, gBCAat, 328 BCL, BCLalways, BCLn, BDNZL, BDNZLm, BDNZLp, BDZL, BDZLm, BDZLp, gBCL, gBCLat, 329 BDNZLA, BDNZLAm, BDNZLAp, BDZLA, BDZLAm, BDZLAp, gBCLA, gBCLAat 330)>; 331 332// 7 Cycles Crypto operations, 1 input operands 333def : InstRW<[P10W_CY_7C, P10W_DISP_ANY, P10CY_Read], 334 (instrs 335 VGNB, 336 VSBOX 337)>; 338 339// 7 Cycles Crypto operations, 2 input operands 340def : InstRW<[P10W_CY_7C, P10W_DISP_ANY, P10CY_Read, P10CY_Read], 341 (instrs 342 CFUGED, 343 CNTLZDM, 344 CNTTZDM, 345 PDEPD, 346 PEXTD, 347 VCFUGED, 348 VCIPHER, 349 VCIPHERLAST, 350 VCLZDM, 351 VCTZDM, 352 VNCIPHER, 353 VNCIPHERLAST, 354 VPDEPD, 355 VPEXTD, 356 VPMSUMB, 357 VPMSUMD, 358 VPMSUMH, 359 VPMSUMW 360)>; 361 362// 13 Cycles Decimal Floating Point operations, 1 input operands 363def : InstRW<[P10W_DF_13C, P10W_DISP_ANY, P10DF_Read], 364 (instrs 365 XSCVDPQP, 366 XSCVQPDP, 367 XSCVQPDPO, 368 XSCVQPSDZ, 369 XSCVQPSQZ, 370 XSCVQPSWZ, 371 XSCVQPUDZ, 372 XSCVQPUQZ, 373 XSCVQPUWZ, 374 XSCVSDQP, 375 XSCVSQQP, 376 XSCVUDQP, 377 XSCVUQQP, 378 XSRQPI, 379 XSRQPIX, 380 XSRQPXP 381)>; 382 383// 13 Cycles Decimal Floating Point operations, 2 input operands 384def : InstRW<[P10W_DF_13C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 385 (instrs 386 BCDSR_rec, 387 XSADDQP, 388 XSADDQPO, 389 XSSUBQP, 390 XSSUBQPO 391)>; 392 393// 2-way crack instructions 394// 13 Cycles Decimal Floating Point operations, and 3 Cycles Store operations, 1 input operands 395def : InstRW<[P10W_DF_13C, P10W_DISP_EVEN, P10W_ST_3C, P10W_DISP_ANY], 396 (instrs 397 HASHST, HASHST8, 398 HASHSTP, HASHSTP8 399)>; 400 401// 24 Cycles Decimal Floating Point operations, 1 input operands 402def : InstRW<[P10W_DF_24C, P10W_DISP_ANY, P10DF_Read], 403 (instrs 404 BCDCTSQ_rec 405)>; 406 407// 25 Cycles Decimal Floating Point operations, 2 input operands 408def : InstRW<[P10W_DF_25C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 409 (instrs 410 XSMULQP, 411 XSMULQPO 412)>; 413 414// 25 Cycles Decimal Floating Point operations, 3 input operands 415def : InstRW<[P10W_DF_25C, P10W_DISP_ANY, P10DF_Read, P10DF_Read, P10DF_Read], 416 (instrs 417 XSMADDQP, 418 XSMADDQPO, 419 XSMSUBQP, 420 XSMSUBQPO, 421 XSNMADDQP, 422 XSNMADDQPO, 423 XSNMSUBQP, 424 XSNMSUBQPO 425)>; 426 427// 38 Cycles Decimal Floating Point operations, 1 input operands 428def : InstRW<[P10W_DF_38C, P10W_DISP_ANY, P10DF_Read], 429 (instrs 430 BCDCFSQ_rec 431)>; 432 433// 59 Cycles Decimal Floating Point operations, 2 input operands 434def : InstRW<[P10W_DF_59C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 435 (instrs 436 XSDIVQP, 437 XSDIVQPO 438)>; 439 440// 61 Cycles Decimal Floating Point operations, 2 input operands 441def : InstRW<[P10W_DF_61C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 442 (instrs 443 VDIVESQ, 444 VDIVEUQ, 445 VDIVSQ, 446 VDIVUQ 447)>; 448 449// 68 Cycles Decimal Floating Point operations, 2 input operands 450def : InstRW<[P10W_DF_68C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 451 (instrs 452 VMODSQ, 453 VMODUQ 454)>; 455 456// 77 Cycles Decimal Floating Point operations, 1 input operands 457def : InstRW<[P10W_DF_77C, P10W_DISP_ANY, P10DF_Read], 458 (instrs 459 XSSQRTQP, 460 XSSQRTQPO 461)>; 462 463// 20 Cycles Scalar Fixed-Point Divide operations, 2 input operands 464def : InstRW<[P10W_DV_20C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 465 (instrs 466 DIVW, 467 DIVWO, 468 DIVWU, 469 DIVWUO, 470 MODSW 471)>; 472 473// 2-way crack instructions 474// 20 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands 475def : InstRW<[P10W_DV_20C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 476 (instrs 477 DIVW_rec, 478 DIVWO_rec, 479 DIVWU_rec, 480 DIVWUO_rec 481)>; 482 483// 25 Cycles Scalar Fixed-Point Divide operations, 2 input operands 484def : InstRW<[P10W_DV_25C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 485 (instrs 486 DIVD, 487 DIVDO, 488 DIVDU, 489 DIVDUO, 490 DIVWE, 491 DIVWEO, 492 DIVWEU, 493 DIVWEUO 494)>; 495 496// 2-way crack instructions 497// 25 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands 498def : InstRW<[P10W_DV_25C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 499 (instrs 500 DIVD_rec, 501 DIVDO_rec, 502 DIVDU_rec, 503 DIVDUO_rec, 504 DIVWE_rec, 505 DIVWEO_rec, 506 DIVWEU_rec, 507 DIVWEUO_rec 508)>; 509 510// 27 Cycles Scalar Fixed-Point Divide operations, 2 input operands 511def : InstRW<[P10W_DV_27C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 512 (instrs 513 MODSD, 514 MODUD, 515 MODUW 516)>; 517 518// 41 Cycles Scalar Fixed-Point Divide operations, 2 input operands 519def : InstRW<[P10W_DV_41C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 520 (instrs 521 DIVDE, 522 DIVDEO, 523 DIVDEU, 524 DIVDEUO 525)>; 526 527// 2-way crack instructions 528// 41 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands 529def : InstRW<[P10W_DV_41C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 530 (instrs 531 DIVDE_rec, 532 DIVDEO_rec, 533 DIVDEU_rec, 534 DIVDEUO_rec 535)>; 536 537// 43 Cycles Scalar Fixed-Point Divide operations, 2 input operands 538def : InstRW<[P10W_DV_43C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 539 (instrs 540 VDIVSD, 541 VDIVUD 542)>; 543 544// 47 Cycles Scalar Fixed-Point Divide operations, 2 input operands 545def : InstRW<[P10W_DV_47C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 546 (instrs 547 VMODSD, 548 VMODUD 549)>; 550 551// 54 Cycles Scalar Fixed-Point Divide operations, 2 input operands 552def : InstRW<[P10W_DV_54C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 553 (instrs 554 VDIVSW, 555 VDIVUW 556)>; 557 558// 60 Cycles Scalar Fixed-Point Divide operations, 2 input operands 559def : InstRW<[P10W_DV_60C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 560 (instrs 561 VMODSW, 562 VMODUW 563)>; 564 565// 75 Cycles Scalar Fixed-Point Divide operations, 2 input operands 566def : InstRW<[P10W_DV_75C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 567 (instrs 568 VDIVESD, 569 VDIVEUD 570)>; 571 572// 83 Cycles Scalar Fixed-Point Divide operations, 2 input operands 573def : InstRW<[P10W_DV_83C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 574 (instrs 575 VDIVESW, 576 VDIVEUW 577)>; 578 579// 5 Cycles Fixed-Point and BCD operations, 1 input operands 580def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read], 581 (instrs 582 BCDCFN_rec, 583 BCDCFZ_rec, 584 BCDCTN_rec, 585 BCDCTZ_rec, 586 BCDSETSGN_rec, 587 VMUL10CUQ, 588 VMUL10UQ, 589 XSTSTDCQP, 590 XSXSIGQP, 591 XXGENPCVBM 592)>; 593 594// 5 Cycles Fixed-Point and BCD operations, 2 input operands 595def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read, P10DX_Read], 596 (instrs 597 BCDADD_rec, 598 BCDCPSGN_rec, 599 BCDS_rec, 600 BCDSUB_rec, 601 BCDTRUNC_rec, 602 BCDUS_rec, 603 BCDUTRUNC_rec, 604 VADDCUQ, 605 VADDUQM, 606 VMUL10ECUQ, 607 VMUL10EUQ, 608 VSUBCUQ, 609 VSUBUQM, 610 XSCMPEQQP, 611 XSCMPEXPQP, 612 XSCMPGEQP, 613 XSCMPGTQP, 614 XSCMPOQP, 615 XSCMPUQP, 616 XSMAXCQP, 617 XSMINCQP 618)>; 619 620// 5 Cycles Fixed-Point and BCD operations, 3 input operands 621def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read, P10DX_Read, P10DX_Read], 622 (instrs 623 VADDECUQ, 624 VADDEUQM, 625 VSUBECUQ, 626 VSUBEUQM 627)>; 628 629// 4 Cycles ALU2 operations, 0 input operands 630def : InstRW<[P10W_F2_4C, P10W_DISP_ANY], 631 (instrs 632 MTVSRBMI 633)>; 634 635// 4 Cycles ALU2 operations, 1 input operands 636def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read], 637 (instrs 638 CBCDTD, CBCDTD8, 639 CDTBCD, CDTBCD8, 640 CNTLZD, 641 CNTLZD_rec, 642 CNTLZW, CNTLZW8, 643 CNTLZW8_rec, CNTLZW_rec, 644 CNTTZD, 645 CNTTZD_rec, 646 CNTTZW, CNTTZW8, 647 CNTTZW8_rec, CNTTZW_rec, 648 EXTSWSLI_32_64_rec, EXTSWSLI_rec, 649 FTSQRT, 650 MTVSRBM, 651 MTVSRDM, 652 MTVSRHM, 653 MTVSRQM, 654 MTVSRWM, 655 POPCNTB, POPCNTB8, 656 POPCNTD, 657 POPCNTW, 658 RLDIC_rec, 659 RLDICL_32_rec, RLDICL_rec, 660 RLDICR_rec, 661 RLWINM8_rec, RLWINM_rec, 662 VCLZB, 663 VCLZD, 664 VCLZH, 665 VCLZW, 666 VCNTMBB, 667 VCNTMBD, 668 VCNTMBH, 669 VCNTMBW, 670 VCTZB, 671 VCTZD, 672 VCTZH, 673 VCTZW, 674 VEXPANDBM, 675 VEXPANDDM, 676 VEXPANDHM, 677 VEXPANDQM, 678 VEXPANDWM, 679 VEXTRACTBM, 680 VEXTRACTDM, 681 VEXTRACTHM, 682 VEXTRACTQM, 683 VEXTRACTWM, 684 VPOPCNTB, 685 VPOPCNTD, 686 VPOPCNTH, 687 VPOPCNTW, 688 VPRTYBD, 689 VPRTYBW, 690 VSHASIGMAD, 691 VSHASIGMAW, 692 XSCVHPDP, 693 XSCVSPDPN, 694 XSTSQRTDP, 695 XSTSTDCDP, 696 XSTSTDCSP, 697 XVCVHPSP, 698 XVTLSBB, 699 XVTSQRTDP, 700 XVTSQRTSP, 701 XVTSTDCDP, 702 XVTSTDCSP 703)>; 704 705// 4 Cycles ALU2 operations, 2 input operands 706def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read], 707 (instrs 708 CMPEQB, 709 CMPRB, CMPRB8, 710 FCMPOD, FCMPOS, 711 FCMPUD, FCMPUS, 712 FTDIV, 713 RLDCL_rec, 714 RLDCR_rec, 715 RLDIMI_rec, 716 RLWIMI8_rec, RLWIMI_rec, 717 RLWNM8_rec, RLWNM_rec, 718 SLD_rec, 719 SLW8_rec, SLW_rec, 720 SRD_rec, 721 SRW8_rec, SRW_rec, 722 TDI, 723 TWI, 724 VABSDUB, 725 VABSDUH, 726 VABSDUW, 727 VADDCUW, 728 VADDSBS, 729 VADDSHS, 730 VADDSWS, 731 VADDUBS, 732 VADDUHS, 733 VADDUWS, 734 VAVGSB, 735 VAVGSH, 736 VAVGSW, 737 VAVGUB, 738 VAVGUH, 739 VAVGUW, 740 VCMPBFP, 741 VCMPBFP_rec, 742 VCMPEQFP, 743 VCMPEQFP_rec, 744 VCMPEQUB_rec, 745 VCMPEQUD_rec, 746 VCMPEQUH_rec, 747 VCMPEQUQ, 748 VCMPEQUQ_rec, 749 VCMPEQUW_rec, 750 VCMPGEFP, 751 VCMPGEFP_rec, 752 VCMPGTFP, 753 VCMPGTFP_rec, 754 VCMPGTSB_rec, 755 VCMPGTSD_rec, 756 VCMPGTSH_rec, 757 VCMPGTSQ, 758 VCMPGTSQ_rec, 759 VCMPGTSW_rec, 760 VCMPGTUB_rec, 761 VCMPGTUD_rec, 762 VCMPGTUH_rec, 763 VCMPGTUQ, 764 VCMPGTUQ_rec, 765 VCMPGTUW_rec, 766 VCMPNEB_rec, 767 VCMPNEH_rec, 768 VCMPNEW_rec, 769 VCMPNEZB_rec, 770 VCMPNEZH_rec, 771 VCMPNEZW_rec, 772 VCMPSQ, 773 VCMPUQ, 774 VMAXFP, 775 VMINFP, 776 VSUBCUW, 777 VSUBSBS, 778 VSUBSHS, 779 VSUBSWS, 780 VSUBUBS, 781 VSUBUHS, 782 VSUBUWS, 783 XSCMPEQDP, 784 XSCMPEXPDP, 785 XSCMPGEDP, 786 XSCMPGTDP, 787 XSCMPODP, 788 XSCMPUDP, 789 XSMAXCDP, 790 XSMAXDP, 791 XSMAXJDP, 792 XSMINCDP, 793 XSMINDP, 794 XSMINJDP, 795 XSTDIVDP, 796 XVCMPEQDP, 797 XVCMPEQDP_rec, 798 XVCMPEQSP, 799 XVCMPEQSP_rec, 800 XVCMPGEDP, 801 XVCMPGEDP_rec, 802 XVCMPGESP, 803 XVCMPGESP_rec, 804 XVCMPGTDP, 805 XVCMPGTDP_rec, 806 XVCMPGTSP, 807 XVCMPGTSP_rec, 808 XVMAXDP, 809 XVMAXSP, 810 XVMINDP, 811 XVMINSP, 812 XVTDIVDP, 813 XVTDIVSP 814)>; 815 816// 4 Cycles ALU2 operations, 3 input operands 817def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read, P10F2_Read], 818 (instrs 819 TD, 820 TRAP, TW 821)>; 822 823// Single crack instructions 824// 4 Cycles ALU2 operations, 1 input operands 825def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_DISP_ANY, P10F2_Read], 826 (instrs 827 SRADI_rec, 828 SRAWI_rec, 829 TABORTDCI, 830 TABORTWCI 831)>; 832 833// Single crack instructions 834// 4 Cycles ALU2 operations, 2 input operands 835def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_DISP_ANY, P10F2_Read, P10F2_Read], 836 (instrs 837 SRAD_rec, 838 SRAW_rec, 839 TABORTDC, 840 TABORTWC 841)>; 842 843// 2-way crack instructions 844// 4 Cycles ALU2 operations, and 4 Cycles Permute operations, 2 input operands 845def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_PM_4C, P10W_DISP_ANY], 846 (instrs 847 VRLQ, 848 VRLQNM, 849 VSLQ, 850 VSRAQ, 851 VSRQ 852)>; 853 854// 2-way crack instructions 855// 4 Cycles ALU2 operations, and 4 Cycles Permute operations, 3 input operands 856def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_PM_4C, P10W_DISP_ANY], 857 (instrs 858 VRLQMI 859)>; 860 861// 2-way crack instructions 862// 4 Cycles ALU2 operations, and 4 Cycles ALU2 operations, 0 input operands 863def : InstRW<[P10W_F2_4C, P10W_DISP_PAIR, P10W_F2_4C], 864 (instrs 865 MFCR, MFCR8 866)>; 867 868// 2 Cycles ALU operations, 1 input operands 869def : InstRW<[P10W_FX_2C, P10W_DISP_ANY, P10FX_Read], 870 (instrs 871 MTCTR, MTCTR8, MTCTR8loop, MTCTRloop, 872 MTLR, MTLR8 873)>; 874 875// 3 Cycles ALU operations, 0 input operands 876def : InstRW<[P10W_FX_3C, P10W_DISP_ANY], 877 (instrs 878 DSS, DSSALL, 879 MCRXRX, 880 MFCTR, MFCTR8, 881 MFLR, MFLR8, 882 WAIT 883)>; 884 885// 3 Cycles ALU operations, 1 input operands 886def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read], 887 (instrs 888 ADDI, ADDI8, ADDIdtprelL32, ADDItlsldLADDR32, ADDItocL, LI, LI8, 889 ADDIC, ADDIC8, 890 ADDIS, ADDIS8, ADDISdtprelHA32, ADDIStocHA, ADDIStocHA8, LIS, LIS8, 891 ADDME, ADDME8, 892 ADDME8O, ADDMEO, 893 ADDZE, ADDZE8, 894 ADDZE8O, ADDZEO, 895 ANDI8_rec, ANDI_rec, 896 ANDIS8_rec, ANDIS_rec, 897 CMPDI, CMPWI, 898 CMPLDI, CMPLWI, 899 EXTSB, EXTSB8, EXTSB8_32_64, 900 EXTSB8_rec, EXTSB_rec, 901 EXTSH, EXTSH8, EXTSH8_32_64, 902 EXTSH8_rec, EXTSH_rec, 903 EXTSW, EXTSW_32, EXTSW_32_64, 904 EXTSW_32_64_rec, EXTSW_rec, 905 EXTSWSLI, EXTSWSLI_32_64, 906 FABSD, FABSS, 907 FMR, 908 FNABSD, FNABSS, 909 FNEGD, FNEGS, 910 MCRF, 911 MFOCRF, MFOCRF8, 912 MFVRD, MFVSRD, 913 MFVRWZ, MFVSRWZ, 914 MTOCRF, MTOCRF8, 915 MTVRD, MTVSRD, 916 MTVRWA, MTVSRWA, 917 MTVRWZ, MTVSRWZ, 918 NEG, NEG8, 919 NEG8_rec, NEG_rec, 920 NEG8O, NEGO, 921 NOP, NOP_GT_PWR6, NOP_GT_PWR7, ORI, ORI8, 922 ORIS, ORIS8, 923 RLDIC, 924 RLDICL, RLDICL_32, RLDICL_32_64, 925 RLDICR, RLDICR_32, 926 RLWINM, RLWINM8, 927 SETB, SETB8, 928 SETBC, SETBC8, 929 SETBCR, SETBCR8, 930 SETNBC, SETNBC8, 931 SETNBCR, SETNBCR8, 932 SRADI, SRADI_32, 933 SRAWI, 934 SUBFIC, SUBFIC8, 935 SUBFME, SUBFME8, 936 SUBFME8O, SUBFMEO, 937 SUBFZE, SUBFZE8, 938 SUBFZE8O, SUBFZEO, 939 VEXTSB2D, VEXTSB2Ds, 940 VEXTSB2W, VEXTSB2Ws, 941 VEXTSD2Q, 942 VEXTSH2D, VEXTSH2Ds, 943 VEXTSH2W, VEXTSH2Ws, 944 VEXTSW2D, VEXTSW2Ds, 945 VNEGD, 946 VNEGW, 947 XORI, XORI8, 948 XORIS, XORIS8, 949 XSABSDP, 950 XSABSQP, 951 XSNABSDP, XSNABSDPs, 952 XSNABSQP, 953 XSNEGDP, 954 XSNEGQP, 955 XSXEXPDP, 956 XSXEXPQP, 957 XSXSIGDP, 958 XVABSDP, 959 XVABSSP, 960 XVNABSDP, 961 XVNABSSP, 962 XVNEGDP, 963 XVNEGSP, 964 XVXEXPDP, 965 XVXEXPSP, 966 XVXSIGDP, 967 XVXSIGSP 968)>; 969 970// 3 Cycles ALU operations, 2 input operands 971def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 972 (instrs 973 ADD4, ADD4TLS, ADD8, ADD8TLS, ADD8TLS_, 974 ADD4_rec, ADD8_rec, 975 ADDE, ADDE8, 976 ADDE8O, ADDEO, 977 ADDEX, ADDEX8, 978 ADD4O, ADD8O, 979 AND, AND8, 980 AND8_rec, AND_rec, 981 ANDC, ANDC8, 982 ANDC8_rec, ANDC_rec, 983 CMPD, CMPW, 984 CMPB, CMPB8, 985 CMPLD, CMPLW, 986 CRAND, 987 CRANDC, 988 CR6SET, CREQV, CRSET, 989 CRNAND, 990 CRNOR, 991 CROR, 992 CRORC, 993 CR6UNSET, CRUNSET, CRXOR, 994 DST, DST64, DSTT, DSTT64, 995 DSTST, DSTST64, DSTSTT, DSTSTT64, 996 EQV, EQV8, 997 EQV8_rec, EQV_rec, 998 FCPSGND, FCPSGNS, 999 NAND, NAND8, 1000 NAND8_rec, NAND_rec, 1001 NOR, NOR8, 1002 NOR8_rec, NOR_rec, 1003 COPY, OR, OR8, 1004 OR8_rec, OR_rec, 1005 ORC, ORC8, 1006 ORC8_rec, ORC_rec, 1007 RLDCL, 1008 RLDCR, 1009 RLDIMI, 1010 RLWIMI, RLWIMI8, 1011 RLWNM, RLWNM8, 1012 SLD, 1013 SLW, SLW8, 1014 SRAD, 1015 SRAW, 1016 SRD, 1017 SRW, SRW8, 1018 SUBF, SUBF8, 1019 SUBF8_rec, SUBF_rec, 1020 SUBFE, SUBFE8, 1021 SUBFE8O, SUBFEO, 1022 SUBF8O, SUBFO, 1023 VADDUBM, 1024 VADDUDM, 1025 VADDUHM, 1026 VADDUWM, 1027 VAND, 1028 VANDC, 1029 VCMPEQUB, 1030 VCMPEQUD, 1031 VCMPEQUH, 1032 VCMPEQUW, 1033 VCMPGTSB, 1034 VCMPGTSD, 1035 VCMPGTSH, 1036 VCMPGTSW, 1037 VCMPGTUB, 1038 VCMPGTUD, 1039 VCMPGTUH, 1040 VCMPGTUW, 1041 VCMPNEB, 1042 VCMPNEH, 1043 VCMPNEW, 1044 VCMPNEZB, 1045 VCMPNEZH, 1046 VCMPNEZW, 1047 VEQV, 1048 VMAXSB, 1049 VMAXSD, 1050 VMAXSH, 1051 VMAXSW, 1052 VMAXUB, 1053 VMAXUD, 1054 VMAXUH, 1055 VMAXUW, 1056 VMINSB, 1057 VMINSD, 1058 VMINSH, 1059 VMINSW, 1060 VMINUB, 1061 VMINUD, 1062 VMINUH, 1063 VMINUW, 1064 VMRGEW, 1065 VMRGOW, 1066 VNAND, 1067 VNOR, 1068 VOR, 1069 VORC, 1070 VRLB, 1071 VRLD, 1072 VRLDNM, 1073 VRLH, 1074 VRLW, 1075 VRLWNM, 1076 VSLB, 1077 VSLD, 1078 VSLH, 1079 VSLW, 1080 VSRAB, 1081 VSRAD, 1082 VSRAH, 1083 VSRAW, 1084 VSRB, 1085 VSRD, 1086 VSRH, 1087 VSRW, 1088 VSUBUBM, 1089 VSUBUDM, 1090 VSUBUHM, 1091 VSUBUWM, 1092 VXOR, V_SET0, V_SET0B, V_SET0H, 1093 XOR, XOR8, 1094 XOR8_rec, XOR_rec, 1095 XSCPSGNDP, 1096 XSCPSGNQP, 1097 XSIEXPDP, 1098 XSIEXPQP, 1099 XVCPSGNDP, 1100 XVCPSGNSP, 1101 XVIEXPDP, 1102 XVIEXPSP, 1103 XXLAND, 1104 XXLANDC, 1105 XXLEQV, XXLEQVOnes, 1106 XXLNAND, 1107 XXLNOR, 1108 XXLOR, XXLORf, 1109 XXLORC, 1110 XXLXOR, XXLXORdpz, XXLXORspz, XXLXORz 1111)>; 1112 1113// 3 Cycles ALU operations, 3 input operands 1114def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read, P10FX_Read], 1115 (instrs 1116 ISEL, ISEL8, 1117 VRLDMI, 1118 VRLWMI, 1119 VSEL, 1120 XXSEL 1121)>; 1122 1123// Single crack instructions 1124// 3 Cycles ALU operations, 0 input operands 1125def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_DISP_ANY], 1126 (instrs 1127 MFFS, 1128 MFFS_rec, 1129 MFFSCDRNI, 1130 MFFSCRNI, 1131 MFFSL, 1132 MFVSCR, 1133 MTFSB0, 1134 TBEGIN, 1135 TRECHKPT, 1136 TSR 1137)>; 1138 1139// Single crack instructions 1140// 3 Cycles ALU operations, 1 input operands 1141def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10FX_Read], 1142 (instrs 1143 ADDIC_rec, 1144 ADDME8_rec, ADDME_rec, 1145 ADDME8O_rec, ADDMEO_rec, 1146 ADDZE8_rec, ADDZE_rec, 1147 ADDZE8O_rec, ADDZEO_rec, 1148 MCRFS, 1149 MFFSCDRN, 1150 MFFSCRN, 1151 MTVSCR, 1152 NEG8O_rec, NEGO_rec, 1153 SUBFME8_rec, SUBFME_rec, 1154 SUBFME8O_rec, SUBFMEO_rec, 1155 SUBFZE8_rec, SUBFZE_rec, 1156 SUBFZE8O_rec, SUBFZEO_rec, 1157 TABORT, 1158 TRECLAIM 1159)>; 1160 1161// Single crack instructions 1162// 3 Cycles ALU operations, 2 input operands 1163def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 1164 (instrs 1165 ADDE8_rec, ADDE_rec, 1166 ADDE8O_rec, ADDEO_rec, 1167 ADD4O_rec, ADD8O_rec, 1168 SUBFE8_rec, SUBFE_rec, 1169 SUBFE8O_rec, SUBFEO_rec, 1170 SUBF8O_rec, SUBFO_rec 1171)>; 1172 1173// 2-way crack instructions 1174// 3 Cycles ALU operations, and 4 Cycles ALU2 operations, 2 input operands 1175def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_F2_4C, P10W_DISP_ANY], 1176 (instrs 1177 ADDG6S, ADDG6S8 1178)>; 1179 1180// 2-way crack instructions 1181// 3 Cycles ALU operations, and 3 Cycles ALU operations, 0 input operands 1182def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1183 (instrs 1184 HRFID, 1185 MFFSCE, 1186 MTFSB1, 1187 MTFSFI, MTFSFIb, 1188 MTFSFI_rec, 1189 RFEBB, 1190 RFID, 1191 SC, 1192 STOP 1193)>; 1194 1195// 2-way crack instructions 1196// 3 Cycles ALU operations, and 3 Cycles ALU operations, 1 input operands 1197def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read], 1198 (instrs 1199 FABSD_rec, FABSS_rec, 1200 FMR_rec, 1201 FNABSD_rec, FNABSS_rec, 1202 FNEGD_rec, FNEGS_rec, 1203 MTFSF, MTFSFb, 1204 MTFSF_rec 1205)>; 1206 1207// 2-way crack instructions 1208// 3 Cycles ALU operations, and 3 Cycles ALU operations, 2 input operands 1209def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 1210 (instrs 1211 ADDC, ADDC8, 1212 ADDC8_rec, ADDC_rec, 1213 ADDC8O, ADDCO, 1214 FCPSGND_rec, FCPSGNS_rec, 1215 SUBFC, SUBFC8, 1216 SUBFC8_rec, SUBFC_rec, 1217 SUBFC8O, SUBFCO 1218)>; 1219 1220// 4-way crack instructions 1221// 3 Cycles ALU operations, 3 Cycles ALU operations, 3 Cycles ALU operations, and 3 Cycles ALU operations, 2 input operands 1222def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 1223 (instrs 1224 ADDC8O_rec, ADDCO_rec, 1225 SUBFC8O_rec, SUBFCO_rec 1226)>; 1227 1228// 2-way crack instructions 1229// 3 Cycles ALU operations, and 4 Cycles Permute operations, 1 input operands 1230def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_PM_4C, P10W_DISP_ANY], 1231 (instrs 1232 VSTRIBL_rec, 1233 VSTRIBR_rec, 1234 VSTRIHL_rec, 1235 VSTRIHR_rec 1236)>; 1237 1238// 2-way crack instructions 1239// 3 Cycles ALU operations, and 3 Cycles ALU operations, 1 input operands 1240def : InstRW<[P10W_FX_3C, P10W_DISP_PAIR, P10W_FX_3C, P10FX_Read], 1241 (instrs 1242 MTCRF, MTCRF8 1243)>; 1244 1245// 6 Cycles Load operations, 0 input operands 1246def : InstRW<[P10W_LD_6C, P10W_DISP_ANY], 1247 (instrs 1248 LBZ, LBZ8, 1249 LD, LDtoc, LDtocBA, LDtocCPT, LDtocJTI, LDtocL, SPILLTOVSR_LD, 1250 DFLOADf32, DFLOADf64, LFD, 1251 LHA, LHA8, 1252 LHZ, LHZ8, 1253 LWA, LWA_32, 1254 LWZ, LWZ8, LWZtoc, LWZtocL, 1255 LXSD, 1256 LXV 1257)>; 1258 1259// 6 Cycles Load operations, 1 input operands 1260def : InstRW<[P10W_LD_6C, P10W_DISP_ANY, P10LD_Read], 1261 (instrs 1262 LXVL, 1263 LXVLL 1264)>; 1265 1266// 6 Cycles Load operations, 2 input operands 1267def : InstRW<[P10W_LD_6C, P10W_DISP_ANY, P10LD_Read, P10LD_Read], 1268 (instrs 1269 DCBT, 1270 DCBTST, 1271 ICBT, 1272 LBZX, LBZX8, LBZXTLS, LBZXTLS_, LBZXTLS_32, 1273 LDBRX, 1274 LDX, LDXTLS, LDXTLS_, SPILLTOVSR_LDX, 1275 LFDX, LFDXTLS, LFDXTLS_, XFLOADf32, XFLOADf64, 1276 LFIWAX, LIWAX, 1277 LFIWZX, LIWZX, 1278 LHAX, LHAX8, LHAXTLS, LHAXTLS_, LHAXTLS_32, 1279 LHBRX, LHBRX8, 1280 LHZX, LHZX8, LHZXTLS, LHZXTLS_, LHZXTLS_32, 1281 LVEBX, 1282 LVEHX, 1283 LVEWX, 1284 LVX, 1285 LVXL, 1286 LWAX, LWAXTLS, LWAXTLS_, LWAXTLS_32, LWAX_32, 1287 LWBRX, LWBRX8, 1288 LWZX, LWZX8, LWZXTLS, LWZXTLS_, LWZXTLS_32, 1289 LXSDX, 1290 LXSIBZX, 1291 LXSIHZX, 1292 LXSIWAX, 1293 LXSIWZX, 1294 LXVB16X, 1295 LXVD2X, 1296 LXVDSX, 1297 LXVH8X, 1298 LXVRBX, 1299 LXVRDX, 1300 LXVRHX, 1301 LXVRWX, 1302 LXVW4X, 1303 LXVWSX, 1304 LXVX 1305)>; 1306 1307// 2-way crack instructions 1308// 6 Cycles Load operations, and 13 Cycles Decimal Floating Point operations, 1 input operands 1309def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DF_13C, P10W_DISP_ANY], 1310 (instrs 1311 HASHCHK, HASHCHK8, 1312 HASHCHKP, HASHCHKP8 1313)>; 1314 1315// Single crack instructions 1316// 6 Cycles Load operations, 0 input operands 1317def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DISP_ANY], 1318 (instrs 1319 DARN, 1320 SLBIA 1321)>; 1322 1323// Single crack instructions 1324// 6 Cycles Load operations, 1 input operands 1325def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DISP_ANY, P10LD_Read], 1326 (instrs 1327 MTSPR, MTSPR8, MTSR, MTUDSCR, MTVRSAVE, MTVRSAVEv, 1328 SLBFEE_rec, 1329 SLBIE, 1330 SLBMFEE, 1331 SLBMFEV 1332)>; 1333 1334// Single crack instructions 1335// 6 Cycles Load operations, 2 input operands 1336def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DISP_ANY, P10LD_Read, P10LD_Read], 1337 (instrs 1338 LBARX, LBARXL, 1339 LBZCIX, 1340 LDARX, LDARXL, 1341 LDCIX, 1342 LHARX, LHARXL, 1343 LHZCIX, 1344 LWARX, LWARXL, 1345 LWZCIX 1346)>; 1347 1348// Expand instructions 1349// 6 Cycles Load operations, 6 Cycles Load operations, 6 Cycles Load operations, and 6 Cycles Load operations, 0 input operands 1350def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY], 1351 (instrs 1352 LMW 1353)>; 1354 1355// Expand instructions 1356// 6 Cycles Load operations, 6 Cycles Load operations, 6 Cycles Load operations, and 6 Cycles Load operations, 1 input operands 1357def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10LD_Read], 1358 (instrs 1359 LSWI 1360)>; 1361 1362// 2-way crack instructions 1363// 6 Cycles Load operations, and 3 Cycles Simple Fixed-point (SFX) operations, 0 input operands 1364def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_SX_3C, P10W_DISP_ANY], 1365 (instrs 1366 LBZU, LBZU8, 1367 LDU, 1368 LFDU, 1369 LHAU, LHAU8, 1370 LHZU, LHZU8, 1371 LWZU, LWZU8 1372)>; 1373 1374// 2-way crack instructions 1375// 6 Cycles Load operations, and 3 Cycles Simple Fixed-point (SFX) operations, 2 input operands 1376def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_SX_3C, P10W_DISP_ANY], 1377 (instrs 1378 LBZUX, LBZUX8, 1379 LDUX, 1380 LFDUX, 1381 LHAUX, LHAUX8, 1382 LHZUX, LHZUX8, 1383 LWAUX, 1384 LWZUX, LWZUX8 1385)>; 1386 1387// 6 Cycles Load operations, 0 input operands 1388def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR], 1389 (instrs 1390 PLBZ, PLBZ8, PLBZ8pc, PLBZpc, 1391 PLD, PLDpc, 1392 PLFD, PLFDpc, 1393 PLFS, PLFSpc, 1394 PLHA, PLHA8, PLHA8pc, PLHApc, 1395 PLHZ, PLHZ8, PLHZ8pc, PLHZpc, 1396 PLWA, PLWA8, PLWA8pc, PLWApc, 1397 PLWZ, PLWZ8, PLWZ8pc, PLWZpc, 1398 PLXSD, PLXSDpc, 1399 PLXSSP, PLXSSPpc, 1400 PLXV, PLXVpc, 1401 PLXVP, PLXVPpc 1402)>; 1403 1404// 2-way crack instructions 1405// 6 Cycles Load operations, and 4 Cycles ALU2 operations, 0 input operands 1406def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C], 1407 (instrs 1408 LFS, 1409 LXSSP 1410)>; 1411 1412// 2-way crack instructions 1413// 6 Cycles Load operations, and 4 Cycles ALU2 operations, 2 input operands 1414def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C], 1415 (instrs 1416 LFSX, LFSXTLS, LFSXTLS_, 1417 LXSSPX 1418)>; 1419 1420// 4-way crack instructions 1421// 6 Cycles Load operations, 4 Cycles ALU2 operations, 3 Cycles Simple Fixed-point (SFX) operations, and 3 Cycles ALU operations, 0 input operands 1422def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C, P10W_SX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY], 1423 (instrs 1424 LFSU 1425)>; 1426 1427// 4-way crack instructions 1428// 6 Cycles Load operations, 4 Cycles ALU2 operations, 3 Cycles Simple Fixed-point (SFX) operations, and 3 Cycles ALU operations, 2 input operands 1429def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C, P10W_SX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY], 1430 (instrs 1431 LFSUX 1432)>; 1433 1434// 2-way crack instructions 1435// 6 Cycles Load operations, and 6 Cycles Load operations, 1 input operands 1436def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_LD_6C, P10W_DISP_PAIR, P10LD_Read], 1437 (instrs 1438 TLBIEL 1439)>; 1440 1441// 2-way crack instructions 1442// 6 Cycles Load operations, and 6 Cycles Load operations, 2 input operands 1443def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_LD_6C, P10W_DISP_PAIR, P10LD_Read, P10LD_Read], 1444 (instrs 1445 SLBMTE 1446)>; 1447 1448// 2-way crack instructions 1449// 6 Cycles Load operations, and 3 Cycles Simple Fixed-point (SFX) operations, 0 input operands 1450def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_SX_3C], 1451 (instrs 1452 LXVP 1453)>; 1454 1455// 2-way crack instructions 1456// 6 Cycles Load operations, and 3 Cycles Simple Fixed-point (SFX) operations, 2 input operands 1457def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_SX_3C], 1458 (instrs 1459 LXVPX 1460)>; 1461 1462// Single crack instructions 1463// 13 Cycles Unknown operations, 1 input operands 1464def : InstRW<[P10W_MFL_13C, P10W_DISP_EVEN, P10W_DISP_ANY], 1465 (instrs 1466 MFSPR, MFSPR8, MFSR, MFTB8, MFUDSCR, MFVRSAVE, MFVRSAVEv 1467)>; 1468 1469// 10 Cycles SIMD Matrix Multiply Engine operations, 0 input operands 1470def : InstRW<[P10W_MM_10C, P10W_DISP_ANY], 1471 (instrs 1472 XXSETACCZ 1473)>; 1474 1475// 10 Cycles SIMD Matrix Multiply Engine operations, 2 input operands 1476def : InstRW<[P10W_MM_10C, P10W_DISP_ANY, P10MM_Read, P10MM_Read], 1477 (instrs 1478 XVBF16GER2, 1479 XVF16GER2, 1480 XVF32GER, 1481 XVF64GER, 1482 XVI16GER2, 1483 XVI16GER2S, 1484 XVI4GER8, 1485 XVI8GER4 1486)>; 1487 1488// 10 Cycles SIMD Matrix Multiply Engine operations, 3 input operands 1489def : InstRW<[P10W_MM_10C, P10W_DISP_ANY, P10MM_Read, P10MM_Read, P10MM_Read], 1490 (instrs 1491 XVBF16GER2NN, 1492 XVBF16GER2NP, 1493 XVBF16GER2PN, 1494 XVBF16GER2PP, 1495 XVF16GER2NN, 1496 XVF16GER2NP, 1497 XVF16GER2PN, 1498 XVF16GER2PP, 1499 XVF32GERNN, 1500 XVF32GERNP, 1501 XVF32GERPN, 1502 XVF32GERPP, 1503 XVF64GERNN, 1504 XVF64GERNP, 1505 XVF64GERPN, 1506 XVF64GERPP, 1507 XVI16GER2PP, 1508 XVI16GER2SPP, 1509 XVI4GER8PP, 1510 XVI8GER4PP, 1511 XVI8GER4SPP 1512)>; 1513 1514// 10 Cycles SIMD Matrix Multiply Engine operations, 2 input operands 1515def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10MM_Read, P10MM_Read], 1516 (instrs 1517 PMXVBF16GER2, 1518 PMXVF16GER2, 1519 PMXVF32GER, 1520 PMXVF64GER, 1521 PMXVI16GER2, 1522 PMXVI16GER2S, 1523 PMXVI4GER8, 1524 PMXVI8GER4 1525)>; 1526 1527// 10 Cycles SIMD Matrix Multiply Engine operations, 3 input operands 1528def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10MM_Read, P10MM_Read, P10MM_Read], 1529 (instrs 1530 PMXVBF16GER2NN, 1531 PMXVBF16GER2NP, 1532 PMXVBF16GER2PN, 1533 PMXVBF16GER2PP, 1534 PMXVF16GER2NN, 1535 PMXVF16GER2NP, 1536 PMXVF16GER2PN, 1537 PMXVF16GER2PP, 1538 PMXVF32GERNN, 1539 PMXVF32GERNP, 1540 PMXVF32GERPN, 1541 PMXVF32GERPP, 1542 PMXVF64GERNN, 1543 PMXVF64GERNP, 1544 PMXVF64GERPN, 1545 PMXVF64GERPP, 1546 PMXVI16GER2PP, 1547 PMXVI16GER2SPP, 1548 PMXVI4GER8PP, 1549 PMXVI8GER4PP, 1550 PMXVI8GER4SPP 1551)>; 1552 1553// 2-way crack instructions 1554// 10 Cycles SIMD Matrix Multiply Engine operations, and 3 Cycles ALU operations, 1 input operands 1555def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10W_FX_3C], 1556 (instrs 1557 XXMTACC 1558)>; 1559 1560// 4-way crack instructions 1561// 10 Cycles SIMD Matrix Multiply Engine operations, 3 Cycles ALU operations, 10 Cycles SIMD Matrix Multiply Engine operations, and 3 Cycles ALU operations, 1 input operands 1562def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10W_FX_3C, P10W_MM_10C, P10W_DISP_PAIR, P10W_FX_3C], 1563 (instrs 1564 XXMFACC 1565)>; 1566 1567// 5 Cycles GPR Multiply operations, 1 input operands 1568def : InstRW<[P10W_MU_5C, P10W_DISP_ANY, P10MU_Read], 1569 (instrs 1570 MULLI, MULLI8 1571)>; 1572 1573// 5 Cycles GPR Multiply operations, 2 input operands 1574def : InstRW<[P10W_MU_5C, P10W_DISP_ANY, P10MU_Read, P10MU_Read], 1575 (instrs 1576 MULHD, 1577 MULHDU, 1578 MULHW, 1579 MULHWU, 1580 MULLD, 1581 MULLDO, 1582 MULLW, 1583 MULLWO, 1584 VMULHSD, 1585 VMULHUD, 1586 VMULLD 1587)>; 1588 1589// 5 Cycles GPR Multiply operations, 3 input operands 1590def : InstRW<[P10W_MU_5C, P10W_DISP_ANY, P10MU_Read, P10MU_Read, P10MU_Read], 1591 (instrs 1592 MADDHD, 1593 MADDHDU, 1594 MADDLD, MADDLD8 1595)>; 1596 1597// 2-way crack instructions 1598// 5 Cycles GPR Multiply operations, and 3 Cycles ALU operations, 2 input operands 1599def : InstRW<[P10W_MU_5C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1600 (instrs 1601 MULHD_rec, 1602 MULHDU_rec, 1603 MULHW_rec, 1604 MULHWU_rec, 1605 MULLD_rec, 1606 MULLDO_rec, 1607 MULLW_rec, 1608 MULLWO_rec 1609)>; 1610 1611// 4 Cycles Permute operations, 0 input operands 1612def : InstRW<[P10W_PM_4C, P10W_DISP_ANY], 1613 (instrs 1614 LXVKQ, 1615 VSPLTISB, 1616 VSPLTISH, 1617 VSPLTISW, V_SETALLONES, V_SETALLONESB, V_SETALLONESH, 1618 XXSPLTIB 1619)>; 1620 1621// 4 Cycles Permute operations, 1 input operands 1622def : InstRW<[P10W_PM_4C, P10W_DISP_ANY, P10PM_Read], 1623 (instrs 1624 BRD, 1625 BRH, BRH8, 1626 BRW, BRW8, 1627 MFVSRLD, 1628 MTVSRWS, 1629 VCLZLSBB, 1630 VCTZLSBB, 1631 VEXTRACTD, 1632 VEXTRACTUB, 1633 VEXTRACTUH, 1634 VEXTRACTUW, 1635 VGBBD, 1636 VINSERTD, 1637 VINSERTW, 1638 VPRTYBQ, 1639 VSPLTB, VSPLTBs, 1640 VSPLTH, VSPLTHs, 1641 VSPLTW, 1642 VSTRIBL, 1643 VSTRIBR, 1644 VSTRIHL, 1645 VSTRIHR, 1646 VUPKHPX, 1647 VUPKHSB, 1648 VUPKHSH, 1649 VUPKHSW, 1650 VUPKLPX, 1651 VUPKLSB, 1652 VUPKLSH, 1653 VUPKLSW, 1654 XVCVBF16SPN, 1655 XXBRD, 1656 XXBRH, 1657 XXBRQ, 1658 XXBRW, 1659 XXEXTRACTUW, 1660 XXGENPCVDM, 1661 XXGENPCVHM, 1662 XXGENPCVWM, 1663 XXSPLTW, XXSPLTWs 1664)>; 1665 1666// 4 Cycles Permute operations, 2 input operands 1667def : InstRW<[P10W_PM_4C, P10W_DISP_ANY, P10PM_Read, P10PM_Read], 1668 (instrs 1669 BPERMD, 1670 LVSL, 1671 LVSR, 1672 MTVSRDD, 1673 VBPERMD, 1674 VBPERMQ, 1675 VCLRLB, 1676 VCLRRB, 1677 VEXTUBLX, 1678 VEXTUBRX, 1679 VEXTUHLX, 1680 VEXTUHRX, 1681 VEXTUWLX, 1682 VEXTUWRX, 1683 VINSD, 1684 VINSERTB, 1685 VINSERTH, 1686 VINSW, 1687 VMRGHB, 1688 VMRGHH, 1689 VMRGHW, 1690 VMRGLB, 1691 VMRGLH, 1692 VMRGLW, 1693 VPKPX, 1694 VPKSDSS, 1695 VPKSDUS, 1696 VPKSHSS, 1697 VPKSHUS, 1698 VPKSWSS, 1699 VPKSWUS, 1700 VPKUDUM, 1701 VPKUDUS, 1702 VPKUHUM, 1703 VPKUHUS, 1704 VPKUWUM, 1705 VPKUWUS, 1706 VSL, 1707 VSLDBI, 1708 VSLDOI, 1709 VSLO, 1710 VSLV, 1711 VSR, 1712 VSRDBI, 1713 VSRO, 1714 VSRV, 1715 XXINSERTW, 1716 XXMRGHW, 1717 XXMRGLW, 1718 XXPERMDI, XXPERMDIs, 1719 XXSLDWI, XXSLDWIs 1720)>; 1721 1722// 4 Cycles Permute operations, 3 input operands 1723def : InstRW<[P10W_PM_4C, P10W_DISP_ANY, P10PM_Read, P10PM_Read, P10PM_Read], 1724 (instrs 1725 VEXTDDVLX, 1726 VEXTDDVRX, 1727 VEXTDUBVLX, 1728 VEXTDUBVRX, 1729 VEXTDUHVLX, 1730 VEXTDUHVRX, 1731 VEXTDUWVLX, 1732 VEXTDUWVRX, 1733 VINSBLX, 1734 VINSBRX, 1735 VINSBVLX, 1736 VINSBVRX, 1737 VINSDLX, 1738 VINSDRX, 1739 VINSHLX, 1740 VINSHRX, 1741 VINSHVLX, 1742 VINSHVRX, 1743 VINSWLX, 1744 VINSWRX, 1745 VINSWVLX, 1746 VINSWVRX, 1747 VPERM, 1748 VPERMR, 1749 VPERMXOR, 1750 XXPERM, 1751 XXPERMR 1752)>; 1753 1754// 2-way crack instructions 1755// 4 Cycles Permute operations, and 7 Cycles VMX Multiply operations, 2 input operands 1756def : InstRW<[P10W_PM_4C, P10W_DISP_EVEN, P10W_vMU_7C, P10W_DISP_ANY], 1757 (instrs 1758 VSUMSWS 1759)>; 1760 1761// 4 Cycles Permute operations, 0 input operands 1762def : InstRW<[P10W_PM_4C, P10W_DISP_PAIR], 1763 (instrs 1764 XXSPLTIDP, 1765 XXSPLTIW 1766)>; 1767 1768// 4 Cycles Permute operations, 1 input operands 1769def : InstRW<[P10W_PM_4C, P10W_DISP_PAIR, P10PM_Read], 1770 (instrs 1771 XXSPLTI32DX 1772)>; 1773 1774// 4 Cycles Permute operations, 3 input operands 1775def : InstRW<[P10W_PM_4C, P10W_DISP_PAIR, P10PM_Read, P10PM_Read, P10PM_Read], 1776 (instrs 1777 XXBLENDVB, 1778 XXBLENDVD, 1779 XXBLENDVH, 1780 XXBLENDVW, 1781 XXEVAL, 1782 XXPERMX 1783)>; 1784 1785// 3 Cycles Store operations, 1 input operands 1786def : InstRW<[P10W_ST_3C, P10W_DISP_ANY, P10ST_Read], 1787 (instrs 1788 PSTXVP, PSTXVPpc, 1789 STB, STB8, 1790 STBU, STBU8, 1791 SPILLTOVSR_ST, STD, 1792 STDU, 1793 DFSTOREf32, DFSTOREf64, STFD, 1794 STFDU, 1795 STFS, 1796 STFSU, 1797 STH, STH8, 1798 STHU, STHU8, 1799 STW, STW8, 1800 STWU, STWU8, 1801 STXSD, 1802 STXSSP, 1803 STXV 1804)>; 1805 1806// 3 Cycles Store operations, 2 input operands 1807def : InstRW<[P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read], 1808 (instrs 1809 CP_COPY, CP_COPY8, 1810 DCBF, 1811 DCBST, 1812 DCBZ, 1813 ICBI, 1814 STXVL, 1815 STXVLL 1816)>; 1817 1818// 3 Cycles Store operations, 3 input operands 1819def : InstRW<[P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read, P10ST_Read], 1820 (instrs 1821 STBUX, STBUX8, 1822 STBX, STBX8, STBXTLS, STBXTLS_, STBXTLS_32, 1823 STDBRX, 1824 STDUX, 1825 SPILLTOVSR_STX, STDX, STDXTLS, STDXTLS_, 1826 STFDUX, 1827 STFDX, STFDXTLS, STFDXTLS_, 1828 STFIWX, STIWX, 1829 STFSUX, 1830 STFSX, STFSXTLS, STFSXTLS_, 1831 STHBRX, 1832 STHUX, STHUX8, 1833 STHX, STHX8, STHXTLS, STHXTLS_, STHXTLS_32, 1834 STVEBX, 1835 STVEHX, 1836 STVEWX, 1837 STVX, 1838 STVXL, 1839 STWBRX, 1840 STWUX, STWUX8, 1841 STWX, STWX8, STWXTLS, STWXTLS_, STWXTLS_32, 1842 STXSDX, 1843 STXSIBX, STXSIBXv, 1844 STXSIHX, STXSIHXv, 1845 STXSIWX, 1846 STXSSPX, 1847 STXVB16X, 1848 STXVD2X, 1849 STXVH8X, 1850 STXVRBX, 1851 STXVRDX, 1852 STXVRHX, 1853 STXVRWX, 1854 STXVW4X, 1855 STXVX 1856)>; 1857 1858// Single crack instructions 1859// 3 Cycles Store operations, 0 input operands 1860def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY], 1861 (instrs 1862 EnforceIEIO, 1863 MSGSYNC, 1864 SLBSYNC, 1865 TCHECK, 1866 TEND, 1867 TLBSYNC 1868)>; 1869 1870// Single crack instructions 1871// 3 Cycles Store operations, 2 input operands 1872def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read, P10ST_Read], 1873 (instrs 1874 CP_PASTE8_rec, CP_PASTE_rec, 1875 SLBIEG, 1876 TLBIE 1877)>; 1878 1879// Single crack instructions 1880// 3 Cycles Store operations, 3 input operands 1881def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read, P10ST_Read, P10ST_Read], 1882 (instrs 1883 STBCIX, 1884 STBCX, 1885 STDCIX, 1886 STDCX, 1887 STHCIX, 1888 STHCX, 1889 STWCIX, 1890 STWCX 1891)>; 1892 1893// 2-way crack instructions 1894// 3 Cycles Store operations, and 3 Cycles ALU operations, 0 input operands 1895def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1896 (instrs 1897 ISYNC, 1898 SYNC 1899)>; 1900 1901// Expand instructions 1902// 3 Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, 3 Cycles ALU operations, 6 Cycles Load operations, and 3 Cycles Store operations, 1 input operands 1903def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY], 1904 (instrs 1905 LDAT, 1906 LWAT 1907)>; 1908 1909// 4-way crack instructions 1910// 3 Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, and 3 Cycles Store operations, 2 input operands 1911def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY], 1912 (instrs 1913 STDAT, 1914 STWAT 1915)>; 1916 1917// Expand instructions 1918// 3 Cycles Store operations, 3 Cycles Store operations, 3 Cycles Store operations, and 3 Cycles Store operations, 1 input operands 1919def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10ST_Read], 1920 (instrs 1921 STMW 1922)>; 1923 1924// Expand instructions 1925// 3 Cycles Store operations, 3 Cycles Store operations, 3 Cycles Store operations, and 3 Cycles Store operations, 2 input operands 1926def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read], 1927 (instrs 1928 STSWI 1929)>; 1930 1931// 3 Cycles Store operations, 1 input operands 1932def : InstRW<[P10W_ST_3C, P10W_DISP_PAIR, P10ST_Read], 1933 (instrs 1934 PSTB, PSTB8, PSTB8pc, PSTBpc, 1935 PSTD, PSTDpc, 1936 PSTFD, PSTFDpc, 1937 PSTFS, PSTFSpc, 1938 PSTH, PSTH8, PSTH8pc, PSTHpc, 1939 PSTW, PSTW8, PSTW8pc, PSTWpc, 1940 PSTXSD, PSTXSDpc, 1941 PSTXSSP, PSTXSSPpc, 1942 PSTXV, PSTXVpc 1943)>; 1944 1945// 2-way crack instructions 1946// 3 Cycles Store operations, and 3 Cycles Store operations, 1 input operands 1947def : InstRW<[P10W_ST_3C, P10W_DISP_PAIR, P10W_ST_3C, P10ST_Read], 1948 (instrs 1949 STXVP 1950)>; 1951 1952// 2-way crack instructions 1953// 3 Cycles Store operations, and 3 Cycles Store operations, 3 input operands 1954def : InstRW<[P10W_ST_3C, P10W_DISP_PAIR, P10W_ST_3C, P10ST_Read, P10ST_Read, P10ST_Read], 1955 (instrs 1956 STXVPX 1957)>; 1958 1959// FIXME - Miss scheduling information from datasheet 1960// Temporary set it as 1 Cycles Simple Fixed-point (SFX) operations, 0 input operands 1961def : InstRW<[P10W_SX, P10W_DISP_ANY], 1962 (instrs 1963 ATTN, 1964 CP_ABORT, 1965 CRNOT, 1966 DCBA, 1967 DCBI, 1968 DCBZL, 1969 DCCCI, 1970 ICBLC, 1971 ICBLQ, 1972 ICBTLS, 1973 ICCCI, 1974 LA, LA8, 1975 MFDCR, 1976 MFPMR, 1977 MFSRIN, 1978 MSYNC, 1979 MTDCR, 1980 MTPMR, 1981 MTSRIN, 1982 NAP, 1983 TLBIA, 1984 TLBLD, 1985 TLBLI, 1986 TLBRE2, 1987 TLBSX2, 1988 TLBSX2D, 1989 TLBWE2 1990)>; 1991 1992// Single crack instructions 1993// 3 Cycles Simple Fixed-point (SFX) operations, 0 input operands 1994def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_DISP_ANY], 1995 (instrs 1996 CLRBHRB, 1997 MFBHRBE, 1998 MFMSR, 1999 MFTB 2000)>; 2001 2002// Single crack instructions 2003// 3 Cycles Simple Fixed-point (SFX) operations, 1 input operands 2004def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10SX_Read], 2005 (instrs 2006 MTMSR, 2007 MTMSRD 2008)>; 2009 2010// 2-way crack instructions 2011// 3 Cycles Simple Fixed-point (SFX) operations, and 3 Cycles ALU operations, 0 input operands 2012def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 2013 (instrs 2014 ADDPCIS 2015)>; 2016 2017// 3 Cycles Simple Fixed-point (SFX) operations, 1 input operands 2018def : InstRW<[P10W_SX_3C, P10W_DISP_PAIR, P10SX_Read], 2019 (instrs 2020 PADDI, PADDI8, PADDI8pc, PADDIpc, PLI, PLI8 2021)>; 2022 2023// 7 Cycles VMX Multiply operations, 2 input operands 2024def : InstRW<[P10W_vMU_7C, P10W_DISP_ANY, P10vMU_Read, P10vMU_Read], 2025 (instrs 2026 VMULESB, 2027 VMULESD, 2028 VMULESH, 2029 VMULESW, 2030 VMULEUB, 2031 VMULEUD, 2032 VMULEUH, 2033 VMULEUW, 2034 VMULHSW, 2035 VMULHUW, 2036 VMULOSB, 2037 VMULOSD, 2038 VMULOSH, 2039 VMULOSW, 2040 VMULOUB, 2041 VMULOUD, 2042 VMULOUH, 2043 VMULOUW, 2044 VMULUWM, 2045 VSUM2SWS, 2046 VSUM4SBS, 2047 VSUM4SHS, 2048 VSUM4UBS 2049)>; 2050 2051// 7 Cycles VMX Multiply operations, 3 input operands 2052def : InstRW<[P10W_vMU_7C, P10W_DISP_ANY, P10vMU_Read, P10vMU_Read, P10vMU_Read], 2053 (instrs 2054 VMHADDSHS, 2055 VMHRADDSHS, 2056 VMLADDUHM, 2057 VMSUMCUD, 2058 VMSUMMBM, 2059 VMSUMSHM, 2060 VMSUMSHS, 2061 VMSUMUBM, 2062 VMSUMUDM, 2063 VMSUMUHM, 2064 VMSUMUHS 2065)>; 2066 2067