1 //===-- R600TargetMachine.cpp - TargetMachine for hw codegen targets-------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU-R600 target machine contains all of the hardware specific
11 /// information needed to emit code for R600 GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "R600TargetMachine.h"
16 #include "AMDGPUTargetMachine.h"
17 #include "R600.h"
18 #include "R600CodeGenPassBuilder.h"
19 #include "R600MachineScheduler.h"
20 #include "R600TargetTransformInfo.h"
21 #include "llvm/Transforms/Scalar.h"
22 #include <optional>
23
24 using namespace llvm;
25
26 static cl::opt<bool>
27 EnableR600StructurizeCFG("r600-ir-structurize",
28 cl::desc("Use StructurizeCFG IR pass"),
29 cl::init(true));
30
31 static cl::opt<bool> EnableR600IfConvert("r600-if-convert",
32 cl::desc("Use if conversion pass"),
33 cl::ReallyHidden, cl::init(true));
34
35 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
36 "amdgpu-function-calls", cl::desc("Enable AMDGPU function call support"),
37 cl::location(AMDGPUTargetMachine::EnableFunctionCalls), cl::init(true),
38 cl::Hidden);
39
createR600MachineScheduler(MachineSchedContext * C)40 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
41 return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
42 }
43
44 static MachineSchedRegistry R600SchedRegistry("r600",
45 "Run R600's custom scheduler",
46 createR600MachineScheduler);
47
48 //===----------------------------------------------------------------------===//
49 // R600 Target Machine (R600 -> Cayman)
50 //===----------------------------------------------------------------------===//
51
R600TargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT)52 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
53 StringRef CPU, StringRef FS,
54 const TargetOptions &Options,
55 std::optional<Reloc::Model> RM,
56 std::optional<CodeModel::Model> CM,
57 CodeGenOptLevel OL, bool JIT)
58 : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
59 setRequiresStructuredCFG(true);
60
61 // Override the default since calls aren't supported for r600.
62 if (EnableFunctionCalls &&
63 EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
64 EnableFunctionCalls = false;
65 }
66
67 const TargetSubtargetInfo *
getSubtargetImpl(const Function & F) const68 R600TargetMachine::getSubtargetImpl(const Function &F) const {
69 StringRef GPU = getGPUName(F);
70 StringRef FS = getFeatureString(F);
71
72 SmallString<128> SubtargetKey(GPU);
73 SubtargetKey.append(FS);
74
75 auto &I = SubtargetMap[SubtargetKey];
76 if (!I) {
77 // This needs to be done before we create a new subtarget since any
78 // creation will depend on the TM and the code generation flags on the
79 // function that reside in TargetOptions.
80 resetTargetOptions(F);
81 I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
82 }
83
84 return I.get();
85 }
86
87 TargetTransformInfo
getTargetTransformInfo(const Function & F) const88 R600TargetMachine::getTargetTransformInfo(const Function &F) const {
89 return TargetTransformInfo(R600TTIImpl(this, F));
90 }
91
92 namespace {
93 class R600PassConfig final : public AMDGPUPassConfig {
94 public:
R600PassConfig(LLVMTargetMachine & TM,PassManagerBase & PM)95 R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
96 : AMDGPUPassConfig(TM, PM) {}
97
98 ScheduleDAGInstrs *
createMachineScheduler(MachineSchedContext * C) const99 createMachineScheduler(MachineSchedContext *C) const override {
100 return createR600MachineScheduler(C);
101 }
102
103 bool addPreISel() override;
104 bool addInstSelector() override;
105 void addPreRegAlloc() override;
106 void addPreSched2() override;
107 void addPreEmitPass() override;
108 };
109 } // namespace
110
111 //===----------------------------------------------------------------------===//
112 // R600 Pass Setup
113 //===----------------------------------------------------------------------===//
114
addPreISel()115 bool R600PassConfig::addPreISel() {
116 AMDGPUPassConfig::addPreISel();
117
118 if (EnableR600StructurizeCFG)
119 addPass(createStructurizeCFGPass());
120 return false;
121 }
122
addInstSelector()123 bool R600PassConfig::addInstSelector() {
124 addPass(createR600ISelDag(getAMDGPUTargetMachine(), getOptLevel()));
125 return false;
126 }
127
addPreRegAlloc()128 void R600PassConfig::addPreRegAlloc() { addPass(createR600VectorRegMerger()); }
129
addPreSched2()130 void R600PassConfig::addPreSched2() {
131 addPass(createR600EmitClauseMarkers());
132 if (EnableR600IfConvert)
133 addPass(&IfConverterID);
134 addPass(createR600ClauseMergePass());
135 }
136
addPreEmitPass()137 void R600PassConfig::addPreEmitPass() {
138 addPass(createR600MachineCFGStructurizerPass());
139 addPass(createR600ExpandSpecialInstrsPass());
140 addPass(&FinalizeMachineBundlesID);
141 addPass(createR600Packetizer());
142 addPass(createR600ControlFlowFinalizer());
143 }
144
createPassConfig(PassManagerBase & PM)145 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
146 return new R600PassConfig(*this, PM);
147 }
148
buildCodeGenPipeline(ModulePassManager & MPM,raw_pwrite_stream & Out,raw_pwrite_stream * DwoOut,CodeGenFileType FileType,const CGPassBuilderOption & Opts,PassInstrumentationCallbacks * PIC)149 Error R600TargetMachine::buildCodeGenPipeline(
150 ModulePassManager &MPM, raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
151 CodeGenFileType FileType, const CGPassBuilderOption &Opts,
152 PassInstrumentationCallbacks *PIC) {
153 R600CodeGenPassBuilder CGPB(*this, Opts, PIC);
154 return CGPB.buildPipeline(MPM, Out, DwoOut, FileType);
155 }
156