1//===- AArch64SystemOperands.td ----------------------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the symbolic operands permitted for various kinds of 10// AArch64 system instruction. 11// 12//===----------------------------------------------------------------------===// 13 14include "llvm/TableGen/SearchableTable.td" 15 16//===----------------------------------------------------------------------===// 17// Features that, for the compiler, only enable system operands and PStates 18//===----------------------------------------------------------------------===// 19 20def HasCCPP : Predicate<"Subtarget->hasCCPP()">, 21 AssemblerPredicateWithAll<(all_of FeatureCCPP), "ccpp">; 22 23def HasPAN : Predicate<"Subtarget->hasPAN()">, 24 AssemblerPredicateWithAll<(all_of FeaturePAN), 25 "ARM v8.1 Privileged Access-Never extension">; 26 27def HasPsUAO : Predicate<"Subtarget->hasPsUAO()">, 28 AssemblerPredicateWithAll<(all_of FeaturePsUAO), 29 "ARM v8.2 UAO PState extension (psuao)">; 30 31def HasPAN_RWV : Predicate<"Subtarget->hasPAN_RWV()">, 32 AssemblerPredicateWithAll<(all_of FeaturePAN_RWV), 33 "ARM v8.2 PAN AT S1E1R and AT S1E1W Variation">; 34 35def HasCONTEXTIDREL2 36 : Predicate<"Subtarget->hasCONTEXTIDREL2()">, 37 AssemblerPredicateWithAll<(all_of FeatureCONTEXTIDREL2), 38 "Target contains CONTEXTIDR_EL2 RW operand">; 39 40//===----------------------------------------------------------------------===// 41// AT (address translate) instruction options. 42//===----------------------------------------------------------------------===// 43 44class AT<string name, bits<3> op1, bits<4> crn, bits<4> crm, 45 bits<3> op2> : SearchableTable { 46 let SearchableFields = ["Name", "Encoding"]; 47 let EnumValueField = "Encoding"; 48 49 string Name = name; 50 bits<14> Encoding; 51 let Encoding{13-11} = op1; 52 let Encoding{10-7} = crn; 53 let Encoding{6-3} = crm; 54 let Encoding{2-0} = op2; 55 code Requires = [{ {} }]; 56} 57 58def : AT<"S1E1R", 0b000, 0b0111, 0b1000, 0b000>; 59def : AT<"S1E2R", 0b100, 0b0111, 0b1000, 0b000>; 60def : AT<"S1E3R", 0b110, 0b0111, 0b1000, 0b000>; 61def : AT<"S1E1W", 0b000, 0b0111, 0b1000, 0b001>; 62def : AT<"S1E2W", 0b100, 0b0111, 0b1000, 0b001>; 63def : AT<"S1E3W", 0b110, 0b0111, 0b1000, 0b001>; 64def : AT<"S1E0R", 0b000, 0b0111, 0b1000, 0b010>; 65def : AT<"S1E0W", 0b000, 0b0111, 0b1000, 0b011>; 66def : AT<"S12E1R", 0b100, 0b0111, 0b1000, 0b100>; 67def : AT<"S12E1W", 0b100, 0b0111, 0b1000, 0b101>; 68def : AT<"S12E0R", 0b100, 0b0111, 0b1000, 0b110>; 69def : AT<"S12E0W", 0b100, 0b0111, 0b1000, 0b111>; 70 71let Requires = [{ {AArch64::FeaturePAN_RWV} }] in { 72def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>; 73def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>; 74} 75 76//===----------------------------------------------------------------------===// 77// DMB/DSB (data barrier) instruction options. 78//===----------------------------------------------------------------------===// 79 80class DB<string name, bits<4> encoding> : SearchableTable { 81 let SearchableFields = ["Name", "Encoding"]; 82 let EnumValueField = "Encoding"; 83 84 string Name = name; 85 bits<4> Encoding = encoding; 86} 87 88def : DB<"oshld", 0x1>; 89def : DB<"oshst", 0x2>; 90def : DB<"osh", 0x3>; 91def : DB<"nshld", 0x5>; 92def : DB<"nshst", 0x6>; 93def : DB<"nsh", 0x7>; 94def : DB<"ishld", 0x9>; 95def : DB<"ishst", 0xa>; 96def : DB<"ish", 0xb>; 97def : DB<"ld", 0xd>; 98def : DB<"st", 0xe>; 99def : DB<"sy", 0xf>; 100 101class DBnXS<string name, bits<4> encoding, bits<5> immValue> : SearchableTable { 102 let SearchableFields = ["Name", "Encoding", "ImmValue"]; 103 let EnumValueField = "Encoding"; 104 105 string Name = name; 106 bits<4> Encoding = encoding; 107 bits<5> ImmValue = immValue; 108 code Requires = [{ {AArch64::FeatureXS} }]; 109} 110 111def : DBnXS<"oshnxs", 0x3, 0x10>; 112def : DBnXS<"nshnxs", 0x7, 0x14>; 113def : DBnXS<"ishnxs", 0xb, 0x18>; 114def : DBnXS<"synxs", 0xf, 0x1c>; 115 116//===----------------------------------------------------------------------===// 117// DC (data cache maintenance) instruction options. 118//===----------------------------------------------------------------------===// 119 120class DC<string name, bits<3> op1, bits<4> crn, bits<4> crm, 121 bits<3> op2> : SearchableTable { 122 let SearchableFields = ["Name", "Encoding"]; 123 let EnumValueField = "Encoding"; 124 125 string Name = name; 126 bits<14> Encoding; 127 let Encoding{13-11} = op1; 128 let Encoding{10-7} = crn; 129 let Encoding{6-3} = crm; 130 let Encoding{2-0} = op2; 131 code Requires = [{ {} }]; 132} 133 134def : DC<"ZVA", 0b011, 0b0111, 0b0100, 0b001>; 135def : DC<"IVAC", 0b000, 0b0111, 0b0110, 0b001>; 136def : DC<"ISW", 0b000, 0b0111, 0b0110, 0b010>; 137def : DC<"CVAC", 0b011, 0b0111, 0b1010, 0b001>; 138def : DC<"CSW", 0b000, 0b0111, 0b1010, 0b010>; 139def : DC<"CVAU", 0b011, 0b0111, 0b1011, 0b001>; 140def : DC<"CIVAC", 0b011, 0b0111, 0b1110, 0b001>; 141def : DC<"CISW", 0b000, 0b0111, 0b1110, 0b010>; 142 143let Requires = [{ {AArch64::FeatureCCPP} }] in 144def : DC<"CVAP", 0b011, 0b0111, 0b1100, 0b001>; 145 146let Requires = [{ {AArch64::FeatureCacheDeepPersist} }] in 147def : DC<"CVADP", 0b011, 0b0111, 0b1101, 0b001>; 148 149let Requires = [{ {AArch64::FeatureMTE} }] in { 150def : DC<"IGVAC", 0b000, 0b0111, 0b0110, 0b011>; 151def : DC<"IGSW", 0b000, 0b0111, 0b0110, 0b100>; 152def : DC<"CGSW", 0b000, 0b0111, 0b1010, 0b100>; 153def : DC<"CIGSW", 0b000, 0b0111, 0b1110, 0b100>; 154def : DC<"CGVAC", 0b011, 0b0111, 0b1010, 0b011>; 155def : DC<"CGVAP", 0b011, 0b0111, 0b1100, 0b011>; 156def : DC<"CGVADP", 0b011, 0b0111, 0b1101, 0b011>; 157def : DC<"CIGVAC", 0b011, 0b0111, 0b1110, 0b011>; 158def : DC<"GVA", 0b011, 0b0111, 0b0100, 0b011>; 159def : DC<"IGDVAC", 0b000, 0b0111, 0b0110, 0b101>; 160def : DC<"IGDSW", 0b000, 0b0111, 0b0110, 0b110>; 161def : DC<"CGDSW", 0b000, 0b0111, 0b1010, 0b110>; 162def : DC<"CIGDSW", 0b000, 0b0111, 0b1110, 0b110>; 163def : DC<"CGDVAC", 0b011, 0b0111, 0b1010, 0b101>; 164def : DC<"CGDVAP", 0b011, 0b0111, 0b1100, 0b101>; 165def : DC<"CGDVADP", 0b011, 0b0111, 0b1101, 0b101>; 166def : DC<"CIGDVAC", 0b011, 0b0111, 0b1110, 0b101>; 167def : DC<"GZVA", 0b011, 0b0111, 0b0100, 0b100>; 168} 169 170let Requires = [{ {AArch64::FeatureMEC} }] in { 171def : DC<"CIPAE", 0b100, 0b0111, 0b1110, 0b000>; 172def : DC<"CIGDPAE", 0b100, 0b0111, 0b1110, 0b111>; 173} 174 175//===----------------------------------------------------------------------===// 176// IC (instruction cache maintenance) instruction options. 177//===----------------------------------------------------------------------===// 178 179class IC<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2, 180 bit needsreg> : SearchableTable { 181 let SearchableFields = ["Name", "Encoding"]; 182 let EnumValueField = "Encoding"; 183 184 string Name = name; 185 bits<14> Encoding; 186 let Encoding{13-11} = op1; 187 let Encoding{10-7} = crn; 188 let Encoding{6-3} = crm; 189 let Encoding{2-0} = op2; 190 bit NeedsReg = needsreg; 191} 192 193def : IC<"IALLUIS", 0b000, 0b0111, 0b0001, 0b000, 0>; 194def : IC<"IALLU", 0b000, 0b0111, 0b0101, 0b000, 0>; 195def : IC<"IVAU", 0b011, 0b0111, 0b0101, 0b001, 1>; 196 197//===----------------------------------------------------------------------===// 198// ISB (instruction-fetch barrier) instruction options. 199//===----------------------------------------------------------------------===// 200 201class ISB<string name, bits<4> encoding> : SearchableTable{ 202 let SearchableFields = ["Name", "Encoding"]; 203 let EnumValueField = "Encoding"; 204 205 string Name = name; 206 bits<4> Encoding; 207 let Encoding = encoding; 208} 209 210def : ISB<"sy", 0xf>; 211 212//===----------------------------------------------------------------------===// 213// TSB (Trace synchronization barrier) instruction options. 214//===----------------------------------------------------------------------===// 215 216class TSB<string name, bits<4> encoding> : SearchableTable{ 217 let SearchableFields = ["Name", "Encoding"]; 218 let EnumValueField = "Encoding"; 219 220 string Name = name; 221 bits<4> Encoding; 222 let Encoding = encoding; 223 224 code Requires = [{ {AArch64::FeatureTRACEV8_4} }]; 225} 226 227def : TSB<"csync", 0>; 228 229//===----------------------------------------------------------------------===// 230// PRFM (prefetch) instruction options. 231//===----------------------------------------------------------------------===// 232 233class PRFM<string type, bits<2> type_encoding, 234 string target, bits<2> target_encoding, 235 string policy, bits<1> policy_encoding> : SearchableTable { 236 let SearchableFields = ["Name", "Encoding"]; 237 let EnumValueField = "Encoding"; 238 239 string Name = type # target # policy; 240 bits<5> Encoding; 241 let Encoding{4-3} = type_encoding; 242 let Encoding{2-1} = target_encoding; 243 let Encoding{0} = policy_encoding; 244 245 code Requires = [{ {} }]; 246} 247 248def : PRFM<"pld", 0b00, "l1", 0b00, "keep", 0b0>; 249def : PRFM<"pld", 0b00, "l1", 0b00, "strm", 0b1>; 250def : PRFM<"pld", 0b00, "l2", 0b01, "keep", 0b0>; 251def : PRFM<"pld", 0b00, "l2", 0b01, "strm", 0b1>; 252def : PRFM<"pld", 0b00, "l3", 0b10, "keep", 0b0>; 253def : PRFM<"pld", 0b00, "l3", 0b10, "strm", 0b1>; 254let Requires = [{ {AArch64::FeaturePRFM_SLC} }] in { 255def : PRFM<"pld", 0b00, "slc", 0b11, "keep", 0b0>; 256def : PRFM<"pld", 0b00, "slc", 0b11, "strm", 0b1>; 257} 258def : PRFM<"pli", 0b01, "l1", 0b00, "keep", 0b0>; 259def : PRFM<"pli", 0b01, "l1", 0b00, "strm", 0b1>; 260def : PRFM<"pli", 0b01, "l2", 0b01, "keep", 0b0>; 261def : PRFM<"pli", 0b01, "l2", 0b01, "strm", 0b1>; 262def : PRFM<"pli", 0b01, "l3", 0b10, "keep", 0b0>; 263def : PRFM<"pli", 0b01, "l3", 0b10, "strm", 0b1>; 264let Requires = [{ {AArch64::FeaturePRFM_SLC} }] in { 265def : PRFM<"pli", 0b01, "slc", 0b11, "keep", 0b0>; 266def : PRFM<"pli", 0b01, "slc", 0b11, "strm", 0b1>; 267} 268def : PRFM<"pst", 0b10, "l1", 0b00, "keep", 0b0>; 269def : PRFM<"pst", 0b10, "l1", 0b00, "strm", 0b1>; 270def : PRFM<"pst", 0b10, "l2", 0b01, "keep", 0b0>; 271def : PRFM<"pst", 0b10, "l2", 0b01, "strm", 0b1>; 272def : PRFM<"pst", 0b10, "l3", 0b10, "keep", 0b0>; 273def : PRFM<"pst", 0b10, "l3", 0b10, "strm", 0b1>; 274let Requires = [{ {AArch64::FeaturePRFM_SLC} }] in { 275def : PRFM<"pst", 0b10, "slc", 0b11, "keep", 0b0>; 276def : PRFM<"pst", 0b10, "slc", 0b11, "strm", 0b1>; 277} 278 279//===----------------------------------------------------------------------===// 280// SVE Prefetch instruction options. 281//===----------------------------------------------------------------------===// 282 283class SVEPRFM<string name, bits<4> encoding> : SearchableTable { 284 let SearchableFields = ["Name", "Encoding"]; 285 let EnumValueField = "Encoding"; 286 287 string Name = name; 288 bits<4> Encoding; 289 let Encoding = encoding; 290 code Requires = [{ {} }]; 291} 292 293let Requires = [{ {AArch64::FeatureSVE} }] in { 294def : SVEPRFM<"pldl1keep", 0x00>; 295def : SVEPRFM<"pldl1strm", 0x01>; 296def : SVEPRFM<"pldl2keep", 0x02>; 297def : SVEPRFM<"pldl2strm", 0x03>; 298def : SVEPRFM<"pldl3keep", 0x04>; 299def : SVEPRFM<"pldl3strm", 0x05>; 300def : SVEPRFM<"pstl1keep", 0x08>; 301def : SVEPRFM<"pstl1strm", 0x09>; 302def : SVEPRFM<"pstl2keep", 0x0a>; 303def : SVEPRFM<"pstl2strm", 0x0b>; 304def : SVEPRFM<"pstl3keep", 0x0c>; 305def : SVEPRFM<"pstl3strm", 0x0d>; 306} 307 308//===----------------------------------------------------------------------===// 309// RPRFM (prefetch) instruction options. 310//===----------------------------------------------------------------------===// 311 312class RPRFM<string name, bits<1> type_encoding, bits<5> policy_encoding> : SearchableTable { 313 let SearchableFields = ["Name", "Encoding"]; 314 let EnumValueField = "Encoding"; 315 316 string Name = name; 317 bits<6> Encoding; 318 let Encoding{0} = type_encoding; 319 let Encoding{5-1} = policy_encoding; 320 code Requires = [{ {} }]; 321} 322 323def : RPRFM<"pldkeep", 0b0, 0b00000>; 324def : RPRFM<"pstkeep", 0b1, 0b00000>; 325def : RPRFM<"pldstrm", 0b0, 0b00010>; 326def : RPRFM<"pststrm", 0b1, 0b00010>; 327 328//===----------------------------------------------------------------------===// 329// SVE Predicate patterns 330//===----------------------------------------------------------------------===// 331 332class SVEPREDPAT<string name, bits<5> encoding> : SearchableTable { 333 let SearchableFields = ["Name", "Encoding"]; 334 let EnumValueField = "Encoding"; 335 336 string Name = name; 337 bits<5> Encoding; 338 let Encoding = encoding; 339} 340 341def : SVEPREDPAT<"pow2", 0x00>; 342def : SVEPREDPAT<"vl1", 0x01>; 343def : SVEPREDPAT<"vl2", 0x02>; 344def : SVEPREDPAT<"vl3", 0x03>; 345def : SVEPREDPAT<"vl4", 0x04>; 346def : SVEPREDPAT<"vl5", 0x05>; 347def : SVEPREDPAT<"vl6", 0x06>; 348def : SVEPREDPAT<"vl7", 0x07>; 349def : SVEPREDPAT<"vl8", 0x08>; 350def : SVEPREDPAT<"vl16", 0x09>; 351def : SVEPREDPAT<"vl32", 0x0a>; 352def : SVEPREDPAT<"vl64", 0x0b>; 353def : SVEPREDPAT<"vl128", 0x0c>; 354def : SVEPREDPAT<"vl256", 0x0d>; 355def : SVEPREDPAT<"mul4", 0x1d>; 356def : SVEPREDPAT<"mul3", 0x1e>; 357def : SVEPREDPAT<"all", 0x1f>; 358 359//===----------------------------------------------------------------------===// 360// SVE Predicate-as-counter patterns 361//===----------------------------------------------------------------------===// 362 363class SVEVECLENSPECIFIER<string name, bits<1> encoding> : SearchableTable { 364 let SearchableFields = ["Name", "Encoding"]; 365 let EnumValueField = "Encoding"; 366 367 string Name = name; 368 bits<1> Encoding; 369 let Encoding = encoding; 370} 371 372def : SVEVECLENSPECIFIER<"vlx2", 0x0>; 373def : SVEVECLENSPECIFIER<"vlx4", 0x1>; 374 375//===----------------------------------------------------------------------===// 376// Exact FP Immediates. 377// 378// These definitions are used to create a lookup table with FP Immediates that 379// is used for a few instructions that only accept a limited set of exact FP 380// immediates values. 381//===----------------------------------------------------------------------===// 382class ExactFPImm<string name, string repr, bits<4> enum > : SearchableTable { 383 let SearchableFields = ["Enum", "Repr"]; 384 let EnumValueField = "Enum"; 385 386 string Name = name; 387 bits<4> Enum = enum; 388 string Repr = repr; 389} 390 391def : ExactFPImm<"zero", "0.0", 0x0>; 392def : ExactFPImm<"half", "0.5", 0x1>; 393def : ExactFPImm<"one", "1.0", 0x2>; 394def : ExactFPImm<"two", "2.0", 0x3>; 395 396//===----------------------------------------------------------------------===// 397// PState instruction options. 398//===----------------------------------------------------------------------===// 399 400class PStateImm0_15<string name, bits<3> op1, bits<3> op2> : SearchableTable { 401 let SearchableFields = ["Name", "Encoding"]; 402 let EnumValueField = "Encoding"; 403 404 string Name = name; 405 bits<6> Encoding; 406 let Encoding{5-3} = op1; 407 let Encoding{2-0} = op2; 408 code Requires = [{ {} }]; 409} 410 411class PStateImm0_1<string name, bits<3> op1, bits<3> op2, bits<3> crm_high> : SearchableTable { 412 let SearchableFields = ["Name", "Encoding"]; 413 let EnumValueField = "Encoding"; 414 415 string Name = name; 416 bits<9> Encoding; 417 let Encoding{8-6} = crm_high; 418 let Encoding{5-3} = op1; 419 let Encoding{2-0} = op2; 420 code Requires = [{ {} }]; 421} 422 423// Name, Op1, Op2 424def : PStateImm0_15<"SPSel", 0b000, 0b101>; 425def : PStateImm0_15<"DAIFSet", 0b011, 0b110>; 426def : PStateImm0_15<"DAIFClr", 0b011, 0b111>; 427// v8.1a "Privileged Access Never" extension-specific PStates 428let Requires = [{ {AArch64::FeaturePAN} }] in 429def : PStateImm0_15<"PAN", 0b000, 0b100>; 430 431// v8.2a "User Access Override" extension-specific PStates 432let Requires = [{ {AArch64::FeaturePsUAO} }] in 433def : PStateImm0_15<"UAO", 0b000, 0b011>; 434// v8.4a timing insensitivity of data processing instructions 435let Requires = [{ {AArch64::FeatureDIT} }] in 436def : PStateImm0_15<"DIT", 0b011, 0b010>; 437// v8.5a Spectre Mitigation 438let Requires = [{ {AArch64::FeatureSSBS} }] in 439def : PStateImm0_15<"SSBS", 0b011, 0b001>; 440// v8.5a Memory Tagging Extension 441let Requires = [{ {AArch64::FeatureMTE} }] in 442def : PStateImm0_15<"TCO", 0b011, 0b100>; 443// v8.8a Non-Maskable Interrupts 444let Requires = [{ {AArch64::FeatureNMI} }] in 445def : PStateImm0_1<"ALLINT", 0b001, 0b000, 0b000>; 446// v9.4a Exception-based event profiling 447// Name, Op1, Op2, Crm_high 448def : PStateImm0_1<"PM", 0b001, 0b000, 0b001>; 449 450//===----------------------------------------------------------------------===// 451// SVCR instruction options. 452//===----------------------------------------------------------------------===// 453 454class SVCR<string name, bits<3> encoding> : SearchableTable { 455 let SearchableFields = ["Name", "Encoding"]; 456 let EnumValueField = "Encoding"; 457 458 string Name = name; 459 bits<3> Encoding; 460 let Encoding = encoding; 461 code Requires = [{ {} }]; 462} 463 464let Requires = [{ {AArch64::FeatureSME} }] in { 465def : SVCR<"SVCRSM", 0b001>; 466def : SVCR<"SVCRZA", 0b010>; 467def : SVCR<"SVCRSMZA", 0b011>; 468} 469 470//===----------------------------------------------------------------------===// 471// PSB instruction options. 472//===----------------------------------------------------------------------===// 473 474class PSB<string name, bits<5> encoding> : SearchableTable { 475 let SearchableFields = ["Name", "Encoding"]; 476 let EnumValueField = "Encoding"; 477 478 string Name = name; 479 bits<5> Encoding; 480 let Encoding = encoding; 481} 482 483def : PSB<"csync", 0x11>; 484 485//===----------------------------------------------------------------------===// 486// BTI instruction options. 487//===----------------------------------------------------------------------===// 488 489class BTI<string name, bits<3> encoding> : SearchableTable { 490 let SearchableFields = ["Name", "Encoding"]; 491 let EnumValueField = "Encoding"; 492 493 string Name = name; 494 bits<3> Encoding; 495 let Encoding = encoding; 496} 497 498def : BTI<"c", 0b010>; 499def : BTI<"j", 0b100>; 500def : BTI<"jc", 0b110>; 501 502//===----------------------------------------------------------------------===// 503// TLBI (translation lookaside buffer invalidate) instruction options. 504//===----------------------------------------------------------------------===// 505 506class TLBIEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm, 507 bits<3> op2, bit needsreg> { 508 string Name = name; 509 bits<14> Encoding; 510 let Encoding{13-11} = op1; 511 let Encoding{10-7} = crn; 512 let Encoding{6-3} = crm; 513 let Encoding{2-0} = op2; 514 bit NeedsReg = needsreg; 515 list<string> Requires = []; 516 list<string> ExtraRequires = []; 517 code RequiresStr = [{ { }] # !interleave(Requires # ExtraRequires, [{, }]) # [{ } }]; 518} 519 520def TLBITable : GenericTable { 521 let FilterClass = "TLBIEntry"; 522 let CppTypeName = "TLBI"; 523 let Fields = ["Name", "Encoding", "NeedsReg", "RequiresStr"]; 524} 525 526def lookupTLBIByName : SearchIndex { 527 let Table = TLBITable; 528 let Key = ["Name"]; 529} 530 531def lookupTLBIByEncoding : SearchIndex { 532 let Table = TLBITable; 533 let Key = ["Encoding"]; 534} 535 536multiclass TLBI<string name, bits<3> op1, bits<4> crn, bits<4> crm, 537 bits<3> op2, bit needsreg = 1> { 538 def : TLBIEntry<name, op1, crn, crm, op2, needsreg>; 539 def : TLBIEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, needsreg> { 540 let Encoding{7} = 1; 541 let ExtraRequires = ["AArch64::FeatureXS"]; 542 } 543} 544 545defm : TLBI<"IPAS2E1IS", 0b100, 0b1000, 0b0000, 0b001>; 546defm : TLBI<"IPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b101>; 547defm : TLBI<"VMALLE1IS", 0b000, 0b1000, 0b0011, 0b000, 0>; 548defm : TLBI<"ALLE2IS", 0b100, 0b1000, 0b0011, 0b000, 0>; 549defm : TLBI<"ALLE3IS", 0b110, 0b1000, 0b0011, 0b000, 0>; 550defm : TLBI<"VAE1IS", 0b000, 0b1000, 0b0011, 0b001>; 551defm : TLBI<"VAE2IS", 0b100, 0b1000, 0b0011, 0b001>; 552defm : TLBI<"VAE3IS", 0b110, 0b1000, 0b0011, 0b001>; 553defm : TLBI<"ASIDE1IS", 0b000, 0b1000, 0b0011, 0b010>; 554defm : TLBI<"VAAE1IS", 0b000, 0b1000, 0b0011, 0b011>; 555defm : TLBI<"ALLE1IS", 0b100, 0b1000, 0b0011, 0b100, 0>; 556defm : TLBI<"VALE1IS", 0b000, 0b1000, 0b0011, 0b101>; 557defm : TLBI<"VALE2IS", 0b100, 0b1000, 0b0011, 0b101>; 558defm : TLBI<"VALE3IS", 0b110, 0b1000, 0b0011, 0b101>; 559defm : TLBI<"VMALLS12E1IS", 0b100, 0b1000, 0b0011, 0b110, 0>; 560defm : TLBI<"VAALE1IS", 0b000, 0b1000, 0b0011, 0b111>; 561defm : TLBI<"IPAS2E1", 0b100, 0b1000, 0b0100, 0b001>; 562defm : TLBI<"IPAS2LE1", 0b100, 0b1000, 0b0100, 0b101>; 563defm : TLBI<"VMALLE1", 0b000, 0b1000, 0b0111, 0b000, 0>; 564defm : TLBI<"ALLE2", 0b100, 0b1000, 0b0111, 0b000, 0>; 565defm : TLBI<"ALLE3", 0b110, 0b1000, 0b0111, 0b000, 0>; 566defm : TLBI<"VAE1", 0b000, 0b1000, 0b0111, 0b001>; 567defm : TLBI<"VAE2", 0b100, 0b1000, 0b0111, 0b001>; 568defm : TLBI<"VAE3", 0b110, 0b1000, 0b0111, 0b001>; 569defm : TLBI<"ASIDE1", 0b000, 0b1000, 0b0111, 0b010>; 570defm : TLBI<"VAAE1", 0b000, 0b1000, 0b0111, 0b011>; 571defm : TLBI<"ALLE1", 0b100, 0b1000, 0b0111, 0b100, 0>; 572defm : TLBI<"VALE1", 0b000, 0b1000, 0b0111, 0b101>; 573defm : TLBI<"VALE2", 0b100, 0b1000, 0b0111, 0b101>; 574defm : TLBI<"VALE3", 0b110, 0b1000, 0b0111, 0b101>; 575defm : TLBI<"VMALLS12E1", 0b100, 0b1000, 0b0111, 0b110, 0>; 576defm : TLBI<"VAALE1", 0b000, 0b1000, 0b0111, 0b111>; 577 578// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI) 579let Requires = ["AArch64::FeatureTLB_RMI"] in { 580// Armv8.4-A Outer Sharable TLB Maintenance instructions: 581// op1 CRn CRm op2 582defm : TLBI<"VMALLE1OS", 0b000, 0b1000, 0b0001, 0b000, 0>; 583defm : TLBI<"VAE1OS", 0b000, 0b1000, 0b0001, 0b001>; 584defm : TLBI<"ASIDE1OS", 0b000, 0b1000, 0b0001, 0b010>; 585defm : TLBI<"VAAE1OS", 0b000, 0b1000, 0b0001, 0b011>; 586defm : TLBI<"VALE1OS", 0b000, 0b1000, 0b0001, 0b101>; 587defm : TLBI<"VAALE1OS", 0b000, 0b1000, 0b0001, 0b111>; 588defm : TLBI<"IPAS2E1OS", 0b100, 0b1000, 0b0100, 0b000>; 589defm : TLBI<"IPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b100>; 590defm : TLBI<"VAE2OS", 0b100, 0b1000, 0b0001, 0b001>; 591defm : TLBI<"VALE2OS", 0b100, 0b1000, 0b0001, 0b101>; 592defm : TLBI<"VMALLS12E1OS", 0b100, 0b1000, 0b0001, 0b110, 0>; 593defm : TLBI<"VAE3OS", 0b110, 0b1000, 0b0001, 0b001>; 594defm : TLBI<"VALE3OS", 0b110, 0b1000, 0b0001, 0b101>; 595defm : TLBI<"ALLE2OS", 0b100, 0b1000, 0b0001, 0b000, 0>; 596defm : TLBI<"ALLE1OS", 0b100, 0b1000, 0b0001, 0b100, 0>; 597defm : TLBI<"ALLE3OS", 0b110, 0b1000, 0b0001, 0b000, 0>; 598 599// Armv8.4-A TLB Range Maintenance instructions: 600// op1 CRn CRm op2 601defm : TLBI<"RVAE1", 0b000, 0b1000, 0b0110, 0b001>; 602defm : TLBI<"RVAAE1", 0b000, 0b1000, 0b0110, 0b011>; 603defm : TLBI<"RVALE1", 0b000, 0b1000, 0b0110, 0b101>; 604defm : TLBI<"RVAALE1", 0b000, 0b1000, 0b0110, 0b111>; 605defm : TLBI<"RVAE1IS", 0b000, 0b1000, 0b0010, 0b001>; 606defm : TLBI<"RVAAE1IS", 0b000, 0b1000, 0b0010, 0b011>; 607defm : TLBI<"RVALE1IS", 0b000, 0b1000, 0b0010, 0b101>; 608defm : TLBI<"RVAALE1IS", 0b000, 0b1000, 0b0010, 0b111>; 609defm : TLBI<"RVAE1OS", 0b000, 0b1000, 0b0101, 0b001>; 610defm : TLBI<"RVAAE1OS", 0b000, 0b1000, 0b0101, 0b011>; 611defm : TLBI<"RVALE1OS", 0b000, 0b1000, 0b0101, 0b101>; 612defm : TLBI<"RVAALE1OS", 0b000, 0b1000, 0b0101, 0b111>; 613defm : TLBI<"RIPAS2E1IS", 0b100, 0b1000, 0b0000, 0b010>; 614defm : TLBI<"RIPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b110>; 615defm : TLBI<"RIPAS2E1", 0b100, 0b1000, 0b0100, 0b010>; 616defm : TLBI<"RIPAS2LE1", 0b100, 0b1000, 0b0100, 0b110>; 617defm : TLBI<"RIPAS2E1OS", 0b100, 0b1000, 0b0100, 0b011>; 618defm : TLBI<"RIPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b111>; 619defm : TLBI<"RVAE2", 0b100, 0b1000, 0b0110, 0b001>; 620defm : TLBI<"RVALE2", 0b100, 0b1000, 0b0110, 0b101>; 621defm : TLBI<"RVAE2IS", 0b100, 0b1000, 0b0010, 0b001>; 622defm : TLBI<"RVALE2IS", 0b100, 0b1000, 0b0010, 0b101>; 623defm : TLBI<"RVAE2OS", 0b100, 0b1000, 0b0101, 0b001>; 624defm : TLBI<"RVALE2OS", 0b100, 0b1000, 0b0101, 0b101>; 625defm : TLBI<"RVAE3", 0b110, 0b1000, 0b0110, 0b001>; 626defm : TLBI<"RVALE3", 0b110, 0b1000, 0b0110, 0b101>; 627defm : TLBI<"RVAE3IS", 0b110, 0b1000, 0b0010, 0b001>; 628defm : TLBI<"RVALE3IS", 0b110, 0b1000, 0b0010, 0b101>; 629defm : TLBI<"RVAE3OS", 0b110, 0b1000, 0b0101, 0b001>; 630defm : TLBI<"RVALE3OS", 0b110, 0b1000, 0b0101, 0b101>; 631} //FeatureTLB_RMI 632 633// Armv9-A Realm Management Extention TLBI Instructions 634let Requires = ["AArch64::FeatureRME"] in { 635defm : TLBI<"RPAOS", 0b110, 0b1000, 0b0100, 0b011>; 636defm : TLBI<"RPALOS", 0b110, 0b1000, 0b0100, 0b111>; 637defm : TLBI<"PAALLOS", 0b110, 0b1000, 0b0001, 0b100, 0>; 638defm : TLBI<"PAALL", 0b110, 0b1000, 0b0111, 0b100, 0>; 639} 640 641//===----------------------------------------------------------------------===// 642// MRS/MSR (system register read/write) instruction options. 643//===----------------------------------------------------------------------===// 644 645class SysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm, 646 bits<3> op2> : SearchableTable { 647 let SearchableFields = ["Name", "Encoding"]; 648 let EnumValueField = "Encoding"; 649 650 string Name = name; 651 string AltName = name; 652 bits<16> Encoding; 653 let Encoding{15-14} = op0; 654 let Encoding{13-11} = op1; 655 let Encoding{10-7} = crn; 656 let Encoding{6-3} = crm; 657 let Encoding{2-0} = op2; 658 bit Readable = ?; 659 bit Writeable = ?; 660 code Requires = [{ {} }]; 661} 662 663class RWSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm, 664 bits<3> op2> 665 : SysReg<name, op0, op1, crn, crm, op2> { 666 let Readable = 1; 667 let Writeable = 1; 668} 669 670class ROSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm, 671 bits<3> op2> 672 : SysReg<name, op0, op1, crn, crm, op2> { 673 let Readable = 1; 674 let Writeable = 0; 675} 676 677class WOSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm, 678 bits<3> op2> 679 : SysReg<name, op0, op1, crn, crm, op2> { 680 let Readable = 0; 681 let Writeable = 1; 682} 683 684//===---------------------- 685// Read-only regs 686//===---------------------- 687 688// Op0 Op1 CRn CRm Op2 689def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>; 690def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>; 691def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>; 692def : ROSysReg<"OSLSR_EL1", 0b10, 0b000, 0b0001, 0b0001, 0b100>; 693def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b10, 0b000, 0b0111, 0b1110, 0b110>; 694def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>; 695def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>; 696def : ROSysReg<"PMMIR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b110>; 697def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>; 698def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>; 699 700//v8.3 CCIDX - extending the CCsIDr number of sets 701def : ROSysReg<"CCSIDR2_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b010> { 702 let Requires = [{ {AArch64::FeatureCCIDX} }]; 703} 704def : ROSysReg<"CLIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b001>; 705def : ROSysReg<"CTR_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b001>; 706def : ROSysReg<"MPIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b101>; 707def : ROSysReg<"REVIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b110>; 708def : ROSysReg<"AIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b111>; 709def : ROSysReg<"DCZID_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b111>; 710def : ROSysReg<"ID_PFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b000>; 711def : ROSysReg<"ID_PFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b001>; 712def : ROSysReg<"ID_PFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b100> { 713 let Requires = [{ {AArch64::FeatureSpecRestrict} }]; 714} 715def : ROSysReg<"ID_DFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b010>; 716def : ROSysReg<"ID_DFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b101>; 717def : ROSysReg<"ID_AFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b011>; 718def : ROSysReg<"ID_MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b100>; 719def : ROSysReg<"ID_MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b101>; 720def : ROSysReg<"ID_MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b110>; 721def : ROSysReg<"ID_MMFR3_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b111>; 722def : ROSysReg<"ID_ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b000>; 723def : ROSysReg<"ID_ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b001>; 724def : ROSysReg<"ID_ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b010>; 725def : ROSysReg<"ID_ISAR3_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b011>; 726def : ROSysReg<"ID_ISAR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b100>; 727def : ROSysReg<"ID_ISAR5_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b101>; 728def : ROSysReg<"ID_ISAR6_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b111> { 729 let Requires = [{ {AArch64::HasV8_2aOps} }]; 730} 731def : ROSysReg<"ID_AA64PFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b000>; 732def : ROSysReg<"ID_AA64PFR1_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b001>; 733def : ROSysReg<"ID_AA64PFR2_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b010>; 734def : ROSysReg<"ID_AA64DFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b000>; 735def : ROSysReg<"ID_AA64DFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b001>; 736def : ROSysReg<"ID_AA64AFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b100>; 737def : ROSysReg<"ID_AA64AFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b101>; 738def : ROSysReg<"ID_AA64ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b000>; 739def : ROSysReg<"ID_AA64ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b001>; 740def : ROSysReg<"ID_AA64ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b010>; 741def : ROSysReg<"ID_AA64MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b000>; 742def : ROSysReg<"ID_AA64MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b001>; 743def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010>; 744def : ROSysReg<"ID_AA64MMFR3_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b011>; 745def : ROSysReg<"ID_AA64MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b100>; 746def : ROSysReg<"MVFR0_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b000>; 747def : ROSysReg<"MVFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b001>; 748def : ROSysReg<"MVFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b010>; 749def : ROSysReg<"RVBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b001>; 750def : ROSysReg<"RVBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b001>; 751def : ROSysReg<"RVBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b001>; 752def : ROSysReg<"ISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b000>; 753def : ROSysReg<"CNTPCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b001>; 754def : ROSysReg<"CNTVCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b010>; 755def : ROSysReg<"ID_MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b110>; 756def : ROSysReg<"ID_MMFR5_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b110>; 757 758// Trace registers 759// Op0 Op1 CRn CRm Op2 760def : ROSysReg<"TRCSTATR", 0b10, 0b001, 0b0000, 0b0011, 0b000>; 761def : ROSysReg<"TRCIDR8", 0b10, 0b001, 0b0000, 0b0000, 0b110>; 762def : ROSysReg<"TRCIDR9", 0b10, 0b001, 0b0000, 0b0001, 0b110>; 763def : ROSysReg<"TRCIDR10", 0b10, 0b001, 0b0000, 0b0010, 0b110>; 764def : ROSysReg<"TRCIDR11", 0b10, 0b001, 0b0000, 0b0011, 0b110>; 765def : ROSysReg<"TRCIDR12", 0b10, 0b001, 0b0000, 0b0100, 0b110>; 766def : ROSysReg<"TRCIDR13", 0b10, 0b001, 0b0000, 0b0101, 0b110>; 767def : ROSysReg<"TRCIDR0", 0b10, 0b001, 0b0000, 0b1000, 0b111>; 768def : ROSysReg<"TRCIDR1", 0b10, 0b001, 0b0000, 0b1001, 0b111>; 769def : ROSysReg<"TRCIDR2", 0b10, 0b001, 0b0000, 0b1010, 0b111>; 770def : ROSysReg<"TRCIDR3", 0b10, 0b001, 0b0000, 0b1011, 0b111>; 771def : ROSysReg<"TRCIDR4", 0b10, 0b001, 0b0000, 0b1100, 0b111>; 772def : ROSysReg<"TRCIDR5", 0b10, 0b001, 0b0000, 0b1101, 0b111>; 773def : ROSysReg<"TRCIDR6", 0b10, 0b001, 0b0000, 0b1110, 0b111>; 774def : ROSysReg<"TRCIDR7", 0b10, 0b001, 0b0000, 0b1111, 0b111>; 775def : ROSysReg<"TRCOSLSR", 0b10, 0b001, 0b0001, 0b0001, 0b100>; 776def : ROSysReg<"TRCPDSR", 0b10, 0b001, 0b0001, 0b0101, 0b100>; 777def : ROSysReg<"TRCDEVAFF0", 0b10, 0b001, 0b0111, 0b1010, 0b110>; 778def : ROSysReg<"TRCDEVAFF1", 0b10, 0b001, 0b0111, 0b1011, 0b110>; 779def : ROSysReg<"TRCLSR", 0b10, 0b001, 0b0111, 0b1101, 0b110>; 780def : ROSysReg<"TRCAUTHSTATUS", 0b10, 0b001, 0b0111, 0b1110, 0b110>; 781def : ROSysReg<"TRCDEVARCH", 0b10, 0b001, 0b0111, 0b1111, 0b110>; 782def : ROSysReg<"TRCDEVID", 0b10, 0b001, 0b0111, 0b0010, 0b111>; 783def : ROSysReg<"TRCDEVTYPE", 0b10, 0b001, 0b0111, 0b0011, 0b111>; 784def : ROSysReg<"TRCPIDR4", 0b10, 0b001, 0b0111, 0b0100, 0b111>; 785def : ROSysReg<"TRCPIDR5", 0b10, 0b001, 0b0111, 0b0101, 0b111>; 786def : ROSysReg<"TRCPIDR6", 0b10, 0b001, 0b0111, 0b0110, 0b111>; 787def : ROSysReg<"TRCPIDR7", 0b10, 0b001, 0b0111, 0b0111, 0b111>; 788def : ROSysReg<"TRCPIDR0", 0b10, 0b001, 0b0111, 0b1000, 0b111>; 789def : ROSysReg<"TRCPIDR1", 0b10, 0b001, 0b0111, 0b1001, 0b111>; 790def : ROSysReg<"TRCPIDR2", 0b10, 0b001, 0b0111, 0b1010, 0b111>; 791def : ROSysReg<"TRCPIDR3", 0b10, 0b001, 0b0111, 0b1011, 0b111>; 792def : ROSysReg<"TRCCIDR0", 0b10, 0b001, 0b0111, 0b1100, 0b111>; 793def : ROSysReg<"TRCCIDR1", 0b10, 0b001, 0b0111, 0b1101, 0b111>; 794def : ROSysReg<"TRCCIDR2", 0b10, 0b001, 0b0111, 0b1110, 0b111>; 795def : ROSysReg<"TRCCIDR3", 0b10, 0b001, 0b0111, 0b1111, 0b111>; 796 797// GICv3 registers 798// Op0 Op1 CRn CRm Op2 799def : ROSysReg<"ICC_IAR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b000>; 800def : ROSysReg<"ICC_IAR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b000>; 801def : ROSysReg<"ICC_HPPIR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b010>; 802def : ROSysReg<"ICC_HPPIR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b010>; 803def : ROSysReg<"ICC_RPR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b011>; 804def : ROSysReg<"ICH_VTR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b001>; 805def : ROSysReg<"ICH_EISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b011>; 806def : ROSysReg<"ICH_ELRSR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b101>; 807 808// SVE control registers 809// Op0 Op1 CRn CRm Op2 810let Requires = [{ {AArch64::FeatureSVE} }] in { 811def : ROSysReg<"ID_AA64ZFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b100>; 812} 813 814// v8.1a "Limited Ordering Regions" extension-specific system register 815// Op0 Op1 CRn CRm Op2 816let Requires = [{ {AArch64::FeatureLOR} }] in 817def : ROSysReg<"LORID_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b111>; 818 819// v8.2a "RAS extension" registers 820// Op0 Op1 CRn CRm Op2 821let Requires = [{ {AArch64::FeatureRAS} }] in { 822def : ROSysReg<"ERRIDR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b000>; 823def : ROSysReg<"ERXFR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b000>; 824} 825 826// v8.5a "random number" registers 827// Op0 Op1 CRn CRm Op2 828let Requires = [{ {AArch64::FeatureRandGen} }] in { 829def : ROSysReg<"RNDR", 0b11, 0b011, 0b0010, 0b0100, 0b000>; 830def : ROSysReg<"RNDRRS", 0b11, 0b011, 0b0010, 0b0100, 0b001>; 831} 832 833// v8.5a Software Context Number registers 834let Requires = [{ {AArch64::FeatureSpecRestrict} }] in { 835def : RWSysReg<"SCXTNUM_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b111>; 836def : RWSysReg<"SCXTNUM_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b111>; 837def : RWSysReg<"SCXTNUM_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b111>; 838def : RWSysReg<"SCXTNUM_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b111>; 839def : RWSysReg<"SCXTNUM_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b111>; 840} 841 842// v9a Realm Management Extension registers 843let Requires = [{ {AArch64::FeatureRME} }] in { 844def : RWSysReg<"GPCCR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b110>; 845def : RWSysReg<"GPTBR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b100>; 846} 847// MFAR_EL3 is part of both FEAT_RME and FEAT_PFAR (further below). The latter 848// is unconditional so this register has to be too. 849def : RWSysReg<"MFAR_EL3", 0b11, 0b110, 0b0110, 0b0000, 0b101>; 850 851// v9a Memory Encryption Contexts Extension registers 852let Requires = [{ {AArch64::FeatureMEC} }] in { 853def : ROSysReg<"MECIDR_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b111>; 854def : RWSysReg<"MECID_P0_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b000>; 855def : RWSysReg<"MECID_A0_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b001>; 856def : RWSysReg<"MECID_P1_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b010>; 857def : RWSysReg<"MECID_A1_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b011>; 858def : RWSysReg<"VMECID_P_EL2", 0b11, 0b100, 0b1010, 0b1001, 0b000>; 859def : RWSysReg<"VMECID_A_EL2", 0b11, 0b100, 0b1010, 0b1001, 0b001>; 860def : RWSysReg<"MECID_RL_A_EL3", 0b11, 0b110, 0b1010, 0b1010, 0b001>; 861} 862 863// v9-a Scalable Matrix Extension (SME) registers 864// Op0 Op1 CRn CRm Op2 865let Requires = [{ {AArch64::FeatureSME} }] in { 866def : ROSysReg<"ID_AA64SMFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b101>; 867} 868 869//===---------------------- 870// Write-only regs 871//===---------------------- 872 873// Op0 Op1 CRn CRm Op2 874def : WOSysReg<"DBGDTRTX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>; 875def : WOSysReg<"OSLAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b100>; 876def : WOSysReg<"PMSWINC_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b100>; 877 878// Trace Registers 879// Op0 Op1 CRn CRm Op2 880def : WOSysReg<"TRCOSLAR", 0b10, 0b001, 0b0001, 0b0000, 0b100>; 881def : WOSysReg<"TRCLAR", 0b10, 0b001, 0b0111, 0b1100, 0b110>; 882 883// GICv3 registers 884// Op0 Op1 CRn CRm Op2 885def : WOSysReg<"ICC_EOIR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b001>; 886def : WOSysReg<"ICC_EOIR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b001>; 887def : WOSysReg<"ICC_DIR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b001>; 888def : WOSysReg<"ICC_SGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b101>; 889def : WOSysReg<"ICC_ASGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b110>; 890def : WOSysReg<"ICC_SGI0R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b111>; 891 892//===---------------------- 893// Read-write regs 894//===---------------------- 895 896// Op0 Op1 CRn CRm Op2 897def : RWSysReg<"OSDTRRX_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b010>; 898def : RWSysReg<"OSDTRTX_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b010>; 899def : RWSysReg<"TEECR32_EL1", 0b10, 0b010, 0b0000, 0b0000, 0b000>; 900def : RWSysReg<"MDCCINT_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b000>; 901def : RWSysReg<"MDSCR_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b010>; 902def : RWSysReg<"DBGDTR_EL0", 0b10, 0b011, 0b0000, 0b0100, 0b000>; 903def : RWSysReg<"OSECCR_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b010>; 904def : RWSysReg<"DBGVCR32_EL2", 0b10, 0b100, 0b0000, 0b0111, 0b000>; 905foreach n = 0-15 in { 906 defvar nb = !cast<bits<4>>(n); 907 // Op0 Op1 CRn CRm Op2 908 def : RWSysReg<"DBGBVR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b100>; 909 def : RWSysReg<"DBGBCR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b101>; 910 def : RWSysReg<"DBGWVR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b110>; 911 def : RWSysReg<"DBGWCR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b111>; 912} 913// Op0 Op1 CRn CRm Op2 914def : RWSysReg<"TEEHBR32_EL1", 0b10, 0b010, 0b0001, 0b0000, 0b000>; 915def : RWSysReg<"OSDLR_EL1", 0b10, 0b000, 0b0001, 0b0011, 0b100>; 916def : RWSysReg<"DBGPRCR_EL1", 0b10, 0b000, 0b0001, 0b0100, 0b100>; 917def : RWSysReg<"DBGCLAIMSET_EL1", 0b10, 0b000, 0b0111, 0b1000, 0b110>; 918def : RWSysReg<"DBGCLAIMCLR_EL1", 0b10, 0b000, 0b0111, 0b1001, 0b110>; 919def : RWSysReg<"CSSELR_EL1", 0b11, 0b010, 0b0000, 0b0000, 0b000>; 920def : RWSysReg<"VPIDR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b000>; 921def : RWSysReg<"VMPIDR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b101>; 922def : RWSysReg<"CPACR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b010>; 923def : RWSysReg<"SCTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b000>; 924def : RWSysReg<"SCTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b000>; 925def : RWSysReg<"SCTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b000>; 926def : RWSysReg<"ACTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b001>; 927def : RWSysReg<"ACTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b001>; 928def : RWSysReg<"ACTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b001>; 929def : RWSysReg<"HCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b000>; 930def : RWSysReg<"HCRX_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b010> { 931 let Requires = [{ {AArch64::FeatureHCX} }]; 932} 933def : RWSysReg<"SCR_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b000>; 934def : RWSysReg<"MDCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b001>; 935def : RWSysReg<"SDER32_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b001>; 936def : RWSysReg<"CPTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b010>; 937def : RWSysReg<"CPTR_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b010>; 938def : RWSysReg<"HSTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b011>; 939def : RWSysReg<"HACR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b111>; 940def : RWSysReg<"MDCR_EL3", 0b11, 0b110, 0b0001, 0b0011, 0b001>; 941def : RWSysReg<"TTBR0_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b000>; 942def : RWSysReg<"TTBR0_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b000>; 943 944let Requires = [{ {AArch64::FeatureEL2VMSA} }] in { 945def : RWSysReg<"TTBR0_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b000> { 946 let AltName = "VSCTLR_EL2"; 947} 948def : RWSysReg<"VTTBR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b000>; 949} 950 951def : RWSysReg<"TTBR1_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b001>; 952def : RWSysReg<"TCR_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b010>; 953def : RWSysReg<"TCR_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b010>; 954def : RWSysReg<"TCR_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b010>; 955def : RWSysReg<"VTCR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b010>; 956def : RWSysReg<"DACR32_EL2", 0b11, 0b100, 0b0011, 0b0000, 0b000>; 957def : RWSysReg<"SPSR_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b000>; 958def : RWSysReg<"SPSR_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b000>; 959def : RWSysReg<"SPSR_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b000>; 960def : RWSysReg<"ELR_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b001>; 961def : RWSysReg<"ELR_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b001>; 962def : RWSysReg<"ELR_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b001>; 963def : RWSysReg<"SP_EL0", 0b11, 0b000, 0b0100, 0b0001, 0b000>; 964def : RWSysReg<"SP_EL1", 0b11, 0b100, 0b0100, 0b0001, 0b000>; 965def : RWSysReg<"SP_EL2", 0b11, 0b110, 0b0100, 0b0001, 0b000>; 966def : RWSysReg<"SPSel", 0b11, 0b000, 0b0100, 0b0010, 0b000>; 967def : RWSysReg<"NZCV", 0b11, 0b011, 0b0100, 0b0010, 0b000>; 968def : RWSysReg<"DAIF", 0b11, 0b011, 0b0100, 0b0010, 0b001>; 969def : ROSysReg<"CurrentEL", 0b11, 0b000, 0b0100, 0b0010, 0b010>; 970def : RWSysReg<"SPSR_irq", 0b11, 0b100, 0b0100, 0b0011, 0b000>; 971def : RWSysReg<"SPSR_abt", 0b11, 0b100, 0b0100, 0b0011, 0b001>; 972def : RWSysReg<"SPSR_und", 0b11, 0b100, 0b0100, 0b0011, 0b010>; 973def : RWSysReg<"SPSR_fiq", 0b11, 0b100, 0b0100, 0b0011, 0b011>; 974def : RWSysReg<"FPCR", 0b11, 0b011, 0b0100, 0b0100, 0b000>; 975def : RWSysReg<"FPSR", 0b11, 0b011, 0b0100, 0b0100, 0b001>; 976def : RWSysReg<"DSPSR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b000>; 977def : RWSysReg<"DLR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b001>; 978def : RWSysReg<"IFSR32_EL2", 0b11, 0b100, 0b0101, 0b0000, 0b001>; 979def : RWSysReg<"AFSR0_EL1", 0b11, 0b000, 0b0101, 0b0001, 0b000>; 980def : RWSysReg<"AFSR0_EL2", 0b11, 0b100, 0b0101, 0b0001, 0b000>; 981def : RWSysReg<"AFSR0_EL3", 0b11, 0b110, 0b0101, 0b0001, 0b000>; 982def : RWSysReg<"AFSR1_EL1", 0b11, 0b000, 0b0101, 0b0001, 0b001>; 983def : RWSysReg<"AFSR1_EL2", 0b11, 0b100, 0b0101, 0b0001, 0b001>; 984def : RWSysReg<"AFSR1_EL3", 0b11, 0b110, 0b0101, 0b0001, 0b001>; 985def : RWSysReg<"ESR_EL1", 0b11, 0b000, 0b0101, 0b0010, 0b000>; 986def : RWSysReg<"ESR_EL2", 0b11, 0b100, 0b0101, 0b0010, 0b000>; 987def : RWSysReg<"ESR_EL3", 0b11, 0b110, 0b0101, 0b0010, 0b000>; 988def : RWSysReg<"FPEXC32_EL2", 0b11, 0b100, 0b0101, 0b0011, 0b000>; 989def : RWSysReg<"FAR_EL1", 0b11, 0b000, 0b0110, 0b0000, 0b000>; 990def : RWSysReg<"FAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b000>; 991def : RWSysReg<"FAR_EL3", 0b11, 0b110, 0b0110, 0b0000, 0b000>; 992def : RWSysReg<"HPFAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b100>; 993def : RWSysReg<"PAR_EL1", 0b11, 0b000, 0b0111, 0b0100, 0b000>; 994def : RWSysReg<"PMCR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b000>; 995def : RWSysReg<"PMCNTENSET_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b001>; 996def : RWSysReg<"PMCNTENCLR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b010>; 997def : RWSysReg<"PMOVSCLR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b011>; 998def : RWSysReg<"PMSELR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b101>; 999def : RWSysReg<"PMCCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b000>; 1000def : RWSysReg<"PMXEVTYPER_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b001>; 1001def : RWSysReg<"PMXEVCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b010>; 1002def : RWSysReg<"PMUSERENR_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b000>; 1003def : RWSysReg<"PMINTENSET_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b001>; 1004def : RWSysReg<"PMINTENCLR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b010>; 1005def : RWSysReg<"PMOVSSET_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b011>; 1006def : RWSysReg<"MAIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b000>; 1007def : RWSysReg<"MAIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b000>; 1008def : RWSysReg<"MAIR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b000>; 1009def : RWSysReg<"AMAIR_EL1", 0b11, 0b000, 0b1010, 0b0011, 0b000>; 1010def : RWSysReg<"AMAIR_EL2", 0b11, 0b100, 0b1010, 0b0011, 0b000>; 1011def : RWSysReg<"AMAIR_EL3", 0b11, 0b110, 0b1010, 0b0011, 0b000>; 1012def : RWSysReg<"VBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b000>; 1013def : RWSysReg<"VBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b000>; 1014def : RWSysReg<"VBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b000>; 1015def : RWSysReg<"RMR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b010>; 1016def : RWSysReg<"RMR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b010>; 1017def : RWSysReg<"RMR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b010>; 1018def : RWSysReg<"CONTEXTIDR_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b001>; 1019def : RWSysReg<"TPIDR_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b010>; 1020def : RWSysReg<"TPIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b010>; 1021def : RWSysReg<"TPIDR_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b010>; 1022def : RWSysReg<"TPIDRRO_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b011>; 1023def : RWSysReg<"TPIDR_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b100>; 1024def : RWSysReg<"CNTFRQ_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b000>; 1025def : RWSysReg<"CNTVOFF_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b011>; 1026def : RWSysReg<"CNTKCTL_EL1", 0b11, 0b000, 0b1110, 0b0001, 0b000>; 1027def : RWSysReg<"CNTHCTL_EL2", 0b11, 0b100, 0b1110, 0b0001, 0b000>; 1028def : RWSysReg<"CNTP_TVAL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b000>; 1029def : RWSysReg<"CNTHP_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b000>; 1030def : RWSysReg<"CNTPS_TVAL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b000>; 1031def : RWSysReg<"CNTP_CTL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b001>; 1032def : RWSysReg<"CNTHP_CTL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b001>; 1033def : RWSysReg<"CNTPS_CTL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b001>; 1034def : RWSysReg<"CNTP_CVAL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b010>; 1035def : RWSysReg<"CNTHP_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b010>; 1036def : RWSysReg<"CNTPS_CVAL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b010>; 1037def : RWSysReg<"CNTV_TVAL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b000>; 1038def : RWSysReg<"CNTV_CTL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b001>; 1039def : RWSysReg<"CNTV_CVAL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b010>; 1040def : RWSysReg<"PMEVCNTR0_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b000>; 1041def : RWSysReg<"PMEVCNTR1_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b001>; 1042def : RWSysReg<"PMEVCNTR2_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b010>; 1043def : RWSysReg<"PMEVCNTR3_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b011>; 1044def : RWSysReg<"PMEVCNTR4_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b100>; 1045def : RWSysReg<"PMEVCNTR5_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b101>; 1046def : RWSysReg<"PMEVCNTR6_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b110>; 1047def : RWSysReg<"PMEVCNTR7_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b111>; 1048def : RWSysReg<"PMEVCNTR8_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b000>; 1049def : RWSysReg<"PMEVCNTR9_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b001>; 1050def : RWSysReg<"PMEVCNTR10_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b010>; 1051def : RWSysReg<"PMEVCNTR11_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b011>; 1052def : RWSysReg<"PMEVCNTR12_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b100>; 1053def : RWSysReg<"PMEVCNTR13_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b101>; 1054def : RWSysReg<"PMEVCNTR14_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b110>; 1055def : RWSysReg<"PMEVCNTR15_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b111>; 1056def : RWSysReg<"PMEVCNTR16_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b000>; 1057def : RWSysReg<"PMEVCNTR17_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b001>; 1058def : RWSysReg<"PMEVCNTR18_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b010>; 1059def : RWSysReg<"PMEVCNTR19_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b011>; 1060def : RWSysReg<"PMEVCNTR20_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b100>; 1061def : RWSysReg<"PMEVCNTR21_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b101>; 1062def : RWSysReg<"PMEVCNTR22_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b110>; 1063def : RWSysReg<"PMEVCNTR23_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b111>; 1064def : RWSysReg<"PMEVCNTR24_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b000>; 1065def : RWSysReg<"PMEVCNTR25_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b001>; 1066def : RWSysReg<"PMEVCNTR26_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b010>; 1067def : RWSysReg<"PMEVCNTR27_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b011>; 1068def : RWSysReg<"PMEVCNTR28_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b100>; 1069def : RWSysReg<"PMEVCNTR29_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b101>; 1070def : RWSysReg<"PMEVCNTR30_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b110>; 1071def : RWSysReg<"PMCCFILTR_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b111>; 1072def : RWSysReg<"PMEVTYPER0_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b000>; 1073def : RWSysReg<"PMEVTYPER1_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b001>; 1074def : RWSysReg<"PMEVTYPER2_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b010>; 1075def : RWSysReg<"PMEVTYPER3_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b011>; 1076def : RWSysReg<"PMEVTYPER4_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b100>; 1077def : RWSysReg<"PMEVTYPER5_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b101>; 1078def : RWSysReg<"PMEVTYPER6_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b110>; 1079def : RWSysReg<"PMEVTYPER7_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b111>; 1080def : RWSysReg<"PMEVTYPER8_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b000>; 1081def : RWSysReg<"PMEVTYPER9_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b001>; 1082def : RWSysReg<"PMEVTYPER10_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b010>; 1083def : RWSysReg<"PMEVTYPER11_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b011>; 1084def : RWSysReg<"PMEVTYPER12_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b100>; 1085def : RWSysReg<"PMEVTYPER13_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b101>; 1086def : RWSysReg<"PMEVTYPER14_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b110>; 1087def : RWSysReg<"PMEVTYPER15_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b111>; 1088def : RWSysReg<"PMEVTYPER16_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b000>; 1089def : RWSysReg<"PMEVTYPER17_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b001>; 1090def : RWSysReg<"PMEVTYPER18_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b010>; 1091def : RWSysReg<"PMEVTYPER19_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b011>; 1092def : RWSysReg<"PMEVTYPER20_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b100>; 1093def : RWSysReg<"PMEVTYPER21_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b101>; 1094def : RWSysReg<"PMEVTYPER22_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b110>; 1095def : RWSysReg<"PMEVTYPER23_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b111>; 1096def : RWSysReg<"PMEVTYPER24_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b000>; 1097def : RWSysReg<"PMEVTYPER25_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b001>; 1098def : RWSysReg<"PMEVTYPER26_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b010>; 1099def : RWSysReg<"PMEVTYPER27_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b011>; 1100def : RWSysReg<"PMEVTYPER28_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b100>; 1101def : RWSysReg<"PMEVTYPER29_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b101>; 1102def : RWSysReg<"PMEVTYPER30_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b110>; 1103 1104// Trace registers 1105// Op0 Op1 CRn CRm Op2 1106def : RWSysReg<"TRCPRGCTLR", 0b10, 0b001, 0b0000, 0b0001, 0b000>; 1107def : RWSysReg<"TRCPROCSELR", 0b10, 0b001, 0b0000, 0b0010, 0b000>; 1108def : RWSysReg<"TRCCONFIGR", 0b10, 0b001, 0b0000, 0b0100, 0b000>; 1109def : RWSysReg<"TRCAUXCTLR", 0b10, 0b001, 0b0000, 0b0110, 0b000>; 1110def : RWSysReg<"TRCEVENTCTL0R", 0b10, 0b001, 0b0000, 0b1000, 0b000>; 1111def : RWSysReg<"TRCEVENTCTL1R", 0b10, 0b001, 0b0000, 0b1001, 0b000>; 1112def : RWSysReg<"TRCSTALLCTLR", 0b10, 0b001, 0b0000, 0b1011, 0b000>; 1113def : RWSysReg<"TRCTSCTLR", 0b10, 0b001, 0b0000, 0b1100, 0b000>; 1114def : RWSysReg<"TRCSYNCPR", 0b10, 0b001, 0b0000, 0b1101, 0b000>; 1115def : RWSysReg<"TRCCCCTLR", 0b10, 0b001, 0b0000, 0b1110, 0b000>; 1116def : RWSysReg<"TRCBBCTLR", 0b10, 0b001, 0b0000, 0b1111, 0b000>; 1117def : RWSysReg<"TRCTRACEIDR", 0b10, 0b001, 0b0000, 0b0000, 0b001>; 1118def : RWSysReg<"TRCQCTLR", 0b10, 0b001, 0b0000, 0b0001, 0b001>; 1119def : RWSysReg<"TRCVICTLR", 0b10, 0b001, 0b0000, 0b0000, 0b010>; 1120def : RWSysReg<"TRCVIIECTLR", 0b10, 0b001, 0b0000, 0b0001, 0b010>; 1121def : RWSysReg<"TRCVISSCTLR", 0b10, 0b001, 0b0000, 0b0010, 0b010>; 1122def : RWSysReg<"TRCVIPCSSCTLR", 0b10, 0b001, 0b0000, 0b0011, 0b010>; 1123def : RWSysReg<"TRCVDCTLR", 0b10, 0b001, 0b0000, 0b1000, 0b010>; 1124def : RWSysReg<"TRCVDSACCTLR", 0b10, 0b001, 0b0000, 0b1001, 0b010>; 1125def : RWSysReg<"TRCVDARCCTLR", 0b10, 0b001, 0b0000, 0b1010, 0b010>; 1126def : RWSysReg<"TRCSEQEVR0", 0b10, 0b001, 0b0000, 0b0000, 0b100>; 1127def : RWSysReg<"TRCSEQEVR1", 0b10, 0b001, 0b0000, 0b0001, 0b100>; 1128def : RWSysReg<"TRCSEQEVR2", 0b10, 0b001, 0b0000, 0b0010, 0b100>; 1129def : RWSysReg<"TRCSEQRSTEVR", 0b10, 0b001, 0b0000, 0b0110, 0b100>; 1130def : RWSysReg<"TRCSEQSTR", 0b10, 0b001, 0b0000, 0b0111, 0b100>; 1131def : RWSysReg<"TRCEXTINSELR", 0b10, 0b001, 0b0000, 0b1000, 0b100>; 1132def : RWSysReg<"TRCCNTRLDVR0", 0b10, 0b001, 0b0000, 0b0000, 0b101>; 1133def : RWSysReg<"TRCCNTRLDVR1", 0b10, 0b001, 0b0000, 0b0001, 0b101>; 1134def : RWSysReg<"TRCCNTRLDVR2", 0b10, 0b001, 0b0000, 0b0010, 0b101>; 1135def : RWSysReg<"TRCCNTRLDVR3", 0b10, 0b001, 0b0000, 0b0011, 0b101>; 1136def : RWSysReg<"TRCCNTCTLR0", 0b10, 0b001, 0b0000, 0b0100, 0b101>; 1137def : RWSysReg<"TRCCNTCTLR1", 0b10, 0b001, 0b0000, 0b0101, 0b101>; 1138def : RWSysReg<"TRCCNTCTLR2", 0b10, 0b001, 0b0000, 0b0110, 0b101>; 1139def : RWSysReg<"TRCCNTCTLR3", 0b10, 0b001, 0b0000, 0b0111, 0b101>; 1140def : RWSysReg<"TRCCNTVR0", 0b10, 0b001, 0b0000, 0b1000, 0b101>; 1141def : RWSysReg<"TRCCNTVR1", 0b10, 0b001, 0b0000, 0b1001, 0b101>; 1142def : RWSysReg<"TRCCNTVR2", 0b10, 0b001, 0b0000, 0b1010, 0b101>; 1143def : RWSysReg<"TRCCNTVR3", 0b10, 0b001, 0b0000, 0b1011, 0b101>; 1144def : RWSysReg<"TRCIMSPEC0", 0b10, 0b001, 0b0000, 0b0000, 0b111>; 1145def : RWSysReg<"TRCIMSPEC1", 0b10, 0b001, 0b0000, 0b0001, 0b111>; 1146def : RWSysReg<"TRCIMSPEC2", 0b10, 0b001, 0b0000, 0b0010, 0b111>; 1147def : RWSysReg<"TRCIMSPEC3", 0b10, 0b001, 0b0000, 0b0011, 0b111>; 1148def : RWSysReg<"TRCIMSPEC4", 0b10, 0b001, 0b0000, 0b0100, 0b111>; 1149def : RWSysReg<"TRCIMSPEC5", 0b10, 0b001, 0b0000, 0b0101, 0b111>; 1150def : RWSysReg<"TRCIMSPEC6", 0b10, 0b001, 0b0000, 0b0110, 0b111>; 1151def : RWSysReg<"TRCIMSPEC7", 0b10, 0b001, 0b0000, 0b0111, 0b111>; 1152def : RWSysReg<"TRCRSCTLR2", 0b10, 0b001, 0b0001, 0b0010, 0b000>; 1153def : RWSysReg<"TRCRSCTLR3", 0b10, 0b001, 0b0001, 0b0011, 0b000>; 1154def : RWSysReg<"TRCRSCTLR4", 0b10, 0b001, 0b0001, 0b0100, 0b000>; 1155def : RWSysReg<"TRCRSCTLR5", 0b10, 0b001, 0b0001, 0b0101, 0b000>; 1156def : RWSysReg<"TRCRSCTLR6", 0b10, 0b001, 0b0001, 0b0110, 0b000>; 1157def : RWSysReg<"TRCRSCTLR7", 0b10, 0b001, 0b0001, 0b0111, 0b000>; 1158def : RWSysReg<"TRCRSCTLR8", 0b10, 0b001, 0b0001, 0b1000, 0b000>; 1159def : RWSysReg<"TRCRSCTLR9", 0b10, 0b001, 0b0001, 0b1001, 0b000>; 1160def : RWSysReg<"TRCRSCTLR10", 0b10, 0b001, 0b0001, 0b1010, 0b000>; 1161def : RWSysReg<"TRCRSCTLR11", 0b10, 0b001, 0b0001, 0b1011, 0b000>; 1162def : RWSysReg<"TRCRSCTLR12", 0b10, 0b001, 0b0001, 0b1100, 0b000>; 1163def : RWSysReg<"TRCRSCTLR13", 0b10, 0b001, 0b0001, 0b1101, 0b000>; 1164def : RWSysReg<"TRCRSCTLR14", 0b10, 0b001, 0b0001, 0b1110, 0b000>; 1165def : RWSysReg<"TRCRSCTLR15", 0b10, 0b001, 0b0001, 0b1111, 0b000>; 1166def : RWSysReg<"TRCRSCTLR16", 0b10, 0b001, 0b0001, 0b0000, 0b001>; 1167def : RWSysReg<"TRCRSCTLR17", 0b10, 0b001, 0b0001, 0b0001, 0b001>; 1168def : RWSysReg<"TRCRSCTLR18", 0b10, 0b001, 0b0001, 0b0010, 0b001>; 1169def : RWSysReg<"TRCRSCTLR19", 0b10, 0b001, 0b0001, 0b0011, 0b001>; 1170def : RWSysReg<"TRCRSCTLR20", 0b10, 0b001, 0b0001, 0b0100, 0b001>; 1171def : RWSysReg<"TRCRSCTLR21", 0b10, 0b001, 0b0001, 0b0101, 0b001>; 1172def : RWSysReg<"TRCRSCTLR22", 0b10, 0b001, 0b0001, 0b0110, 0b001>; 1173def : RWSysReg<"TRCRSCTLR23", 0b10, 0b001, 0b0001, 0b0111, 0b001>; 1174def : RWSysReg<"TRCRSCTLR24", 0b10, 0b001, 0b0001, 0b1000, 0b001>; 1175def : RWSysReg<"TRCRSCTLR25", 0b10, 0b001, 0b0001, 0b1001, 0b001>; 1176def : RWSysReg<"TRCRSCTLR26", 0b10, 0b001, 0b0001, 0b1010, 0b001>; 1177def : RWSysReg<"TRCRSCTLR27", 0b10, 0b001, 0b0001, 0b1011, 0b001>; 1178def : RWSysReg<"TRCRSCTLR28", 0b10, 0b001, 0b0001, 0b1100, 0b001>; 1179def : RWSysReg<"TRCRSCTLR29", 0b10, 0b001, 0b0001, 0b1101, 0b001>; 1180def : RWSysReg<"TRCRSCTLR30", 0b10, 0b001, 0b0001, 0b1110, 0b001>; 1181def : RWSysReg<"TRCRSCTLR31", 0b10, 0b001, 0b0001, 0b1111, 0b001>; 1182def : RWSysReg<"TRCSSCCR0", 0b10, 0b001, 0b0001, 0b0000, 0b010>; 1183def : RWSysReg<"TRCSSCCR1", 0b10, 0b001, 0b0001, 0b0001, 0b010>; 1184def : RWSysReg<"TRCSSCCR2", 0b10, 0b001, 0b0001, 0b0010, 0b010>; 1185def : RWSysReg<"TRCSSCCR3", 0b10, 0b001, 0b0001, 0b0011, 0b010>; 1186def : RWSysReg<"TRCSSCCR4", 0b10, 0b001, 0b0001, 0b0100, 0b010>; 1187def : RWSysReg<"TRCSSCCR5", 0b10, 0b001, 0b0001, 0b0101, 0b010>; 1188def : RWSysReg<"TRCSSCCR6", 0b10, 0b001, 0b0001, 0b0110, 0b010>; 1189def : RWSysReg<"TRCSSCCR7", 0b10, 0b001, 0b0001, 0b0111, 0b010>; 1190def : RWSysReg<"TRCSSCSR0", 0b10, 0b001, 0b0001, 0b1000, 0b010>; 1191def : RWSysReg<"TRCSSCSR1", 0b10, 0b001, 0b0001, 0b1001, 0b010>; 1192def : RWSysReg<"TRCSSCSR2", 0b10, 0b001, 0b0001, 0b1010, 0b010>; 1193def : RWSysReg<"TRCSSCSR3", 0b10, 0b001, 0b0001, 0b1011, 0b010>; 1194def : RWSysReg<"TRCSSCSR4", 0b10, 0b001, 0b0001, 0b1100, 0b010>; 1195def : RWSysReg<"TRCSSCSR5", 0b10, 0b001, 0b0001, 0b1101, 0b010>; 1196def : RWSysReg<"TRCSSCSR6", 0b10, 0b001, 0b0001, 0b1110, 0b010>; 1197def : RWSysReg<"TRCSSCSR7", 0b10, 0b001, 0b0001, 0b1111, 0b010>; 1198def : RWSysReg<"TRCSSPCICR0", 0b10, 0b001, 0b0001, 0b0000, 0b011>; 1199def : RWSysReg<"TRCSSPCICR1", 0b10, 0b001, 0b0001, 0b0001, 0b011>; 1200def : RWSysReg<"TRCSSPCICR2", 0b10, 0b001, 0b0001, 0b0010, 0b011>; 1201def : RWSysReg<"TRCSSPCICR3", 0b10, 0b001, 0b0001, 0b0011, 0b011>; 1202def : RWSysReg<"TRCSSPCICR4", 0b10, 0b001, 0b0001, 0b0100, 0b011>; 1203def : RWSysReg<"TRCSSPCICR5", 0b10, 0b001, 0b0001, 0b0101, 0b011>; 1204def : RWSysReg<"TRCSSPCICR6", 0b10, 0b001, 0b0001, 0b0110, 0b011>; 1205def : RWSysReg<"TRCSSPCICR7", 0b10, 0b001, 0b0001, 0b0111, 0b011>; 1206def : RWSysReg<"TRCPDCR", 0b10, 0b001, 0b0001, 0b0100, 0b100>; 1207def : RWSysReg<"TRCACVR0", 0b10, 0b001, 0b0010, 0b0000, 0b000>; 1208def : RWSysReg<"TRCACVR1", 0b10, 0b001, 0b0010, 0b0010, 0b000>; 1209def : RWSysReg<"TRCACVR2", 0b10, 0b001, 0b0010, 0b0100, 0b000>; 1210def : RWSysReg<"TRCACVR3", 0b10, 0b001, 0b0010, 0b0110, 0b000>; 1211def : RWSysReg<"TRCACVR4", 0b10, 0b001, 0b0010, 0b1000, 0b000>; 1212def : RWSysReg<"TRCACVR5", 0b10, 0b001, 0b0010, 0b1010, 0b000>; 1213def : RWSysReg<"TRCACVR6", 0b10, 0b001, 0b0010, 0b1100, 0b000>; 1214def : RWSysReg<"TRCACVR7", 0b10, 0b001, 0b0010, 0b1110, 0b000>; 1215def : RWSysReg<"TRCACVR8", 0b10, 0b001, 0b0010, 0b0000, 0b001>; 1216def : RWSysReg<"TRCACVR9", 0b10, 0b001, 0b0010, 0b0010, 0b001>; 1217def : RWSysReg<"TRCACVR10", 0b10, 0b001, 0b0010, 0b0100, 0b001>; 1218def : RWSysReg<"TRCACVR11", 0b10, 0b001, 0b0010, 0b0110, 0b001>; 1219def : RWSysReg<"TRCACVR12", 0b10, 0b001, 0b0010, 0b1000, 0b001>; 1220def : RWSysReg<"TRCACVR13", 0b10, 0b001, 0b0010, 0b1010, 0b001>; 1221def : RWSysReg<"TRCACVR14", 0b10, 0b001, 0b0010, 0b1100, 0b001>; 1222def : RWSysReg<"TRCACVR15", 0b10, 0b001, 0b0010, 0b1110, 0b001>; 1223def : RWSysReg<"TRCACATR0", 0b10, 0b001, 0b0010, 0b0000, 0b010>; 1224def : RWSysReg<"TRCACATR1", 0b10, 0b001, 0b0010, 0b0010, 0b010>; 1225def : RWSysReg<"TRCACATR2", 0b10, 0b001, 0b0010, 0b0100, 0b010>; 1226def : RWSysReg<"TRCACATR3", 0b10, 0b001, 0b0010, 0b0110, 0b010>; 1227def : RWSysReg<"TRCACATR4", 0b10, 0b001, 0b0010, 0b1000, 0b010>; 1228def : RWSysReg<"TRCACATR5", 0b10, 0b001, 0b0010, 0b1010, 0b010>; 1229def : RWSysReg<"TRCACATR6", 0b10, 0b001, 0b0010, 0b1100, 0b010>; 1230def : RWSysReg<"TRCACATR7", 0b10, 0b001, 0b0010, 0b1110, 0b010>; 1231def : RWSysReg<"TRCACATR8", 0b10, 0b001, 0b0010, 0b0000, 0b011>; 1232def : RWSysReg<"TRCACATR9", 0b10, 0b001, 0b0010, 0b0010, 0b011>; 1233def : RWSysReg<"TRCACATR10", 0b10, 0b001, 0b0010, 0b0100, 0b011>; 1234def : RWSysReg<"TRCACATR11", 0b10, 0b001, 0b0010, 0b0110, 0b011>; 1235def : RWSysReg<"TRCACATR12", 0b10, 0b001, 0b0010, 0b1000, 0b011>; 1236def : RWSysReg<"TRCACATR13", 0b10, 0b001, 0b0010, 0b1010, 0b011>; 1237def : RWSysReg<"TRCACATR14", 0b10, 0b001, 0b0010, 0b1100, 0b011>; 1238def : RWSysReg<"TRCACATR15", 0b10, 0b001, 0b0010, 0b1110, 0b011>; 1239def : RWSysReg<"TRCDVCVR0", 0b10, 0b001, 0b0010, 0b0000, 0b100>; 1240def : RWSysReg<"TRCDVCVR1", 0b10, 0b001, 0b0010, 0b0100, 0b100>; 1241def : RWSysReg<"TRCDVCVR2", 0b10, 0b001, 0b0010, 0b1000, 0b100>; 1242def : RWSysReg<"TRCDVCVR3", 0b10, 0b001, 0b0010, 0b1100, 0b100>; 1243def : RWSysReg<"TRCDVCVR4", 0b10, 0b001, 0b0010, 0b0000, 0b101>; 1244def : RWSysReg<"TRCDVCVR5", 0b10, 0b001, 0b0010, 0b0100, 0b101>; 1245def : RWSysReg<"TRCDVCVR6", 0b10, 0b001, 0b0010, 0b1000, 0b101>; 1246def : RWSysReg<"TRCDVCVR7", 0b10, 0b001, 0b0010, 0b1100, 0b101>; 1247def : RWSysReg<"TRCDVCMR0", 0b10, 0b001, 0b0010, 0b0000, 0b110>; 1248def : RWSysReg<"TRCDVCMR1", 0b10, 0b001, 0b0010, 0b0100, 0b110>; 1249def : RWSysReg<"TRCDVCMR2", 0b10, 0b001, 0b0010, 0b1000, 0b110>; 1250def : RWSysReg<"TRCDVCMR3", 0b10, 0b001, 0b0010, 0b1100, 0b110>; 1251def : RWSysReg<"TRCDVCMR4", 0b10, 0b001, 0b0010, 0b0000, 0b111>; 1252def : RWSysReg<"TRCDVCMR5", 0b10, 0b001, 0b0010, 0b0100, 0b111>; 1253def : RWSysReg<"TRCDVCMR6", 0b10, 0b001, 0b0010, 0b1000, 0b111>; 1254def : RWSysReg<"TRCDVCMR7", 0b10, 0b001, 0b0010, 0b1100, 0b111>; 1255def : RWSysReg<"TRCCIDCVR0", 0b10, 0b001, 0b0011, 0b0000, 0b000>; 1256def : RWSysReg<"TRCCIDCVR1", 0b10, 0b001, 0b0011, 0b0010, 0b000>; 1257def : RWSysReg<"TRCCIDCVR2", 0b10, 0b001, 0b0011, 0b0100, 0b000>; 1258def : RWSysReg<"TRCCIDCVR3", 0b10, 0b001, 0b0011, 0b0110, 0b000>; 1259def : RWSysReg<"TRCCIDCVR4", 0b10, 0b001, 0b0011, 0b1000, 0b000>; 1260def : RWSysReg<"TRCCIDCVR5", 0b10, 0b001, 0b0011, 0b1010, 0b000>; 1261def : RWSysReg<"TRCCIDCVR6", 0b10, 0b001, 0b0011, 0b1100, 0b000>; 1262def : RWSysReg<"TRCCIDCVR7", 0b10, 0b001, 0b0011, 0b1110, 0b000>; 1263def : RWSysReg<"TRCVMIDCVR0", 0b10, 0b001, 0b0011, 0b0000, 0b001>; 1264def : RWSysReg<"TRCVMIDCVR1", 0b10, 0b001, 0b0011, 0b0010, 0b001>; 1265def : RWSysReg<"TRCVMIDCVR2", 0b10, 0b001, 0b0011, 0b0100, 0b001>; 1266def : RWSysReg<"TRCVMIDCVR3", 0b10, 0b001, 0b0011, 0b0110, 0b001>; 1267def : RWSysReg<"TRCVMIDCVR4", 0b10, 0b001, 0b0011, 0b1000, 0b001>; 1268def : RWSysReg<"TRCVMIDCVR5", 0b10, 0b001, 0b0011, 0b1010, 0b001>; 1269def : RWSysReg<"TRCVMIDCVR6", 0b10, 0b001, 0b0011, 0b1100, 0b001>; 1270def : RWSysReg<"TRCVMIDCVR7", 0b10, 0b001, 0b0011, 0b1110, 0b001>; 1271def : RWSysReg<"TRCCIDCCTLR0", 0b10, 0b001, 0b0011, 0b0000, 0b010>; 1272def : RWSysReg<"TRCCIDCCTLR1", 0b10, 0b001, 0b0011, 0b0001, 0b010>; 1273def : RWSysReg<"TRCVMIDCCTLR0", 0b10, 0b001, 0b0011, 0b0010, 0b010>; 1274def : RWSysReg<"TRCVMIDCCTLR1", 0b10, 0b001, 0b0011, 0b0011, 0b010>; 1275def : RWSysReg<"TRCITCTRL", 0b10, 0b001, 0b0111, 0b0000, 0b100>; 1276def : RWSysReg<"TRCCLAIMSET", 0b10, 0b001, 0b0111, 0b1000, 0b110>; 1277def : RWSysReg<"TRCCLAIMCLR", 0b10, 0b001, 0b0111, 0b1001, 0b110>; 1278 1279// GICv3 registers 1280// Op0 Op1 CRn CRm Op2 1281def : RWSysReg<"ICC_BPR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b011>; 1282def : RWSysReg<"ICC_BPR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b011>; 1283def : RWSysReg<"ICC_PMR_EL1", 0b11, 0b000, 0b0100, 0b0110, 0b000>; 1284def : RWSysReg<"ICC_CTLR_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b100>; 1285def : RWSysReg<"ICC_CTLR_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b100>; 1286def : RWSysReg<"ICC_SRE_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b101>; 1287def : RWSysReg<"ICC_SRE_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b101>; 1288def : RWSysReg<"ICC_SRE_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b101>; 1289def : RWSysReg<"ICC_IGRPEN0_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b110>; 1290def : RWSysReg<"ICC_IGRPEN1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b111>; 1291def : RWSysReg<"ICC_IGRPEN1_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b111>; 1292def : RWSysReg<"ICC_AP0R0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b100>; 1293def : RWSysReg<"ICC_AP0R1_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b101>; 1294def : RWSysReg<"ICC_AP0R2_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b110>; 1295def : RWSysReg<"ICC_AP0R3_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b111>; 1296def : RWSysReg<"ICC_AP1R0_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b000>; 1297def : RWSysReg<"ICC_AP1R1_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b001>; 1298def : RWSysReg<"ICC_AP1R2_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b010>; 1299def : RWSysReg<"ICC_AP1R3_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b011>; 1300def : RWSysReg<"ICH_AP0R0_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b000>; 1301def : RWSysReg<"ICH_AP0R1_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b001>; 1302def : RWSysReg<"ICH_AP0R2_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b010>; 1303def : RWSysReg<"ICH_AP0R3_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b011>; 1304def : RWSysReg<"ICH_AP1R0_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b000>; 1305def : RWSysReg<"ICH_AP1R1_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b001>; 1306def : RWSysReg<"ICH_AP1R2_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b010>; 1307def : RWSysReg<"ICH_AP1R3_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b011>; 1308def : RWSysReg<"ICH_HCR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b000>; 1309def : ROSysReg<"ICH_MISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b010>; 1310def : RWSysReg<"ICH_VMCR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b111>; 1311def : RWSysReg<"ICH_LR0_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b000>; 1312def : RWSysReg<"ICH_LR1_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b001>; 1313def : RWSysReg<"ICH_LR2_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b010>; 1314def : RWSysReg<"ICH_LR3_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b011>; 1315def : RWSysReg<"ICH_LR4_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b100>; 1316def : RWSysReg<"ICH_LR5_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b101>; 1317def : RWSysReg<"ICH_LR6_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b110>; 1318def : RWSysReg<"ICH_LR7_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b111>; 1319def : RWSysReg<"ICH_LR8_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b000>; 1320def : RWSysReg<"ICH_LR9_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b001>; 1321def : RWSysReg<"ICH_LR10_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b010>; 1322def : RWSysReg<"ICH_LR11_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b011>; 1323def : RWSysReg<"ICH_LR12_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b100>; 1324def : RWSysReg<"ICH_LR13_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b101>; 1325def : RWSysReg<"ICH_LR14_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b110>; 1326def : RWSysReg<"ICH_LR15_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b111>; 1327 1328// v8r system registers 1329let Requires = [{ {AArch64::HasV8_0rOps} }] in { 1330//Virtualization System Control Register 1331// Op0 Op1 CRn CRm Op2 1332def : RWSysReg<"VSCTLR_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b000> { 1333 let AltName = "TTBR0_EL2"; 1334} 1335 1336//MPU Type Register 1337// Op0 Op1 CRn CRm Op2 1338def : RWSysReg<"MPUIR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b100>; 1339def : RWSysReg<"MPUIR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b100>; 1340 1341//Protection Region Enable Register 1342// Op0 Op1 CRn CRm Op2 1343def : RWSysReg<"PRENR_EL1", 0b11, 0b000, 0b0110, 0b0001, 0b001>; 1344def : RWSysReg<"PRENR_EL2", 0b11, 0b100, 0b0110, 0b0001, 0b001>; 1345 1346//Protection Region Selection Register 1347// Op0 Op1 CRn CRm Op2 1348def : RWSysReg<"PRSELR_EL1", 0b11, 0b000, 0b0110, 0b0010, 0b001>; 1349def : RWSysReg<"PRSELR_EL2", 0b11, 0b100, 0b0110, 0b0010, 0b001>; 1350 1351//Protection Region Base Address Register 1352// Op0 Op1 CRn CRm Op2 1353def : RWSysReg<"PRBAR_EL1", 0b11, 0b000, 0b0110, 0b1000, 0b000>; 1354def : RWSysReg<"PRBAR_EL2", 0b11, 0b100, 0b0110, 0b1000, 0b000>; 1355 1356//Protection Region Limit Address Register 1357// Op0 Op1 CRn CRm Op2 1358def : RWSysReg<"PRLAR_EL1", 0b11, 0b000, 0b0110, 0b1000, 0b001>; 1359def : RWSysReg<"PRLAR_EL2", 0b11, 0b100, 0b0110, 0b1000, 0b001>; 1360 1361foreach n = 1-15 in { 1362foreach x = 1-2 in { 1363//Direct acces to Protection Region Base Address Register for n th MPU region 1364 def : RWSysReg<!strconcat("PRBAR"#n, "_EL"#x), 1365 0b11, 0b000, 0b0110, 0b1000, 0b000>{ 1366 let Encoding{5-2} = n; 1367 let Encoding{13} = !add(x,-1); 1368 } 1369 1370 def : RWSysReg<!strconcat("PRLAR"#n, "_EL"#x), 1371 0b11, 0b000, 0b0110, 0b1000, 0b001>{ 1372 let Encoding{5-2} = n; 1373 let Encoding{13} = !add(x,-1); 1374 } 1375} //foreach x = 1-2 in 1376} //foreach n = 1-15 in 1377} //let Requires = [{ {AArch64::HasV8_0rOps} }] in 1378 1379// v8.1a "Privileged Access Never" extension-specific system registers 1380let Requires = [{ {AArch64::FeaturePAN} }] in 1381def : RWSysReg<"PAN", 0b11, 0b000, 0b0100, 0b0010, 0b011>; 1382 1383// v8.1a "Limited Ordering Regions" extension-specific system registers 1384// Op0 Op1 CRn CRm Op2 1385let Requires = [{ {AArch64::FeatureLOR} }] in { 1386def : RWSysReg<"LORSA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b000>; 1387def : RWSysReg<"LOREA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b001>; 1388def : RWSysReg<"LORN_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b010>; 1389def : RWSysReg<"LORC_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b011>; 1390} 1391 1392// v8.1a "Virtualization Host extensions" system registers 1393// Op0 Op1 CRn CRm Op2 1394let Requires = [{ {AArch64::FeatureVH} }] in { 1395def : RWSysReg<"TTBR1_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b001>; 1396def : RWSysReg<"CNTHV_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b000>; 1397def : RWSysReg<"CNTHV_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b010>; 1398def : RWSysReg<"CNTHV_CTL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b001>; 1399def : RWSysReg<"SCTLR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b000>; 1400def : RWSysReg<"CPACR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b010>; 1401def : RWSysReg<"TTBR0_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b000>; 1402def : RWSysReg<"TTBR1_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b001>; 1403def : RWSysReg<"TCR_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b010>; 1404def : RWSysReg<"AFSR0_EL12", 0b11, 0b101, 0b0101, 0b0001, 0b000>; 1405def : RWSysReg<"AFSR1_EL12", 0b11, 0b101, 0b0101, 0b0001, 0b001>; 1406def : RWSysReg<"ESR_EL12", 0b11, 0b101, 0b0101, 0b0010, 0b000>; 1407def : RWSysReg<"FAR_EL12", 0b11, 0b101, 0b0110, 0b0000, 0b000>; 1408def : RWSysReg<"MAIR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b000>; 1409def : RWSysReg<"AMAIR_EL12", 0b11, 0b101, 0b1010, 0b0011, 0b000>; 1410def : RWSysReg<"VBAR_EL12", 0b11, 0b101, 0b1100, 0b0000, 0b000>; 1411def : RWSysReg<"CONTEXTIDR_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b001>; 1412def : RWSysReg<"CNTKCTL_EL12", 0b11, 0b101, 0b1110, 0b0001, 0b000>; 1413def : RWSysReg<"CNTP_TVAL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b000>; 1414def : RWSysReg<"CNTP_CTL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b001>; 1415def : RWSysReg<"CNTP_CVAL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b010>; 1416def : RWSysReg<"CNTV_TVAL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b000>; 1417def : RWSysReg<"CNTV_CTL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b001>; 1418def : RWSysReg<"CNTV_CVAL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b010>; 1419def : RWSysReg<"SPSR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b000>; 1420def : RWSysReg<"ELR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b001>; 1421let Requires = [{ {AArch64::FeatureCONTEXTIDREL2} }] in { 1422 def : RWSysReg<"CONTEXTIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b001>; 1423} 1424} 1425// v8.2a registers 1426// Op0 Op1 CRn CRm Op2 1427let Requires = [{ {AArch64::FeaturePsUAO} }] in 1428def : RWSysReg<"UAO", 0b11, 0b000, 0b0100, 0b0010, 0b100>; 1429 1430// v8.2a "Statistical Profiling extension" registers 1431// Op0 Op1 CRn CRm Op2 1432let Requires = [{ {AArch64::FeatureSPE} }] in { 1433def : RWSysReg<"PMBLIMITR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b000>; 1434def : RWSysReg<"PMBPTR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b001>; 1435def : RWSysReg<"PMBSR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b011>; 1436def : ROSysReg<"PMBIDR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b111>; 1437def : RWSysReg<"PMSCR_EL2", 0b11, 0b100, 0b1001, 0b1001, 0b000>; 1438def : RWSysReg<"PMSCR_EL12", 0b11, 0b101, 0b1001, 0b1001, 0b000>; 1439def : RWSysReg<"PMSCR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b000>; 1440def : RWSysReg<"PMSICR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b010>; 1441def : RWSysReg<"PMSIRR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b011>; 1442def : RWSysReg<"PMSFCR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b100>; 1443def : RWSysReg<"PMSEVFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b101>; 1444def : RWSysReg<"PMSLATFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b110>; 1445def : ROSysReg<"PMSIDR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b111>; 1446} 1447 1448// v8.2a "RAS extension" registers 1449// Op0 Op1 CRn CRm Op2 1450let Requires = [{ {AArch64::FeatureRAS} }] in { 1451def : RWSysReg<"ERRSELR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b001>; 1452def : RWSysReg<"ERXCTLR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b001>; 1453def : RWSysReg<"ERXSTATUS_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b010>; 1454def : RWSysReg<"ERXADDR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b011>; 1455def : RWSysReg<"ERXMISC0_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b000>; 1456def : RWSysReg<"ERXMISC1_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b001>; 1457def : RWSysReg<"DISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b001>; 1458def : RWSysReg<"VDISR_EL2", 0b11, 0b100, 0b1100, 0b0001, 0b001>; 1459def : RWSysReg<"VSESR_EL2", 0b11, 0b100, 0b0101, 0b0010, 0b011>; 1460} 1461 1462// v8.3a "Pointer authentication extension" registers 1463// Op0 Op1 CRn CRm Op2 1464let Requires = [{ {AArch64::FeaturePAuth} }] in { 1465def : RWSysReg<"APIAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b000>; 1466def : RWSysReg<"APIAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b001>; 1467def : RWSysReg<"APIBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b010>; 1468def : RWSysReg<"APIBKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b011>; 1469def : RWSysReg<"APDAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b000>; 1470def : RWSysReg<"APDAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b001>; 1471def : RWSysReg<"APDBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b010>; 1472def : RWSysReg<"APDBKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b011>; 1473def : RWSysReg<"APGAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b000>; 1474def : RWSysReg<"APGAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b001>; 1475} 1476 1477// v8.4 "Secure Exception Level 2 extension" 1478let Requires = [{ {AArch64::FeatureSEL2} }] in { 1479// v8.4a "Virtualization secure second stage translation" registers 1480// Op0 Op1 CRn CRm Op2 1481def : RWSysReg<"VSTCR_EL2" , 0b11, 0b100, 0b0010, 0b0110, 0b010>; 1482def : RWSysReg<"VSTTBR_EL2", 0b11, 0b100, 0b0010, 0b0110, 0b000> { 1483 let Requires = [{ {AArch64::HasV8_0aOps} }]; 1484} 1485 1486// v8.4a "Virtualization timer" registers 1487// Op0 Op1 CRn CRm Op2 1488def : RWSysReg<"CNTHVS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b000>; 1489def : RWSysReg<"CNTHVS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b010>; 1490def : RWSysReg<"CNTHVS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b001>; 1491def : RWSysReg<"CNTHPS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b000>; 1492def : RWSysReg<"CNTHPS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b010>; 1493def : RWSysReg<"CNTHPS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b001>; 1494 1495// v8.4a "Virtualization debug state" registers 1496// Op0 Op1 CRn CRm Op2 1497def : RWSysReg<"SDER32_EL2", 0b11, 0b100, 0b0001, 0b0011, 0b001>; 1498} // FeatureSEL2 1499 1500// v8.4a RAS registers 1501// Op0 Op1 CRn CRm Op2 1502def : RWSysReg<"ERXPFGCTL_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b101>; 1503def : RWSysReg<"ERXPFGCDN_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b110>; 1504def : RWSysReg<"ERXMISC2_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b010>; 1505def : RWSysReg<"ERXMISC3_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b011>; 1506def : ROSysReg<"ERXPFGF_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b100>; 1507 1508// v8.4a MPAM registers 1509// Op0 Op1 CRn CRm Op2 1510let Requires = [{ {AArch64::FeatureMPAM} }] in { 1511def : RWSysReg<"MPAM0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b001>; 1512def : RWSysReg<"MPAM1_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b000>; 1513def : RWSysReg<"MPAM2_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b000>; 1514def : RWSysReg<"MPAM3_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b000>; 1515def : RWSysReg<"MPAM1_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b000>; 1516def : RWSysReg<"MPAMHCR_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b000>; 1517def : RWSysReg<"MPAMVPMV_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b001>; 1518def : RWSysReg<"MPAMVPM0_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b000>; 1519def : RWSysReg<"MPAMVPM1_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b001>; 1520def : RWSysReg<"MPAMVPM2_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b010>; 1521def : RWSysReg<"MPAMVPM3_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b011>; 1522def : RWSysReg<"MPAMVPM4_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b100>; 1523def : RWSysReg<"MPAMVPM5_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b101>; 1524def : RWSysReg<"MPAMVPM6_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b110>; 1525def : RWSysReg<"MPAMVPM7_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b111>; 1526def : ROSysReg<"MPAMIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b100>; 1527} //FeatureMPAM 1528 1529// v8.4a Activity Monitor registers 1530// Op0 Op1 CRn CRm Op2 1531let Requires = [{ {AArch64::FeatureAM} }] in { 1532def : RWSysReg<"AMCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b000>; 1533def : ROSysReg<"AMCFGR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b001>; 1534def : ROSysReg<"AMCGCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b010>; 1535def : RWSysReg<"AMUSERENR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b011>; 1536def : RWSysReg<"AMCNTENCLR0_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b100>; 1537def : RWSysReg<"AMCNTENSET0_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b101>; 1538def : RWSysReg<"AMEVCNTR00_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b000>; 1539def : RWSysReg<"AMEVCNTR01_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b001>; 1540def : RWSysReg<"AMEVCNTR02_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b010>; 1541def : RWSysReg<"AMEVCNTR03_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b011>; 1542def : ROSysReg<"AMEVTYPER00_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b000>; 1543def : ROSysReg<"AMEVTYPER01_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b001>; 1544def : ROSysReg<"AMEVTYPER02_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b010>; 1545def : ROSysReg<"AMEVTYPER03_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b011>; 1546def : RWSysReg<"AMCNTENCLR1_EL0", 0b11, 0b011, 0b1101, 0b0011, 0b000>; 1547def : RWSysReg<"AMCNTENSET1_EL0", 0b11, 0b011, 0b1101, 0b0011, 0b001>; 1548def : RWSysReg<"AMEVCNTR10_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b000>; 1549def : RWSysReg<"AMEVCNTR11_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b001>; 1550def : RWSysReg<"AMEVCNTR12_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b010>; 1551def : RWSysReg<"AMEVCNTR13_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b011>; 1552def : RWSysReg<"AMEVCNTR14_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b100>; 1553def : RWSysReg<"AMEVCNTR15_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b101>; 1554def : RWSysReg<"AMEVCNTR16_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b110>; 1555def : RWSysReg<"AMEVCNTR17_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b111>; 1556def : RWSysReg<"AMEVCNTR18_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b000>; 1557def : RWSysReg<"AMEVCNTR19_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b001>; 1558def : RWSysReg<"AMEVCNTR110_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b010>; 1559def : RWSysReg<"AMEVCNTR111_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b011>; 1560def : RWSysReg<"AMEVCNTR112_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b100>; 1561def : RWSysReg<"AMEVCNTR113_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b101>; 1562def : RWSysReg<"AMEVCNTR114_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b110>; 1563def : RWSysReg<"AMEVCNTR115_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b111>; 1564def : RWSysReg<"AMEVTYPER10_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b000>; 1565def : RWSysReg<"AMEVTYPER11_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b001>; 1566def : RWSysReg<"AMEVTYPER12_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b010>; 1567def : RWSysReg<"AMEVTYPER13_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b011>; 1568def : RWSysReg<"AMEVTYPER14_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b100>; 1569def : RWSysReg<"AMEVTYPER15_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b101>; 1570def : RWSysReg<"AMEVTYPER16_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b110>; 1571def : RWSysReg<"AMEVTYPER17_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b111>; 1572def : RWSysReg<"AMEVTYPER18_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b000>; 1573def : RWSysReg<"AMEVTYPER19_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b001>; 1574def : RWSysReg<"AMEVTYPER110_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b010>; 1575def : RWSysReg<"AMEVTYPER111_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b011>; 1576def : RWSysReg<"AMEVTYPER112_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b100>; 1577def : RWSysReg<"AMEVTYPER113_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b101>; 1578def : RWSysReg<"AMEVTYPER114_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b110>; 1579def : RWSysReg<"AMEVTYPER115_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b111>; 1580} //FeatureAM 1581 1582// v8.4a Trace Extension registers 1583// 1584// Please note that the 8.4 spec also defines these registers: 1585// TRCIDR1, ID_DFR0_EL1, ID_AA64DFR0_EL1, MDSCR_EL1, MDCR_EL2, and MDCR_EL3, 1586// but they are already defined above. 1587// 1588// Op0 Op1 CRn CRm Op2 1589let Requires = [{ {AArch64::FeatureTRACEV8_4} }] in { 1590def : RWSysReg<"TRFCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b001>; 1591def : RWSysReg<"TRFCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b001>; 1592def : RWSysReg<"TRFCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b001>; 1593} //FeatureTRACEV8_4 1594 1595// v8.4a Timing insensitivity of data processing instructions 1596// DIT: Data Independent Timing instructions 1597// Op0 Op1 CRn CRm Op2 1598let Requires = [{ {AArch64::FeatureDIT} }] in { 1599def : RWSysReg<"DIT", 0b11, 0b011, 0b0100, 0b0010, 0b101>; 1600} //FeatureDIT 1601 1602// v8.4a Enhanced Support for Nested Virtualization 1603// Op0 Op1 CRn CRm Op2 1604let Requires = [{ {AArch64::FeatureNV} }] in { 1605def : RWSysReg<"VNCR_EL2", 0b11, 0b100, 0b0010, 0b0010, 0b000>; 1606} //FeatureNV 1607 1608// SVE control registers 1609// Op0 Op1 CRn CRm Op2 1610let Requires = [{ {AArch64::FeatureSVE} }] in { 1611def : RWSysReg<"ZCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b000>; 1612def : RWSysReg<"ZCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b000>; 1613def : RWSysReg<"ZCR_EL3", 0b11, 0b110, 0b0001, 0b0010, 0b000>; 1614def : RWSysReg<"ZCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b000>; 1615} 1616 1617// V8.5a Spectre mitigation SSBS register 1618// Op0 Op1 CRn CRm Op2 1619let Requires = [{ {AArch64::FeatureSSBS} }] in 1620def : RWSysReg<"SSBS", 0b11, 0b011, 0b0100, 0b0010, 0b110>; 1621 1622// v8.5a Memory Tagging Extension 1623// Op0 Op1 CRn CRm Op2 1624let Requires = [{ {AArch64::FeatureMTE} }] in { 1625def : RWSysReg<"TCO", 0b11, 0b011, 0b0100, 0b0010, 0b111>; 1626def : RWSysReg<"GCR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b110>; 1627def : RWSysReg<"RGSR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b101>; 1628def : RWSysReg<"TFSR_EL1", 0b11, 0b000, 0b0101, 0b0110, 0b000>; 1629def : RWSysReg<"TFSR_EL2", 0b11, 0b100, 0b0101, 0b0110, 0b000>; 1630def : RWSysReg<"TFSR_EL3", 0b11, 0b110, 0b0101, 0b0110, 0b000>; 1631def : RWSysReg<"TFSR_EL12", 0b11, 0b101, 0b0101, 0b0110, 0b000>; 1632def : RWSysReg<"TFSRE0_EL1", 0b11, 0b000, 0b0101, 0b0110, 0b001>; 1633def : ROSysReg<"GMID_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b100>; 1634} // HasMTE 1635 1636// Embedded Trace Extension R/W System registers 1637let Requires = [{ {AArch64::FeatureETE} }] in { 1638// Name Op0 Op1 CRn CRm Op2 1639def : RWSysReg<"TRCRSR", 0b10, 0b001, 0b0000, 0b1010, 0b000>; 1640// TRCEXTINSELR0 has the same encoding as ETM TRCEXTINSELR 1641def : RWSysReg<"TRCEXTINSELR0", 0b10, 0b001, 0b0000, 0b1000, 0b100>; 1642def : RWSysReg<"TRCEXTINSELR1", 0b10, 0b001, 0b0000, 0b1001, 0b100>; 1643def : RWSysReg<"TRCEXTINSELR2", 0b10, 0b001, 0b0000, 0b1010, 0b100>; 1644def : RWSysReg<"TRCEXTINSELR3", 0b10, 0b001, 0b0000, 0b1011, 0b100>; 1645} // FeatureETE 1646 1647// Trace Buffer Extension System registers 1648let Requires = [{ {AArch64::FeatureTRBE} }] in { 1649// Name Op0 Op1 CRn CRm Op2 1650def : RWSysReg<"TRBLIMITR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b000>; 1651def : RWSysReg<"TRBPTR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b001>; 1652def : RWSysReg<"TRBBASER_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b010>; 1653def : RWSysReg<"TRBSR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b011>; 1654def : RWSysReg<"TRBMAR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b100>; 1655def : RWSysReg<"TRBTRG_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b110>; 1656def : ROSysReg<"TRBIDR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b111>; 1657} // FeatureTRBE 1658 1659 1660// v8.6a Activity Monitors Virtualization Support 1661let Requires = [{ {AArch64::FeatureAMVS} }] in { 1662// Name Op0 Op1 CRn CRm Op2 1663def : ROSysReg<"AMCG1IDR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b110>; 1664foreach n = 0-15 in { 1665 foreach x = 0-1 in { 1666 def : RWSysReg<"AMEVCNTVOFF"#x#n#"_EL2", 1667 0b11, 0b100, 0b1101, 0b1000, 0b000>{ 1668 let Encoding{4} = x; 1669 let Encoding{3-0} = n; 1670 } 1671 } 1672} 1673} 1674 1675// v8.6a Fine Grained Virtualization Traps 1676// Op0 Op1 CRn CRm Op2 1677let Requires = [{ {AArch64::FeatureFineGrainedTraps} }] in { 1678def : RWSysReg<"HFGRTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b100>; 1679def : RWSysReg<"HFGWTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b101>; 1680def : RWSysReg<"HFGITR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b110>; 1681def : RWSysReg<"HDFGRTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b100>; 1682def : RWSysReg<"HDFGWTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b101>; 1683def : RWSysReg<"HAFGRTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b110>; 1684 1685// v8.9a/v9.4a additions to Fine Grained Traps (FEAT_FGT2) 1686// Op0 Op1 CRn CRm Op2 1687def : RWSysReg<"HDFGRTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b000>; 1688def : RWSysReg<"HDFGWTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b001>; 1689def : RWSysReg<"HFGRTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b010>; 1690def : RWSysReg<"HFGWTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b011>; 1691def : RWSysReg<"HFGITR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b111>; 1692} 1693 1694// v8.6a Enhanced Counter Virtualization 1695// Op0 Op1 CRn CRm Op2 1696let Requires = [{ {AArch64::FeatureEnhancedCounterVirtualization} }] in { 1697def : RWSysReg<"CNTSCALE_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b100>; 1698def : RWSysReg<"CNTISCALE_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b101>; 1699def : RWSysReg<"CNTPOFF_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b110>; 1700def : RWSysReg<"CNTVFRQ_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b111>; 1701def : ROSysReg<"CNTPCTSS_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b101>; 1702def : ROSysReg<"CNTVCTSS_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b110>; 1703} 1704 1705// v8.7a LD64B/ST64B Accelerator Extension system register 1706let Requires = [{ {AArch64::FeatureLS64} }] in 1707def : RWSysReg<"ACCDATA_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b101>; 1708 1709// Branch Record Buffer system registers 1710let Requires = [{ {AArch64::FeatureBRBE} }] in { 1711def : RWSysReg<"BRBCR_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b000>; 1712def : RWSysReg<"BRBCR_EL12", 0b10, 0b101, 0b1001, 0b0000, 0b000>; 1713def : RWSysReg<"BRBCR_EL2", 0b10, 0b100, 0b1001, 0b0000, 0b000>; 1714def : RWSysReg<"BRBFCR_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b001>; 1715def : ROSysReg<"BRBIDR0_EL1", 0b10, 0b001, 0b1001, 0b0010, 0b000>; 1716def : RWSysReg<"BRBINFINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b000>; 1717def : RWSysReg<"BRBSRCINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b001>; 1718def : RWSysReg<"BRBTGTINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b010>; 1719def : RWSysReg<"BRBTS_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b010>; 1720foreach n = 0-31 in { 1721 defvar nb = !cast<bits<5>>(n); 1722 def : ROSysReg<"BRBINF"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b00}>; 1723 def : ROSysReg<"BRBSRC"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b01}>; 1724 def : ROSysReg<"BRBTGT"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b10}>; 1725} 1726} 1727 1728// Statistical Profiling Extension system register 1729let Requires = [{ {AArch64::FeatureSPE_EEF} }] in 1730def : RWSysReg<"PMSNEVFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b001>; 1731 1732// Cyclone specific system registers 1733// Op0 Op1 CRn CRm Op2 1734let Requires = [{ {AArch64::FeatureAppleA7SysReg} }] in 1735def : RWSysReg<"CPM_IOACC_CTL_EL3", 0b11, 0b111, 0b1111, 0b0010, 0b000>; 1736 1737// Scalable Matrix Extension (SME) 1738// Op0 Op1 CRn CRm Op2 1739let Requires = [{ {AArch64::FeatureSME} }] in { 1740def : RWSysReg<"SMCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b110>; 1741def : RWSysReg<"SMCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b110>; 1742def : RWSysReg<"SMCR_EL3", 0b11, 0b110, 0b0001, 0b0010, 0b110>; 1743def : RWSysReg<"SMCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b110>; 1744def : RWSysReg<"SVCR", 0b11, 0b011, 0b0100, 0b0010, 0b010>; 1745def : RWSysReg<"SMPRI_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b100>; 1746def : RWSysReg<"SMPRIMAP_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b101>; 1747def : ROSysReg<"SMIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b110>; 1748def : RWSysReg<"TPIDR2_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b101>; 1749} // HasSME 1750 1751// v8.4a MPAM and SME registers 1752// Op0 Op1 CRn CRm Op2 1753let Requires = [{ {AArch64::FeatureMPAM, AArch64::FeatureSME} }] in { 1754def : RWSysReg<"MPAMSM_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b011>; 1755} // HasMPAM, HasSME 1756 1757// v8.8a Non-Maskable Interrupts 1758let Requires = [{ {AArch64::FeatureNMI} }] in { 1759 // Op0 Op1 CRn CRm Op2 1760 def : RWSysReg<"ALLINT", 0b11, 0b000, 0b0100, 0b0011, 0b000>; 1761 def : ROSysReg<"ICC_NMIAR1_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b101>; // FEAT_GICv3_NMI 1762} 1763 1764// v8.9a/v9.4a Memory Attribute Index Enhancement (FEAT_AIE) 1765// Op0 Op1 CRn CRm Op2 1766def : RWSysReg<"AMAIR2_EL1", 0b11, 0b000, 0b1010, 0b0011, 0b001>; 1767def : RWSysReg<"AMAIR2_EL12", 0b11, 0b101, 0b1010, 0b0011, 0b001>; 1768def : RWSysReg<"AMAIR2_EL2", 0b11, 0b100, 0b1010, 0b0011, 0b001>; 1769def : RWSysReg<"AMAIR2_EL3", 0b11, 0b110, 0b1010, 0b0011, 0b001>; 1770def : RWSysReg<"MAIR2_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b001>; 1771def : RWSysReg<"MAIR2_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b001>; 1772def : RWSysReg<"MAIR2_EL2", 0b11, 0b100, 0b1010, 0b0001, 0b001>; 1773def : RWSysReg<"MAIR2_EL3", 0b11, 0b110, 0b1010, 0b0001, 0b001>; 1774 1775// v8.9a/9.4a Stage 1 Permission Indirection Extension (FEAT_S1PIE) 1776// Op0 Op1 CRn CRm Op2 1777def : RWSysReg<"PIRE0_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b010>; 1778def : RWSysReg<"PIRE0_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b010>; 1779def : RWSysReg<"PIRE0_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b010>; 1780def : RWSysReg<"PIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b011>; 1781def : RWSysReg<"PIR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b011>; 1782def : RWSysReg<"PIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b011>; 1783def : RWSysReg<"PIR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b011>; 1784 1785// v8.9a/v9.4a Stage 2 Permission Indirection Extension (FEAT_S2PIE) 1786// Op0 Op1 CRn CRm Op2 1787def : RWSysReg<"S2PIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b101>; 1788 1789// v8.9a/v9.4a Stage 1 Permission Overlay Extension (FEAT_S1POE) 1790// Op0 Op1 CRn CRm Op2 1791def : RWSysReg<"POR_EL0", 0b11, 0b011, 0b1010, 0b0010, 0b100>; 1792def : RWSysReg<"POR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b100>; 1793def : RWSysReg<"POR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b100>; 1794def : RWSysReg<"POR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b100>; 1795def : RWSysReg<"POR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b100>; 1796 1797// v8.9a/v9.4a Stage 2 Permission Overlay Extension (FEAT_S2POE) 1798// Op0 Op1 CRn CRm Op2 1799def : RWSysReg<"S2POR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b101>; 1800 1801// v8.9a/v9.4a Extension to System Control Registers (FEAT_SCTLR2) 1802// Op0 Op1 CRn CRm Op2 1803def : RWSysReg<"SCTLR2_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b011>; 1804def : RWSysReg<"SCTLR2_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b011>; 1805def : RWSysReg<"SCTLR2_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b011>; 1806def : RWSysReg<"SCTLR2_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b011>; 1807 1808// v8.9a/v9.4a Extension to Translation Control Registers (FEAT_TCR2) 1809// Op0 Op1 CRn CRm Op2 1810def : RWSysReg<"TCR2_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b011>; 1811def : RWSysReg<"TCR2_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b011>; 1812def : RWSysReg<"TCR2_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b011>; 1813 1814// v8.9a/9.4a Translation Hardening Extension (FEAT_THE) 1815// Op0 Op1 CRn CRm Op2 1816let Requires = [{ {AArch64::FeatureTHE} }] in { 1817def : RWSysReg<"RCWMASK_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b110>; 1818def : RWSysReg<"RCWSMASK_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b011>; 1819} 1820 1821// v8.9a/9.4a new Debug feature (FEAT_DEBUGv8p9) 1822// Op0 Op1 CRn CRm Op2 1823def : RWSysReg<"MDSELR_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b010>; 1824 1825// v8.9a/9.4a new Performance Monitors Extension (FEAT_PMUv3p9) 1826// Op0 Op1 CRn CRm Op2 1827def : RWSysReg<"PMUACR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b100>; 1828 1829// v8.9a/9.4a PMU Snapshot Extension (FEAT_PMUv3_SS) 1830// Op0 Op1 CRn CRm Op2 1831def : ROSysReg<"PMCCNTSVR_EL1", 0b10, 0b000, 0b1110, 0b1011, 0b111>; 1832def : ROSysReg<"PMICNTSVR_EL1", 0b10, 0b000, 0b1110, 0b1100, 0b000>; 1833def : RWSysReg<"PMSSCR_EL1", 0b11, 0b000, 0b1001, 0b1101, 0b011>; 1834foreach n = 0-30 in { 1835 defvar nb = !cast<bits<5>>(n); 1836 def : ROSysReg<"PMEVCNTSVR"#n#"_EL1", 0b10, 0b000, 0b1110, {0b10,nb{4-3}}, nb{2-0}>; 1837} 1838 1839// v8.9a/v9.4a PMUv3 Fixed-function instruction counter (FEAT_PMUv3_ICNTR) 1840// Op0 Op1 CRn CRm Op2 1841def : RWSysReg<"PMICNTR_EL0", 0b11, 0b011, 0b1001, 0b0100, 0b000>; 1842def : RWSysReg<"PMICFILTR_EL0", 0b11, 0b011, 0b1001, 0b0110, 0b000>; 1843 1844// v8.9a/v9.4a PMUv3 Performance Monitors Zero with Mask (FEAT_PMUv3p9/FEAT_PMUv3_ICNTR) 1845// Op0 Op1 CRn CRm Op2 1846def : WOSysReg<"PMZR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b100>; 1847 1848// v8.9a/9.4a Synchronous-Exception-Based Event Profiling extension (FEAT_SEBEP) 1849// Op0 Op1 CRn CRm Op2 1850def : RWSysReg<"PMECR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b101>; 1851def : RWSysReg<"PMIAR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b111>; 1852 1853// v8.9a/9.4a System Performance Monitors Extension (FEAT_SPMU) 1854// Op0 Op1 CRn CRm Op2 1855def : RWSysReg<"SPMACCESSR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b011>; 1856def : RWSysReg<"SPMACCESSR_EL12", 0b10, 0b101, 0b1001, 0b1101, 0b011>; 1857def : RWSysReg<"SPMACCESSR_EL2", 0b10, 0b100, 0b1001, 0b1101, 0b011>; 1858def : RWSysReg<"SPMACCESSR_EL3", 0b10, 0b110, 0b1001, 0b1101, 0b011>; 1859def : RWSysReg<"SPMCNTENCLR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b010>; 1860def : RWSysReg<"SPMCNTENSET_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b001>; 1861def : RWSysReg<"SPMCR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b000>; 1862def : ROSysReg<"SPMDEVAFF_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b110>; 1863def : ROSysReg<"SPMDEVARCH_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b101>; 1864foreach n = 0-15 in { 1865 defvar nb = !cast<bits<4>>(n); 1866 // Op0 Op1 CRn CRm Op2 1867 def : RWSysReg<"SPMEVCNTR"#n#"_EL0", 0b10, 0b011, 0b1110, {0b000,nb{3}}, nb{2-0}>; 1868 def : RWSysReg<"SPMEVFILT2R"#n#"_EL0", 0b10, 0b011, 0b1110, {0b011,nb{3}}, nb{2-0}>; 1869 def : RWSysReg<"SPMEVFILTR"#n#"_EL0", 0b10, 0b011, 0b1110, {0b010,nb{3}}, nb{2-0}>; 1870 def : RWSysReg<"SPMEVTYPER"#n#"_EL0", 0b10, 0b011, 0b1110, {0b001,nb{3}}, nb{2-0}>; 1871} 1872// Op0 Op1 CRn CRm Op2 1873def : ROSysReg<"SPMIIDR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b100>; 1874def : RWSysReg<"SPMINTENCLR_EL1", 0b10, 0b000, 0b1001, 0b1110, 0b010>; 1875def : RWSysReg<"SPMINTENSET_EL1", 0b10, 0b000, 0b1001, 0b1110, 0b001>; 1876def : RWSysReg<"SPMOVSCLR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b011>; 1877def : RWSysReg<"SPMOVSSET_EL0", 0b10, 0b011, 0b1001, 0b1110, 0b011>; 1878def : RWSysReg<"SPMSELR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b101>; 1879def : ROSysReg<"SPMCGCR0_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b000>; 1880def : ROSysReg<"SPMCGCR1_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b001>; 1881def : ROSysReg<"SPMCFGR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b111>; 1882def : RWSysReg<"SPMROOTCR_EL3", 0b10, 0b110, 0b1001, 0b1110, 0b111>; 1883def : RWSysReg<"SPMSCR_EL1", 0b10, 0b111, 0b1001, 0b1110, 0b111>; 1884 1885// v8.9a/9.4a Instrumentation Extension (FEAT_ITE) 1886// Op0 Op1 CRn CRm Op2 1887let Requires = [{ {AArch64::FeatureITE} }] in { 1888def : RWSysReg<"TRCITEEDCR", 0b10, 0b001, 0b0000, 0b0010, 0b001>; 1889def : RWSysReg<"TRCITECR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b011>; 1890def : RWSysReg<"TRCITECR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b011>; 1891def : RWSysReg<"TRCITECR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b011>; 1892} 1893 1894// v8.9a/9.4a SPE Data Source Filtering (FEAT_SPE_FDS) 1895// Op0 Op1 CRn CRm Op2 1896def : RWSysReg<"PMSDSFR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b100>; 1897 1898// v8.9a/9.4a RASv2 (FEAT_RASv2) 1899// Op0 Op1 CRn CRm Op2 1900let Requires = [{ {AArch64::FeatureRASv2} }] in 1901def : ROSysReg<"ERXGSR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b010>; 1902 1903// v8.9a/9.4a Physical Fault Address (FEAT_PFAR) 1904// Op0 Op1 CRn CRm Op2 1905def : RWSysReg<"PFAR_EL1", 0b11, 0b000, 0b0110, 0b0000, 0b101>; 1906def : RWSysReg<"PFAR_EL12", 0b11, 0b101, 0b0110, 0b0000, 0b101>; 1907def : RWSysReg<"PFAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b101>; 1908 1909// v9.4a Exception-based event profiling (FEAT_EBEP) 1910// Op0 Op1 CRn CRm Op2 1911def : RWSysReg<"PM", 0b11, 0b000, 0b0100, 0b0011, 0b001>; 1912