1//===- AArch64SystemOperands.td ----------------------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the symbolic operands permitted for various kinds of 10// AArch64 system instruction. 11// 12//===----------------------------------------------------------------------===// 13 14include "llvm/TableGen/SearchableTable.td" 15 16//===----------------------------------------------------------------------===// 17// Features that, for the compiler, only enable system operands and PStates 18//===----------------------------------------------------------------------===// 19 20def HasCCPP : Predicate<"Subtarget->hasCCPP()">, 21 AssemblerPredicateWithAll<(all_of FeatureCCPP), "ccpp">; 22 23def HasPAN : Predicate<"Subtarget->hasPAN()">, 24 AssemblerPredicateWithAll<(all_of FeaturePAN), 25 "ARM v8.1 Privileged Access-Never extension">; 26 27def HasPsUAO : Predicate<"Subtarget->hasPsUAO()">, 28 AssemblerPredicateWithAll<(all_of FeaturePsUAO), 29 "ARM v8.2 UAO PState extension (psuao)">; 30 31def HasPAN_RWV : Predicate<"Subtarget->hasPAN_RWV()">, 32 AssemblerPredicateWithAll<(all_of FeaturePAN_RWV), 33 "ARM v8.2 PAN AT S1E1R and AT S1E1W Variation">; 34 35def HasCONTEXTIDREL2 36 : Predicate<"Subtarget->hasCONTEXTIDREL2()">, 37 AssemblerPredicateWithAll<(all_of FeatureCONTEXTIDREL2), 38 "Target contains CONTEXTIDR_EL2 RW operand">; 39 40//===----------------------------------------------------------------------===// 41// AT (address translate) instruction options. 42//===----------------------------------------------------------------------===// 43 44class AT<string name, bits<3> op1, bits<4> crn, bits<4> crm, 45 bits<3> op2> : SearchableTable { 46 let SearchableFields = ["Name", "Encoding"]; 47 let EnumValueField = "Encoding"; 48 49 string Name = name; 50 bits<14> Encoding; 51 let Encoding{13-11} = op1; 52 let Encoding{10-7} = crn; 53 let Encoding{6-3} = crm; 54 let Encoding{2-0} = op2; 55 code Requires = [{ {} }]; 56} 57 58def : AT<"S1E1R", 0b000, 0b0111, 0b1000, 0b000>; 59def : AT<"S1E2R", 0b100, 0b0111, 0b1000, 0b000>; 60def : AT<"S1E3R", 0b110, 0b0111, 0b1000, 0b000>; 61def : AT<"S1E1W", 0b000, 0b0111, 0b1000, 0b001>; 62def : AT<"S1E2W", 0b100, 0b0111, 0b1000, 0b001>; 63def : AT<"S1E3W", 0b110, 0b0111, 0b1000, 0b001>; 64def : AT<"S1E0R", 0b000, 0b0111, 0b1000, 0b010>; 65def : AT<"S1E0W", 0b000, 0b0111, 0b1000, 0b011>; 66def : AT<"S12E1R", 0b100, 0b0111, 0b1000, 0b100>; 67def : AT<"S12E1W", 0b100, 0b0111, 0b1000, 0b101>; 68def : AT<"S12E0R", 0b100, 0b0111, 0b1000, 0b110>; 69def : AT<"S12E0W", 0b100, 0b0111, 0b1000, 0b111>; 70 71let Requires = [{ {AArch64::FeaturePAN_RWV} }] in { 72def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>; 73def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>; 74} 75 76//===----------------------------------------------------------------------===// 77// DMB/DSB (data barrier) instruction options. 78//===----------------------------------------------------------------------===// 79 80class DB<string name, bits<4> encoding> : SearchableTable { 81 let SearchableFields = ["Name", "Encoding"]; 82 let EnumValueField = "Encoding"; 83 84 string Name = name; 85 bits<4> Encoding = encoding; 86} 87 88def : DB<"oshld", 0x1>; 89def : DB<"oshst", 0x2>; 90def : DB<"osh", 0x3>; 91def : DB<"nshld", 0x5>; 92def : DB<"nshst", 0x6>; 93def : DB<"nsh", 0x7>; 94def : DB<"ishld", 0x9>; 95def : DB<"ishst", 0xa>; 96def : DB<"ish", 0xb>; 97def : DB<"ld", 0xd>; 98def : DB<"st", 0xe>; 99def : DB<"sy", 0xf>; 100 101class DBnXS<string name, bits<4> encoding, bits<5> immValue> : SearchableTable { 102 let SearchableFields = ["Name", "Encoding", "ImmValue"]; 103 let EnumValueField = "Encoding"; 104 105 string Name = name; 106 bits<4> Encoding = encoding; 107 bits<5> ImmValue = immValue; 108 code Requires = [{ {AArch64::FeatureXS} }]; 109} 110 111def : DBnXS<"oshnxs", 0x3, 0x10>; 112def : DBnXS<"nshnxs", 0x7, 0x14>; 113def : DBnXS<"ishnxs", 0xb, 0x18>; 114def : DBnXS<"synxs", 0xf, 0x1c>; 115 116//===----------------------------------------------------------------------===// 117// DC (data cache maintenance) instruction options. 118//===----------------------------------------------------------------------===// 119 120class DC<string name, bits<3> op1, bits<4> crn, bits<4> crm, 121 bits<3> op2> : SearchableTable { 122 let SearchableFields = ["Name", "Encoding"]; 123 let EnumValueField = "Encoding"; 124 125 string Name = name; 126 bits<14> Encoding; 127 let Encoding{13-11} = op1; 128 let Encoding{10-7} = crn; 129 let Encoding{6-3} = crm; 130 let Encoding{2-0} = op2; 131 code Requires = [{ {} }]; 132} 133 134def : DC<"ZVA", 0b011, 0b0111, 0b0100, 0b001>; 135def : DC<"IVAC", 0b000, 0b0111, 0b0110, 0b001>; 136def : DC<"ISW", 0b000, 0b0111, 0b0110, 0b010>; 137def : DC<"CVAC", 0b011, 0b0111, 0b1010, 0b001>; 138def : DC<"CSW", 0b000, 0b0111, 0b1010, 0b010>; 139def : DC<"CVAU", 0b011, 0b0111, 0b1011, 0b001>; 140def : DC<"CIVAC", 0b011, 0b0111, 0b1110, 0b001>; 141def : DC<"CISW", 0b000, 0b0111, 0b1110, 0b010>; 142 143let Requires = [{ {AArch64::FeatureCCPP} }] in 144def : DC<"CVAP", 0b011, 0b0111, 0b1100, 0b001>; 145 146let Requires = [{ {AArch64::FeatureCacheDeepPersist} }] in 147def : DC<"CVADP", 0b011, 0b0111, 0b1101, 0b001>; 148 149let Requires = [{ {AArch64::FeatureMTE} }] in { 150def : DC<"IGVAC", 0b000, 0b0111, 0b0110, 0b011>; 151def : DC<"IGSW", 0b000, 0b0111, 0b0110, 0b100>; 152def : DC<"CGSW", 0b000, 0b0111, 0b1010, 0b100>; 153def : DC<"CIGSW", 0b000, 0b0111, 0b1110, 0b100>; 154def : DC<"CGVAC", 0b011, 0b0111, 0b1010, 0b011>; 155def : DC<"CGVAP", 0b011, 0b0111, 0b1100, 0b011>; 156def : DC<"CGVADP", 0b011, 0b0111, 0b1101, 0b011>; 157def : DC<"CIGVAC", 0b011, 0b0111, 0b1110, 0b011>; 158def : DC<"GVA", 0b011, 0b0111, 0b0100, 0b011>; 159def : DC<"IGDVAC", 0b000, 0b0111, 0b0110, 0b101>; 160def : DC<"IGDSW", 0b000, 0b0111, 0b0110, 0b110>; 161def : DC<"CGDSW", 0b000, 0b0111, 0b1010, 0b110>; 162def : DC<"CIGDSW", 0b000, 0b0111, 0b1110, 0b110>; 163def : DC<"CGDVAC", 0b011, 0b0111, 0b1010, 0b101>; 164def : DC<"CGDVAP", 0b011, 0b0111, 0b1100, 0b101>; 165def : DC<"CGDVADP", 0b011, 0b0111, 0b1101, 0b101>; 166def : DC<"CIGDVAC", 0b011, 0b0111, 0b1110, 0b101>; 167def : DC<"GZVA", 0b011, 0b0111, 0b0100, 0b100>; 168} 169 170//===----------------------------------------------------------------------===// 171// IC (instruction cache maintenance) instruction options. 172//===----------------------------------------------------------------------===// 173 174class IC<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2, 175 bit needsreg> : SearchableTable { 176 let SearchableFields = ["Name", "Encoding"]; 177 let EnumValueField = "Encoding"; 178 179 string Name = name; 180 bits<14> Encoding; 181 let Encoding{13-11} = op1; 182 let Encoding{10-7} = crn; 183 let Encoding{6-3} = crm; 184 let Encoding{2-0} = op2; 185 bit NeedsReg = needsreg; 186} 187 188def : IC<"IALLUIS", 0b000, 0b0111, 0b0001, 0b000, 0>; 189def : IC<"IALLU", 0b000, 0b0111, 0b0101, 0b000, 0>; 190def : IC<"IVAU", 0b011, 0b0111, 0b0101, 0b001, 1>; 191 192//===----------------------------------------------------------------------===// 193// ISB (instruction-fetch barrier) instruction options. 194//===----------------------------------------------------------------------===// 195 196class ISB<string name, bits<4> encoding> : SearchableTable{ 197 let SearchableFields = ["Name", "Encoding"]; 198 let EnumValueField = "Encoding"; 199 200 string Name = name; 201 bits<4> Encoding; 202 let Encoding = encoding; 203} 204 205def : ISB<"sy", 0xf>; 206 207//===----------------------------------------------------------------------===// 208// TSB (Trace synchronization barrier) instruction options. 209//===----------------------------------------------------------------------===// 210 211class TSB<string name, bits<4> encoding> : SearchableTable{ 212 let SearchableFields = ["Name", "Encoding"]; 213 let EnumValueField = "Encoding"; 214 215 string Name = name; 216 bits<4> Encoding; 217 let Encoding = encoding; 218 219 code Requires = [{ {AArch64::FeatureTRACEV8_4} }]; 220} 221 222def : TSB<"csync", 0>; 223 224//===----------------------------------------------------------------------===// 225// PRFM (prefetch) instruction options. 226//===----------------------------------------------------------------------===// 227 228class PRFM<string name, bits<5> encoding> : SearchableTable { 229 let SearchableFields = ["Name", "Encoding"]; 230 let EnumValueField = "Encoding"; 231 232 string Name = name; 233 bits<5> Encoding; 234 let Encoding = encoding; 235} 236 237def : PRFM<"pldl1keep", 0x00>; 238def : PRFM<"pldl1strm", 0x01>; 239def : PRFM<"pldl2keep", 0x02>; 240def : PRFM<"pldl2strm", 0x03>; 241def : PRFM<"pldl3keep", 0x04>; 242def : PRFM<"pldl3strm", 0x05>; 243def : PRFM<"plil1keep", 0x08>; 244def : PRFM<"plil1strm", 0x09>; 245def : PRFM<"plil2keep", 0x0a>; 246def : PRFM<"plil2strm", 0x0b>; 247def : PRFM<"plil3keep", 0x0c>; 248def : PRFM<"plil3strm", 0x0d>; 249def : PRFM<"pstl1keep", 0x10>; 250def : PRFM<"pstl1strm", 0x11>; 251def : PRFM<"pstl2keep", 0x12>; 252def : PRFM<"pstl2strm", 0x13>; 253def : PRFM<"pstl3keep", 0x14>; 254def : PRFM<"pstl3strm", 0x15>; 255 256//===----------------------------------------------------------------------===// 257// SVE Prefetch instruction options. 258//===----------------------------------------------------------------------===// 259 260class SVEPRFM<string name, bits<4> encoding> : SearchableTable { 261 let SearchableFields = ["Name", "Encoding"]; 262 let EnumValueField = "Encoding"; 263 264 string Name = name; 265 bits<4> Encoding; 266 let Encoding = encoding; 267 code Requires = [{ {} }]; 268} 269 270let Requires = [{ {AArch64::FeatureSVE} }] in { 271def : SVEPRFM<"pldl1keep", 0x00>; 272def : SVEPRFM<"pldl1strm", 0x01>; 273def : SVEPRFM<"pldl2keep", 0x02>; 274def : SVEPRFM<"pldl2strm", 0x03>; 275def : SVEPRFM<"pldl3keep", 0x04>; 276def : SVEPRFM<"pldl3strm", 0x05>; 277def : SVEPRFM<"pstl1keep", 0x08>; 278def : SVEPRFM<"pstl1strm", 0x09>; 279def : SVEPRFM<"pstl2keep", 0x0a>; 280def : SVEPRFM<"pstl2strm", 0x0b>; 281def : SVEPRFM<"pstl3keep", 0x0c>; 282def : SVEPRFM<"pstl3strm", 0x0d>; 283} 284 285//===----------------------------------------------------------------------===// 286// SVE Predicate patterns 287//===----------------------------------------------------------------------===// 288 289class SVEPREDPAT<string name, bits<5> encoding> : SearchableTable { 290 let SearchableFields = ["Name", "Encoding"]; 291 let EnumValueField = "Encoding"; 292 293 string Name = name; 294 bits<5> Encoding; 295 let Encoding = encoding; 296} 297 298def : SVEPREDPAT<"pow2", 0x00>; 299def : SVEPREDPAT<"vl1", 0x01>; 300def : SVEPREDPAT<"vl2", 0x02>; 301def : SVEPREDPAT<"vl3", 0x03>; 302def : SVEPREDPAT<"vl4", 0x04>; 303def : SVEPREDPAT<"vl5", 0x05>; 304def : SVEPREDPAT<"vl6", 0x06>; 305def : SVEPREDPAT<"vl7", 0x07>; 306def : SVEPREDPAT<"vl8", 0x08>; 307def : SVEPREDPAT<"vl16", 0x09>; 308def : SVEPREDPAT<"vl32", 0x0a>; 309def : SVEPREDPAT<"vl64", 0x0b>; 310def : SVEPREDPAT<"vl128", 0x0c>; 311def : SVEPREDPAT<"vl256", 0x0d>; 312def : SVEPREDPAT<"mul4", 0x1d>; 313def : SVEPREDPAT<"mul3", 0x1e>; 314def : SVEPREDPAT<"all", 0x1f>; 315 316//===----------------------------------------------------------------------===// 317// Exact FP Immediates. 318// 319// These definitions are used to create a lookup table with FP Immediates that 320// is used for a few instructions that only accept a limited set of exact FP 321// immediates values. 322//===----------------------------------------------------------------------===// 323class ExactFPImm<string name, string repr, bits<4> enum > : SearchableTable { 324 let SearchableFields = ["Enum", "Repr"]; 325 let EnumValueField = "Enum"; 326 327 string Name = name; 328 bits<4> Enum = enum; 329 string Repr = repr; 330} 331 332def : ExactFPImm<"zero", "0.0", 0x0>; 333def : ExactFPImm<"half", "0.5", 0x1>; 334def : ExactFPImm<"one", "1.0", 0x2>; 335def : ExactFPImm<"two", "2.0", 0x3>; 336 337//===----------------------------------------------------------------------===// 338// PState instruction options. 339//===----------------------------------------------------------------------===// 340 341class PState<string name, bits<5> encoding> : SearchableTable { 342 let SearchableFields = ["Name", "Encoding"]; 343 let EnumValueField = "Encoding"; 344 345 string Name = name; 346 bits<5> Encoding; 347 let Encoding = encoding; 348 code Requires = [{ {} }]; 349} 350 351def : PState<"SPSel", 0b00101>; 352def : PState<"DAIFSet", 0b11110>; 353def : PState<"DAIFClr", 0b11111>; 354// v8.1a "Privileged Access Never" extension-specific PStates 355let Requires = [{ {AArch64::FeaturePAN} }] in 356def : PState<"PAN", 0b00100>; 357 358// v8.2a "User Access Override" extension-specific PStates 359let Requires = [{ {AArch64::FeaturePsUAO} }] in 360def : PState<"UAO", 0b00011>; 361// v8.4a timing insensitivity of data processing instructions 362let Requires = [{ {AArch64::FeatureDIT} }] in 363def : PState<"DIT", 0b11010>; 364// v8.5a Spectre Mitigation 365let Requires = [{ {AArch64::FeatureSSBS} }] in 366def : PState<"SSBS", 0b11001>; 367// v8.5a Memory Tagging Extension 368let Requires = [{ {AArch64::FeatureMTE} }] in 369def : PState<"TCO", 0b11100>; 370 371//===----------------------------------------------------------------------===// 372// SVCR instruction options. 373//===----------------------------------------------------------------------===// 374 375class SVCR<string name, bits<3> encoding> : SearchableTable { 376 let SearchableFields = ["Name", "Encoding"]; 377 let EnumValueField = "Encoding"; 378 379 string Name = name; 380 bits<3> Encoding; 381 let Encoding = encoding; 382 code Requires = [{ {} }]; 383} 384 385let Requires = [{ {AArch64::FeatureSME} }] in { 386def : SVCR<"SVCRSM", 0b001>; 387def : SVCR<"SVCRZA", 0b010>; 388def : SVCR<"SVCRSMZA", 0b011>; 389} 390 391//===----------------------------------------------------------------------===// 392// PSB instruction options. 393//===----------------------------------------------------------------------===// 394 395class PSB<string name, bits<5> encoding> : SearchableTable { 396 let SearchableFields = ["Name", "Encoding"]; 397 let EnumValueField = "Encoding"; 398 399 string Name = name; 400 bits<5> Encoding; 401 let Encoding = encoding; 402} 403 404def : PSB<"csync", 0x11>; 405 406//===----------------------------------------------------------------------===// 407// BTI instruction options. 408//===----------------------------------------------------------------------===// 409 410class BTI<string name, bits<3> encoding> : SearchableTable { 411 let SearchableFields = ["Name", "Encoding"]; 412 let EnumValueField = "Encoding"; 413 414 string Name = name; 415 bits<3> Encoding; 416 let Encoding = encoding; 417} 418 419def : BTI<"c", 0b010>; 420def : BTI<"j", 0b100>; 421def : BTI<"jc", 0b110>; 422 423//===----------------------------------------------------------------------===// 424// TLBI (translation lookaside buffer invalidate) instruction options. 425//===----------------------------------------------------------------------===// 426 427class TLBIEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm, 428 bits<3> op2, bit needsreg> { 429 string Name = name; 430 bits<14> Encoding; 431 let Encoding{13-11} = op1; 432 let Encoding{10-7} = crn; 433 let Encoding{6-3} = crm; 434 let Encoding{2-0} = op2; 435 bit NeedsReg = needsreg; 436 list<string> Requires = []; 437 list<string> ExtraRequires = []; 438 code RequiresStr = [{ { }] # !interleave(Requires # ExtraRequires, [{, }]) # [{ } }]; 439} 440 441def TLBITable : GenericTable { 442 let FilterClass = "TLBIEntry"; 443 let CppTypeName = "TLBI"; 444 let Fields = ["Name", "Encoding", "NeedsReg", "RequiresStr"]; 445} 446 447def lookupTLBIByName : SearchIndex { 448 let Table = TLBITable; 449 let Key = ["Name"]; 450} 451 452def lookupTLBIByEncoding : SearchIndex { 453 let Table = TLBITable; 454 let Key = ["Encoding"]; 455} 456 457multiclass TLBI<string name, bits<3> op1, bits<4> crn, bits<4> crm, 458 bits<3> op2, bit needsreg = 1> { 459 def : TLBIEntry<name, op1, crn, crm, op2, needsreg>; 460 def : TLBIEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, needsreg> { 461 let Encoding{7} = 1; 462 let ExtraRequires = ["AArch64::FeatureXS"]; 463 } 464} 465 466defm : TLBI<"IPAS2E1IS", 0b100, 0b1000, 0b0000, 0b001>; 467defm : TLBI<"IPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b101>; 468defm : TLBI<"VMALLE1IS", 0b000, 0b1000, 0b0011, 0b000, 0>; 469defm : TLBI<"ALLE2IS", 0b100, 0b1000, 0b0011, 0b000, 0>; 470defm : TLBI<"ALLE3IS", 0b110, 0b1000, 0b0011, 0b000, 0>; 471defm : TLBI<"VAE1IS", 0b000, 0b1000, 0b0011, 0b001>; 472defm : TLBI<"VAE2IS", 0b100, 0b1000, 0b0011, 0b001>; 473defm : TLBI<"VAE3IS", 0b110, 0b1000, 0b0011, 0b001>; 474defm : TLBI<"ASIDE1IS", 0b000, 0b1000, 0b0011, 0b010>; 475defm : TLBI<"VAAE1IS", 0b000, 0b1000, 0b0011, 0b011>; 476defm : TLBI<"ALLE1IS", 0b100, 0b1000, 0b0011, 0b100, 0>; 477defm : TLBI<"VALE1IS", 0b000, 0b1000, 0b0011, 0b101>; 478defm : TLBI<"VALE2IS", 0b100, 0b1000, 0b0011, 0b101>; 479defm : TLBI<"VALE3IS", 0b110, 0b1000, 0b0011, 0b101>; 480defm : TLBI<"VMALLS12E1IS", 0b100, 0b1000, 0b0011, 0b110, 0>; 481defm : TLBI<"VAALE1IS", 0b000, 0b1000, 0b0011, 0b111>; 482defm : TLBI<"IPAS2E1", 0b100, 0b1000, 0b0100, 0b001>; 483defm : TLBI<"IPAS2LE1", 0b100, 0b1000, 0b0100, 0b101>; 484defm : TLBI<"VMALLE1", 0b000, 0b1000, 0b0111, 0b000, 0>; 485defm : TLBI<"ALLE2", 0b100, 0b1000, 0b0111, 0b000, 0>; 486defm : TLBI<"ALLE3", 0b110, 0b1000, 0b0111, 0b000, 0>; 487defm : TLBI<"VAE1", 0b000, 0b1000, 0b0111, 0b001>; 488defm : TLBI<"VAE2", 0b100, 0b1000, 0b0111, 0b001>; 489defm : TLBI<"VAE3", 0b110, 0b1000, 0b0111, 0b001>; 490defm : TLBI<"ASIDE1", 0b000, 0b1000, 0b0111, 0b010>; 491defm : TLBI<"VAAE1", 0b000, 0b1000, 0b0111, 0b011>; 492defm : TLBI<"ALLE1", 0b100, 0b1000, 0b0111, 0b100, 0>; 493defm : TLBI<"VALE1", 0b000, 0b1000, 0b0111, 0b101>; 494defm : TLBI<"VALE2", 0b100, 0b1000, 0b0111, 0b101>; 495defm : TLBI<"VALE3", 0b110, 0b1000, 0b0111, 0b101>; 496defm : TLBI<"VMALLS12E1", 0b100, 0b1000, 0b0111, 0b110, 0>; 497defm : TLBI<"VAALE1", 0b000, 0b1000, 0b0111, 0b111>; 498 499// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI) 500let Requires = ["AArch64::FeatureTLB_RMI"] in { 501// Armv8.4-A Outer Sharable TLB Maintenance instructions: 502// op1 CRn CRm op2 503defm : TLBI<"VMALLE1OS", 0b000, 0b1000, 0b0001, 0b000, 0>; 504defm : TLBI<"VAE1OS", 0b000, 0b1000, 0b0001, 0b001>; 505defm : TLBI<"ASIDE1OS", 0b000, 0b1000, 0b0001, 0b010>; 506defm : TLBI<"VAAE1OS", 0b000, 0b1000, 0b0001, 0b011>; 507defm : TLBI<"VALE1OS", 0b000, 0b1000, 0b0001, 0b101>; 508defm : TLBI<"VAALE1OS", 0b000, 0b1000, 0b0001, 0b111>; 509defm : TLBI<"IPAS2E1OS", 0b100, 0b1000, 0b0100, 0b000>; 510defm : TLBI<"IPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b100>; 511defm : TLBI<"VAE2OS", 0b100, 0b1000, 0b0001, 0b001>; 512defm : TLBI<"VALE2OS", 0b100, 0b1000, 0b0001, 0b101>; 513defm : TLBI<"VMALLS12E1OS", 0b100, 0b1000, 0b0001, 0b110, 0>; 514defm : TLBI<"VAE3OS", 0b110, 0b1000, 0b0001, 0b001>; 515defm : TLBI<"VALE3OS", 0b110, 0b1000, 0b0001, 0b101>; 516defm : TLBI<"ALLE2OS", 0b100, 0b1000, 0b0001, 0b000, 0>; 517defm : TLBI<"ALLE1OS", 0b100, 0b1000, 0b0001, 0b100, 0>; 518defm : TLBI<"ALLE3OS", 0b110, 0b1000, 0b0001, 0b000, 0>; 519 520// Armv8.4-A TLB Range Maintenance instructions: 521// op1 CRn CRm op2 522defm : TLBI<"RVAE1", 0b000, 0b1000, 0b0110, 0b001>; 523defm : TLBI<"RVAAE1", 0b000, 0b1000, 0b0110, 0b011>; 524defm : TLBI<"RVALE1", 0b000, 0b1000, 0b0110, 0b101>; 525defm : TLBI<"RVAALE1", 0b000, 0b1000, 0b0110, 0b111>; 526defm : TLBI<"RVAE1IS", 0b000, 0b1000, 0b0010, 0b001>; 527defm : TLBI<"RVAAE1IS", 0b000, 0b1000, 0b0010, 0b011>; 528defm : TLBI<"RVALE1IS", 0b000, 0b1000, 0b0010, 0b101>; 529defm : TLBI<"RVAALE1IS", 0b000, 0b1000, 0b0010, 0b111>; 530defm : TLBI<"RVAE1OS", 0b000, 0b1000, 0b0101, 0b001>; 531defm : TLBI<"RVAAE1OS", 0b000, 0b1000, 0b0101, 0b011>; 532defm : TLBI<"RVALE1OS", 0b000, 0b1000, 0b0101, 0b101>; 533defm : TLBI<"RVAALE1OS", 0b000, 0b1000, 0b0101, 0b111>; 534defm : TLBI<"RIPAS2E1IS", 0b100, 0b1000, 0b0000, 0b010>; 535defm : TLBI<"RIPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b110>; 536defm : TLBI<"RIPAS2E1", 0b100, 0b1000, 0b0100, 0b010>; 537defm : TLBI<"RIPAS2LE1", 0b100, 0b1000, 0b0100, 0b110>; 538defm : TLBI<"RIPAS2E1OS", 0b100, 0b1000, 0b0100, 0b011>; 539defm : TLBI<"RIPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b111>; 540defm : TLBI<"RVAE2", 0b100, 0b1000, 0b0110, 0b001>; 541defm : TLBI<"RVALE2", 0b100, 0b1000, 0b0110, 0b101>; 542defm : TLBI<"RVAE2IS", 0b100, 0b1000, 0b0010, 0b001>; 543defm : TLBI<"RVALE2IS", 0b100, 0b1000, 0b0010, 0b101>; 544defm : TLBI<"RVAE2OS", 0b100, 0b1000, 0b0101, 0b001>; 545defm : TLBI<"RVALE2OS", 0b100, 0b1000, 0b0101, 0b101>; 546defm : TLBI<"RVAE3", 0b110, 0b1000, 0b0110, 0b001>; 547defm : TLBI<"RVALE3", 0b110, 0b1000, 0b0110, 0b101>; 548defm : TLBI<"RVAE3IS", 0b110, 0b1000, 0b0010, 0b001>; 549defm : TLBI<"RVALE3IS", 0b110, 0b1000, 0b0010, 0b101>; 550defm : TLBI<"RVAE3OS", 0b110, 0b1000, 0b0101, 0b001>; 551defm : TLBI<"RVALE3OS", 0b110, 0b1000, 0b0101, 0b101>; 552} //FeatureTLB_RMI 553 554// Armv9-A Realm Management Extention TLBI Instructions 555let Requires = ["AArch64::FeatureRME"] in { 556defm : TLBI<"RPAOS", 0b110, 0b1000, 0b0100, 0b011>; 557defm : TLBI<"RPALOS", 0b110, 0b1000, 0b0100, 0b111>; 558defm : TLBI<"PAALLOS", 0b110, 0b1000, 0b0001, 0b100, 0>; 559defm : TLBI<"PAALL", 0b110, 0b1000, 0b0111, 0b100, 0>; 560} 561 562// Armv8.5-A Prediction Restriction by Context instruction options: 563class PRCTX<string name, bits<4> crm> : SearchableTable { 564 let SearchableFields = ["Name", "Encoding"]; 565 let EnumValueField = "Encoding"; 566 567 string Name = name; 568 bits<11> Encoding; 569 let Encoding{10-4} = 0b0110111; 570 let Encoding{3-0} = crm; 571 bit NeedsReg = 1; 572 code Requires = [{ {} }]; 573} 574 575let Requires = [{ {AArch64::FeaturePredRes} }] in { 576def : PRCTX<"RCTX", 0b0011>; 577} 578 579//===----------------------------------------------------------------------===// 580// MRS/MSR (system register read/write) instruction options. 581//===----------------------------------------------------------------------===// 582 583class SysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm, 584 bits<3> op2> : SearchableTable { 585 let SearchableFields = ["Name", "Encoding"]; 586 let EnumValueField = "Encoding"; 587 588 string Name = name; 589 string AltName = name; 590 bits<16> Encoding; 591 let Encoding{15-14} = op0; 592 let Encoding{13-11} = op1; 593 let Encoding{10-7} = crn; 594 let Encoding{6-3} = crm; 595 let Encoding{2-0} = op2; 596 bit Readable = ?; 597 bit Writeable = ?; 598 code Requires = [{ {} }]; 599} 600 601class RWSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm, 602 bits<3> op2> 603 : SysReg<name, op0, op1, crn, crm, op2> { 604 let Readable = 1; 605 let Writeable = 1; 606} 607 608class ROSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm, 609 bits<3> op2> 610 : SysReg<name, op0, op1, crn, crm, op2> { 611 let Readable = 1; 612 let Writeable = 0; 613} 614 615class WOSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm, 616 bits<3> op2> 617 : SysReg<name, op0, op1, crn, crm, op2> { 618 let Readable = 0; 619 let Writeable = 1; 620} 621 622//===---------------------- 623// Read-only regs 624//===---------------------- 625 626// Op0 Op1 CRn CRm Op2 627def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>; 628def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>; 629def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>; 630def : ROSysReg<"OSLSR_EL1", 0b10, 0b000, 0b0001, 0b0001, 0b100>; 631def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b10, 0b000, 0b0111, 0b1110, 0b110>; 632def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>; 633def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>; 634def : ROSysReg<"PMMIR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b110>; 635def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>; 636def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>; 637 638//v8.3 CCIDX - extending the CCsIDr number of sets 639def : ROSysReg<"CCSIDR2_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b010> { 640 let Requires = [{ {AArch64::FeatureCCIDX} }]; 641} 642def : ROSysReg<"CLIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b001>; 643def : ROSysReg<"CTR_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b001>; 644def : ROSysReg<"MPIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b101>; 645def : ROSysReg<"REVIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b110>; 646def : ROSysReg<"AIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b111>; 647def : ROSysReg<"DCZID_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b111>; 648def : ROSysReg<"ID_PFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b000>; 649def : ROSysReg<"ID_PFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b001>; 650def : ROSysReg<"ID_PFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b100> { 651 let Requires = [{ {AArch64::FeatureSpecRestrict} }]; 652} 653def : ROSysReg<"ID_DFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b010>; 654def : ROSysReg<"ID_AFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b011>; 655def : ROSysReg<"ID_MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b100>; 656def : ROSysReg<"ID_MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b101>; 657def : ROSysReg<"ID_MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b110>; 658def : ROSysReg<"ID_MMFR3_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b111>; 659def : ROSysReg<"ID_ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b000>; 660def : ROSysReg<"ID_ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b001>; 661def : ROSysReg<"ID_ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b010>; 662def : ROSysReg<"ID_ISAR3_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b011>; 663def : ROSysReg<"ID_ISAR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b100>; 664def : ROSysReg<"ID_ISAR5_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b101>; 665def : ROSysReg<"ID_ISAR6_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b111> { 666 let Requires = [{ {AArch64::HasV8_2aOps} }]; 667} 668def : ROSysReg<"ID_AA64PFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b000>; 669def : ROSysReg<"ID_AA64PFR1_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b001>; 670def : ROSysReg<"ID_AA64DFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b000>; 671def : ROSysReg<"ID_AA64DFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b001>; 672def : ROSysReg<"ID_AA64AFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b100>; 673def : ROSysReg<"ID_AA64AFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b101>; 674def : ROSysReg<"ID_AA64ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b000>; 675def : ROSysReg<"ID_AA64ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b001>; 676def : ROSysReg<"ID_AA64ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b010>; 677def : ROSysReg<"ID_AA64MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b000>; 678def : ROSysReg<"ID_AA64MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b001>; 679def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010>; 680def : ROSysReg<"MVFR0_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b000>; 681def : ROSysReg<"MVFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b001>; 682def : ROSysReg<"MVFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b010>; 683def : ROSysReg<"RVBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b001>; 684def : ROSysReg<"RVBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b001>; 685def : ROSysReg<"RVBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b001>; 686def : ROSysReg<"ISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b000>; 687def : ROSysReg<"CNTPCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b001>; 688def : ROSysReg<"CNTVCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b010>; 689def : ROSysReg<"ID_MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b110>; 690def : ROSysReg<"ID_MMFR5_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b110>; 691 692// Trace registers 693// Op0 Op1 CRn CRm Op2 694def : ROSysReg<"TRCSTATR", 0b10, 0b001, 0b0000, 0b0011, 0b000>; 695def : ROSysReg<"TRCIDR8", 0b10, 0b001, 0b0000, 0b0000, 0b110>; 696def : ROSysReg<"TRCIDR9", 0b10, 0b001, 0b0000, 0b0001, 0b110>; 697def : ROSysReg<"TRCIDR10", 0b10, 0b001, 0b0000, 0b0010, 0b110>; 698def : ROSysReg<"TRCIDR11", 0b10, 0b001, 0b0000, 0b0011, 0b110>; 699def : ROSysReg<"TRCIDR12", 0b10, 0b001, 0b0000, 0b0100, 0b110>; 700def : ROSysReg<"TRCIDR13", 0b10, 0b001, 0b0000, 0b0101, 0b110>; 701def : ROSysReg<"TRCIDR0", 0b10, 0b001, 0b0000, 0b1000, 0b111>; 702def : ROSysReg<"TRCIDR1", 0b10, 0b001, 0b0000, 0b1001, 0b111>; 703def : ROSysReg<"TRCIDR2", 0b10, 0b001, 0b0000, 0b1010, 0b111>; 704def : ROSysReg<"TRCIDR3", 0b10, 0b001, 0b0000, 0b1011, 0b111>; 705def : ROSysReg<"TRCIDR4", 0b10, 0b001, 0b0000, 0b1100, 0b111>; 706def : ROSysReg<"TRCIDR5", 0b10, 0b001, 0b0000, 0b1101, 0b111>; 707def : ROSysReg<"TRCIDR6", 0b10, 0b001, 0b0000, 0b1110, 0b111>; 708def : ROSysReg<"TRCIDR7", 0b10, 0b001, 0b0000, 0b1111, 0b111>; 709def : ROSysReg<"TRCOSLSR", 0b10, 0b001, 0b0001, 0b0001, 0b100>; 710def : ROSysReg<"TRCPDSR", 0b10, 0b001, 0b0001, 0b0101, 0b100>; 711def : ROSysReg<"TRCDEVAFF0", 0b10, 0b001, 0b0111, 0b1010, 0b110>; 712def : ROSysReg<"TRCDEVAFF1", 0b10, 0b001, 0b0111, 0b1011, 0b110>; 713def : ROSysReg<"TRCLSR", 0b10, 0b001, 0b0111, 0b1101, 0b110>; 714def : ROSysReg<"TRCAUTHSTATUS", 0b10, 0b001, 0b0111, 0b1110, 0b110>; 715def : ROSysReg<"TRCDEVARCH", 0b10, 0b001, 0b0111, 0b1111, 0b110>; 716def : ROSysReg<"TRCDEVID", 0b10, 0b001, 0b0111, 0b0010, 0b111>; 717def : ROSysReg<"TRCDEVTYPE", 0b10, 0b001, 0b0111, 0b0011, 0b111>; 718def : ROSysReg<"TRCPIDR4", 0b10, 0b001, 0b0111, 0b0100, 0b111>; 719def : ROSysReg<"TRCPIDR5", 0b10, 0b001, 0b0111, 0b0101, 0b111>; 720def : ROSysReg<"TRCPIDR6", 0b10, 0b001, 0b0111, 0b0110, 0b111>; 721def : ROSysReg<"TRCPIDR7", 0b10, 0b001, 0b0111, 0b0111, 0b111>; 722def : ROSysReg<"TRCPIDR0", 0b10, 0b001, 0b0111, 0b1000, 0b111>; 723def : ROSysReg<"TRCPIDR1", 0b10, 0b001, 0b0111, 0b1001, 0b111>; 724def : ROSysReg<"TRCPIDR2", 0b10, 0b001, 0b0111, 0b1010, 0b111>; 725def : ROSysReg<"TRCPIDR3", 0b10, 0b001, 0b0111, 0b1011, 0b111>; 726def : ROSysReg<"TRCCIDR0", 0b10, 0b001, 0b0111, 0b1100, 0b111>; 727def : ROSysReg<"TRCCIDR1", 0b10, 0b001, 0b0111, 0b1101, 0b111>; 728def : ROSysReg<"TRCCIDR2", 0b10, 0b001, 0b0111, 0b1110, 0b111>; 729def : ROSysReg<"TRCCIDR3", 0b10, 0b001, 0b0111, 0b1111, 0b111>; 730 731// GICv3 registers 732// Op0 Op1 CRn CRm Op2 733def : ROSysReg<"ICC_IAR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b000>; 734def : ROSysReg<"ICC_IAR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b000>; 735def : ROSysReg<"ICC_HPPIR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b010>; 736def : ROSysReg<"ICC_HPPIR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b010>; 737def : ROSysReg<"ICC_RPR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b011>; 738def : ROSysReg<"ICH_VTR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b001>; 739def : ROSysReg<"ICH_EISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b011>; 740def : ROSysReg<"ICH_ELRSR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b101>; 741 742// SVE control registers 743// Op0 Op1 CRn CRm Op2 744let Requires = [{ {AArch64::FeatureSVE} }] in { 745def : ROSysReg<"ID_AA64ZFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b100>; 746} 747 748// v8.1a "Limited Ordering Regions" extension-specific system register 749// Op0 Op1 CRn CRm Op2 750let Requires = [{ {AArch64::FeatureLOR} }] in 751def : ROSysReg<"LORID_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b111>; 752 753// v8.2a "RAS extension" registers 754// Op0 Op1 CRn CRm Op2 755let Requires = [{ {AArch64::FeatureRAS} }] in { 756def : ROSysReg<"ERRIDR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b000>; 757def : ROSysReg<"ERXFR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b000>; 758} 759 760// v8.5a "random number" registers 761// Op0 Op1 CRn CRm Op2 762let Requires = [{ {AArch64::FeatureRandGen} }] in { 763def : ROSysReg<"RNDR", 0b11, 0b011, 0b0010, 0b0100, 0b000>; 764def : ROSysReg<"RNDRRS", 0b11, 0b011, 0b0010, 0b0100, 0b001>; 765} 766 767// v8.5a Software Context Number registers 768let Requires = [{ {AArch64::FeatureSpecRestrict} }] in { 769def : RWSysReg<"SCXTNUM_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b111>; 770def : RWSysReg<"SCXTNUM_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b111>; 771def : RWSysReg<"SCXTNUM_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b111>; 772def : RWSysReg<"SCXTNUM_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b111>; 773def : RWSysReg<"SCXTNUM_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b111>; 774} 775 776// v9a Realm Management Extension registers 777let Requires = [{ {AArch64::FeatureRME} }] in { 778def : RWSysReg<"MFAR_EL3", 0b11, 0b110, 0b0110, 0b0000, 0b101>; 779def : RWSysReg<"GPCCR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b110>; 780def : RWSysReg<"GPTBR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b100>; 781} 782 783// v9-a Scalable Matrix Extension (SME) registers 784// Op0 Op1 CRn CRm Op2 785let Requires = [{ {AArch64::FeatureSME} }] in { 786def : ROSysReg<"ID_AA64SMFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b101>; 787} 788 789//===---------------------- 790// Write-only regs 791//===---------------------- 792 793// Op0 Op1 CRn CRm Op2 794def : WOSysReg<"DBGDTRTX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>; 795def : WOSysReg<"OSLAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b100>; 796def : WOSysReg<"PMSWINC_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b100>; 797 798// Trace Registers 799// Op0 Op1 CRn CRm Op2 800def : WOSysReg<"TRCOSLAR", 0b10, 0b001, 0b0001, 0b0000, 0b100>; 801def : WOSysReg<"TRCLAR", 0b10, 0b001, 0b0111, 0b1100, 0b110>; 802 803// GICv3 registers 804// Op0 Op1 CRn CRm Op2 805def : WOSysReg<"ICC_EOIR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b001>; 806def : WOSysReg<"ICC_EOIR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b001>; 807def : WOSysReg<"ICC_DIR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b001>; 808def : WOSysReg<"ICC_SGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b101>; 809def : WOSysReg<"ICC_ASGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b110>; 810def : WOSysReg<"ICC_SGI0R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b111>; 811 812//===---------------------- 813// Read-write regs 814//===---------------------- 815 816// Op0 Op1 CRn CRm Op2 817def : RWSysReg<"OSDTRRX_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b010>; 818def : RWSysReg<"OSDTRTX_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b010>; 819def : RWSysReg<"TEECR32_EL1", 0b10, 0b010, 0b0000, 0b0000, 0b000>; 820def : RWSysReg<"MDCCINT_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b000>; 821def : RWSysReg<"MDSCR_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b010>; 822def : RWSysReg<"DBGDTR_EL0", 0b10, 0b011, 0b0000, 0b0100, 0b000>; 823def : RWSysReg<"OSECCR_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b010>; 824def : RWSysReg<"DBGVCR32_EL2", 0b10, 0b100, 0b0000, 0b0111, 0b000>; 825def : RWSysReg<"DBGBVR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b100>; 826def : RWSysReg<"DBGBVR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b100>; 827def : RWSysReg<"DBGBVR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b100>; 828def : RWSysReg<"DBGBVR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b100>; 829def : RWSysReg<"DBGBVR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b100>; 830def : RWSysReg<"DBGBVR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b100>; 831def : RWSysReg<"DBGBVR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b100>; 832def : RWSysReg<"DBGBVR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b100>; 833def : RWSysReg<"DBGBVR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b100>; 834def : RWSysReg<"DBGBVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b100>; 835def : RWSysReg<"DBGBVR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b100>; 836def : RWSysReg<"DBGBVR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b100>; 837def : RWSysReg<"DBGBVR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b100>; 838def : RWSysReg<"DBGBVR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b100>; 839def : RWSysReg<"DBGBVR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b100>; 840def : RWSysReg<"DBGBVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b100>; 841def : RWSysReg<"DBGBCR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b101>; 842def : RWSysReg<"DBGBCR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b101>; 843def : RWSysReg<"DBGBCR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b101>; 844def : RWSysReg<"DBGBCR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b101>; 845def : RWSysReg<"DBGBCR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b101>; 846def : RWSysReg<"DBGBCR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b101>; 847def : RWSysReg<"DBGBCR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b101>; 848def : RWSysReg<"DBGBCR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b101>; 849def : RWSysReg<"DBGBCR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b101>; 850def : RWSysReg<"DBGBCR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b101>; 851def : RWSysReg<"DBGBCR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b101>; 852def : RWSysReg<"DBGBCR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b101>; 853def : RWSysReg<"DBGBCR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b101>; 854def : RWSysReg<"DBGBCR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b101>; 855def : RWSysReg<"DBGBCR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b101>; 856def : RWSysReg<"DBGBCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b101>; 857def : RWSysReg<"DBGWVR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b110>; 858def : RWSysReg<"DBGWVR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b110>; 859def : RWSysReg<"DBGWVR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b110>; 860def : RWSysReg<"DBGWVR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b110>; 861def : RWSysReg<"DBGWVR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b110>; 862def : RWSysReg<"DBGWVR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b110>; 863def : RWSysReg<"DBGWVR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b110>; 864def : RWSysReg<"DBGWVR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b110>; 865def : RWSysReg<"DBGWVR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b110>; 866def : RWSysReg<"DBGWVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b110>; 867def : RWSysReg<"DBGWVR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b110>; 868def : RWSysReg<"DBGWVR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b110>; 869def : RWSysReg<"DBGWVR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b110>; 870def : RWSysReg<"DBGWVR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b110>; 871def : RWSysReg<"DBGWVR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b110>; 872def : RWSysReg<"DBGWVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b110>; 873def : RWSysReg<"DBGWCR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b111>; 874def : RWSysReg<"DBGWCR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b111>; 875def : RWSysReg<"DBGWCR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b111>; 876def : RWSysReg<"DBGWCR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b111>; 877def : RWSysReg<"DBGWCR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b111>; 878def : RWSysReg<"DBGWCR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b111>; 879def : RWSysReg<"DBGWCR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b111>; 880def : RWSysReg<"DBGWCR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b111>; 881def : RWSysReg<"DBGWCR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b111>; 882def : RWSysReg<"DBGWCR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b111>; 883def : RWSysReg<"DBGWCR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b111>; 884def : RWSysReg<"DBGWCR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b111>; 885def : RWSysReg<"DBGWCR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b111>; 886def : RWSysReg<"DBGWCR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b111>; 887def : RWSysReg<"DBGWCR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b111>; 888def : RWSysReg<"DBGWCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b111>; 889def : RWSysReg<"TEEHBR32_EL1", 0b10, 0b010, 0b0001, 0b0000, 0b000>; 890def : RWSysReg<"OSDLR_EL1", 0b10, 0b000, 0b0001, 0b0011, 0b100>; 891def : RWSysReg<"DBGPRCR_EL1", 0b10, 0b000, 0b0001, 0b0100, 0b100>; 892def : RWSysReg<"DBGCLAIMSET_EL1", 0b10, 0b000, 0b0111, 0b1000, 0b110>; 893def : RWSysReg<"DBGCLAIMCLR_EL1", 0b10, 0b000, 0b0111, 0b1001, 0b110>; 894def : RWSysReg<"CSSELR_EL1", 0b11, 0b010, 0b0000, 0b0000, 0b000>; 895def : RWSysReg<"VPIDR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b000>; 896def : RWSysReg<"VMPIDR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b101>; 897def : RWSysReg<"CPACR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b010>; 898def : RWSysReg<"SCTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b000>; 899def : RWSysReg<"SCTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b000>; 900def : RWSysReg<"SCTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b000>; 901def : RWSysReg<"ACTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b001>; 902def : RWSysReg<"ACTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b001>; 903def : RWSysReg<"ACTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b001>; 904def : RWSysReg<"HCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b000>; 905def : RWSysReg<"HCRX_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b010> { 906 let Requires = [{ {AArch64::FeatureHCX} }]; 907} 908def : RWSysReg<"SCR_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b000>; 909def : RWSysReg<"MDCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b001>; 910def : RWSysReg<"SDER32_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b001>; 911def : RWSysReg<"CPTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b010>; 912def : RWSysReg<"CPTR_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b010>; 913def : RWSysReg<"HSTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b011>; 914def : RWSysReg<"HACR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b111>; 915def : RWSysReg<"MDCR_EL3", 0b11, 0b110, 0b0001, 0b0011, 0b001>; 916def : RWSysReg<"TTBR0_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b000>; 917def : RWSysReg<"TTBR0_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b000>; 918 919let Requires = [{ {AArch64::FeatureEL2VMSA} }] in { 920def : RWSysReg<"TTBR0_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b000> { 921 let AltName = "VSCTLR_EL2"; 922} 923def : RWSysReg<"VTTBR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b000>; 924} 925 926def : RWSysReg<"TTBR1_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b001>; 927def : RWSysReg<"TCR_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b010>; 928def : RWSysReg<"TCR_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b010>; 929def : RWSysReg<"TCR_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b010>; 930def : RWSysReg<"VTCR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b010>; 931def : RWSysReg<"DACR32_EL2", 0b11, 0b100, 0b0011, 0b0000, 0b000>; 932def : RWSysReg<"SPSR_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b000>; 933def : RWSysReg<"SPSR_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b000>; 934def : RWSysReg<"SPSR_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b000>; 935def : RWSysReg<"ELR_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b001>; 936def : RWSysReg<"ELR_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b001>; 937def : RWSysReg<"ELR_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b001>; 938def : RWSysReg<"SP_EL0", 0b11, 0b000, 0b0100, 0b0001, 0b000>; 939def : RWSysReg<"SP_EL1", 0b11, 0b100, 0b0100, 0b0001, 0b000>; 940def : RWSysReg<"SP_EL2", 0b11, 0b110, 0b0100, 0b0001, 0b000>; 941def : RWSysReg<"SPSel", 0b11, 0b000, 0b0100, 0b0010, 0b000>; 942def : RWSysReg<"NZCV", 0b11, 0b011, 0b0100, 0b0010, 0b000>; 943def : RWSysReg<"DAIF", 0b11, 0b011, 0b0100, 0b0010, 0b001>; 944def : ROSysReg<"CurrentEL", 0b11, 0b000, 0b0100, 0b0010, 0b010>; 945def : RWSysReg<"SPSR_irq", 0b11, 0b100, 0b0100, 0b0011, 0b000>; 946def : RWSysReg<"SPSR_abt", 0b11, 0b100, 0b0100, 0b0011, 0b001>; 947def : RWSysReg<"SPSR_und", 0b11, 0b100, 0b0100, 0b0011, 0b010>; 948def : RWSysReg<"SPSR_fiq", 0b11, 0b100, 0b0100, 0b0011, 0b011>; 949def : RWSysReg<"FPCR", 0b11, 0b011, 0b0100, 0b0100, 0b000>; 950def : RWSysReg<"FPSR", 0b11, 0b011, 0b0100, 0b0100, 0b001>; 951def : RWSysReg<"DSPSR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b000>; 952def : RWSysReg<"DLR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b001>; 953def : RWSysReg<"IFSR32_EL2", 0b11, 0b100, 0b0101, 0b0000, 0b001>; 954def : RWSysReg<"AFSR0_EL1", 0b11, 0b000, 0b0101, 0b0001, 0b000>; 955def : RWSysReg<"AFSR0_EL2", 0b11, 0b100, 0b0101, 0b0001, 0b000>; 956def : RWSysReg<"AFSR0_EL3", 0b11, 0b110, 0b0101, 0b0001, 0b000>; 957def : RWSysReg<"AFSR1_EL1", 0b11, 0b000, 0b0101, 0b0001, 0b001>; 958def : RWSysReg<"AFSR1_EL2", 0b11, 0b100, 0b0101, 0b0001, 0b001>; 959def : RWSysReg<"AFSR1_EL3", 0b11, 0b110, 0b0101, 0b0001, 0b001>; 960def : RWSysReg<"ESR_EL1", 0b11, 0b000, 0b0101, 0b0010, 0b000>; 961def : RWSysReg<"ESR_EL2", 0b11, 0b100, 0b0101, 0b0010, 0b000>; 962def : RWSysReg<"ESR_EL3", 0b11, 0b110, 0b0101, 0b0010, 0b000>; 963def : RWSysReg<"FPEXC32_EL2", 0b11, 0b100, 0b0101, 0b0011, 0b000>; 964def : RWSysReg<"FAR_EL1", 0b11, 0b000, 0b0110, 0b0000, 0b000>; 965def : RWSysReg<"FAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b000>; 966def : RWSysReg<"FAR_EL3", 0b11, 0b110, 0b0110, 0b0000, 0b000>; 967def : RWSysReg<"HPFAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b100>; 968def : RWSysReg<"PAR_EL1", 0b11, 0b000, 0b0111, 0b0100, 0b000>; 969def : RWSysReg<"PMCR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b000>; 970def : RWSysReg<"PMCNTENSET_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b001>; 971def : RWSysReg<"PMCNTENCLR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b010>; 972def : RWSysReg<"PMOVSCLR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b011>; 973def : RWSysReg<"PMSELR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b101>; 974def : RWSysReg<"PMCCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b000>; 975def : RWSysReg<"PMXEVTYPER_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b001>; 976def : RWSysReg<"PMXEVCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b010>; 977def : RWSysReg<"PMUSERENR_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b000>; 978def : RWSysReg<"PMINTENSET_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b001>; 979def : RWSysReg<"PMINTENCLR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b010>; 980def : RWSysReg<"PMOVSSET_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b011>; 981def : RWSysReg<"MAIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b000>; 982def : RWSysReg<"MAIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b000>; 983def : RWSysReg<"MAIR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b000>; 984def : RWSysReg<"AMAIR_EL1", 0b11, 0b000, 0b1010, 0b0011, 0b000>; 985def : RWSysReg<"AMAIR_EL2", 0b11, 0b100, 0b1010, 0b0011, 0b000>; 986def : RWSysReg<"AMAIR_EL3", 0b11, 0b110, 0b1010, 0b0011, 0b000>; 987def : RWSysReg<"VBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b000>; 988def : RWSysReg<"VBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b000>; 989def : RWSysReg<"VBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b000>; 990def : RWSysReg<"RMR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b010>; 991def : RWSysReg<"RMR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b010>; 992def : RWSysReg<"RMR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b010>; 993def : RWSysReg<"CONTEXTIDR_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b001>; 994def : RWSysReg<"TPIDR_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b010>; 995def : RWSysReg<"TPIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b010>; 996def : RWSysReg<"TPIDR_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b010>; 997def : RWSysReg<"TPIDRRO_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b011>; 998def : RWSysReg<"TPIDR_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b100>; 999def : RWSysReg<"CNTFRQ_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b000>; 1000def : RWSysReg<"CNTVOFF_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b011>; 1001def : RWSysReg<"CNTKCTL_EL1", 0b11, 0b000, 0b1110, 0b0001, 0b000>; 1002def : RWSysReg<"CNTHCTL_EL2", 0b11, 0b100, 0b1110, 0b0001, 0b000>; 1003def : RWSysReg<"CNTP_TVAL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b000>; 1004def : RWSysReg<"CNTHP_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b000>; 1005def : RWSysReg<"CNTPS_TVAL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b000>; 1006def : RWSysReg<"CNTP_CTL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b001>; 1007def : RWSysReg<"CNTHP_CTL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b001>; 1008def : RWSysReg<"CNTPS_CTL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b001>; 1009def : RWSysReg<"CNTP_CVAL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b010>; 1010def : RWSysReg<"CNTHP_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b010>; 1011def : RWSysReg<"CNTPS_CVAL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b010>; 1012def : RWSysReg<"CNTV_TVAL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b000>; 1013def : RWSysReg<"CNTV_CTL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b001>; 1014def : RWSysReg<"CNTV_CVAL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b010>; 1015def : RWSysReg<"PMEVCNTR0_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b000>; 1016def : RWSysReg<"PMEVCNTR1_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b001>; 1017def : RWSysReg<"PMEVCNTR2_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b010>; 1018def : RWSysReg<"PMEVCNTR3_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b011>; 1019def : RWSysReg<"PMEVCNTR4_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b100>; 1020def : RWSysReg<"PMEVCNTR5_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b101>; 1021def : RWSysReg<"PMEVCNTR6_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b110>; 1022def : RWSysReg<"PMEVCNTR7_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b111>; 1023def : RWSysReg<"PMEVCNTR8_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b000>; 1024def : RWSysReg<"PMEVCNTR9_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b001>; 1025def : RWSysReg<"PMEVCNTR10_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b010>; 1026def : RWSysReg<"PMEVCNTR11_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b011>; 1027def : RWSysReg<"PMEVCNTR12_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b100>; 1028def : RWSysReg<"PMEVCNTR13_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b101>; 1029def : RWSysReg<"PMEVCNTR14_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b110>; 1030def : RWSysReg<"PMEVCNTR15_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b111>; 1031def : RWSysReg<"PMEVCNTR16_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b000>; 1032def : RWSysReg<"PMEVCNTR17_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b001>; 1033def : RWSysReg<"PMEVCNTR18_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b010>; 1034def : RWSysReg<"PMEVCNTR19_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b011>; 1035def : RWSysReg<"PMEVCNTR20_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b100>; 1036def : RWSysReg<"PMEVCNTR21_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b101>; 1037def : RWSysReg<"PMEVCNTR22_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b110>; 1038def : RWSysReg<"PMEVCNTR23_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b111>; 1039def : RWSysReg<"PMEVCNTR24_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b000>; 1040def : RWSysReg<"PMEVCNTR25_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b001>; 1041def : RWSysReg<"PMEVCNTR26_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b010>; 1042def : RWSysReg<"PMEVCNTR27_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b011>; 1043def : RWSysReg<"PMEVCNTR28_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b100>; 1044def : RWSysReg<"PMEVCNTR29_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b101>; 1045def : RWSysReg<"PMEVCNTR30_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b110>; 1046def : RWSysReg<"PMCCFILTR_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b111>; 1047def : RWSysReg<"PMEVTYPER0_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b000>; 1048def : RWSysReg<"PMEVTYPER1_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b001>; 1049def : RWSysReg<"PMEVTYPER2_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b010>; 1050def : RWSysReg<"PMEVTYPER3_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b011>; 1051def : RWSysReg<"PMEVTYPER4_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b100>; 1052def : RWSysReg<"PMEVTYPER5_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b101>; 1053def : RWSysReg<"PMEVTYPER6_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b110>; 1054def : RWSysReg<"PMEVTYPER7_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b111>; 1055def : RWSysReg<"PMEVTYPER8_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b000>; 1056def : RWSysReg<"PMEVTYPER9_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b001>; 1057def : RWSysReg<"PMEVTYPER10_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b010>; 1058def : RWSysReg<"PMEVTYPER11_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b011>; 1059def : RWSysReg<"PMEVTYPER12_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b100>; 1060def : RWSysReg<"PMEVTYPER13_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b101>; 1061def : RWSysReg<"PMEVTYPER14_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b110>; 1062def : RWSysReg<"PMEVTYPER15_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b111>; 1063def : RWSysReg<"PMEVTYPER16_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b000>; 1064def : RWSysReg<"PMEVTYPER17_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b001>; 1065def : RWSysReg<"PMEVTYPER18_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b010>; 1066def : RWSysReg<"PMEVTYPER19_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b011>; 1067def : RWSysReg<"PMEVTYPER20_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b100>; 1068def : RWSysReg<"PMEVTYPER21_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b101>; 1069def : RWSysReg<"PMEVTYPER22_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b110>; 1070def : RWSysReg<"PMEVTYPER23_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b111>; 1071def : RWSysReg<"PMEVTYPER24_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b000>; 1072def : RWSysReg<"PMEVTYPER25_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b001>; 1073def : RWSysReg<"PMEVTYPER26_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b010>; 1074def : RWSysReg<"PMEVTYPER27_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b011>; 1075def : RWSysReg<"PMEVTYPER28_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b100>; 1076def : RWSysReg<"PMEVTYPER29_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b101>; 1077def : RWSysReg<"PMEVTYPER30_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b110>; 1078 1079// Trace registers 1080// Op0 Op1 CRn CRm Op2 1081def : RWSysReg<"TRCPRGCTLR", 0b10, 0b001, 0b0000, 0b0001, 0b000>; 1082def : RWSysReg<"TRCPROCSELR", 0b10, 0b001, 0b0000, 0b0010, 0b000>; 1083def : RWSysReg<"TRCCONFIGR", 0b10, 0b001, 0b0000, 0b0100, 0b000>; 1084def : RWSysReg<"TRCAUXCTLR", 0b10, 0b001, 0b0000, 0b0110, 0b000>; 1085def : RWSysReg<"TRCEVENTCTL0R", 0b10, 0b001, 0b0000, 0b1000, 0b000>; 1086def : RWSysReg<"TRCEVENTCTL1R", 0b10, 0b001, 0b0000, 0b1001, 0b000>; 1087def : RWSysReg<"TRCSTALLCTLR", 0b10, 0b001, 0b0000, 0b1011, 0b000>; 1088def : RWSysReg<"TRCTSCTLR", 0b10, 0b001, 0b0000, 0b1100, 0b000>; 1089def : RWSysReg<"TRCSYNCPR", 0b10, 0b001, 0b0000, 0b1101, 0b000>; 1090def : RWSysReg<"TRCCCCTLR", 0b10, 0b001, 0b0000, 0b1110, 0b000>; 1091def : RWSysReg<"TRCBBCTLR", 0b10, 0b001, 0b0000, 0b1111, 0b000>; 1092def : RWSysReg<"TRCTRACEIDR", 0b10, 0b001, 0b0000, 0b0000, 0b001>; 1093def : RWSysReg<"TRCQCTLR", 0b10, 0b001, 0b0000, 0b0001, 0b001>; 1094def : RWSysReg<"TRCVICTLR", 0b10, 0b001, 0b0000, 0b0000, 0b010>; 1095def : RWSysReg<"TRCVIIECTLR", 0b10, 0b001, 0b0000, 0b0001, 0b010>; 1096def : RWSysReg<"TRCVISSCTLR", 0b10, 0b001, 0b0000, 0b0010, 0b010>; 1097def : RWSysReg<"TRCVIPCSSCTLR", 0b10, 0b001, 0b0000, 0b0011, 0b010>; 1098def : RWSysReg<"TRCVDCTLR", 0b10, 0b001, 0b0000, 0b1000, 0b010>; 1099def : RWSysReg<"TRCVDSACCTLR", 0b10, 0b001, 0b0000, 0b1001, 0b010>; 1100def : RWSysReg<"TRCVDARCCTLR", 0b10, 0b001, 0b0000, 0b1010, 0b010>; 1101def : RWSysReg<"TRCSEQEVR0", 0b10, 0b001, 0b0000, 0b0000, 0b100>; 1102def : RWSysReg<"TRCSEQEVR1", 0b10, 0b001, 0b0000, 0b0001, 0b100>; 1103def : RWSysReg<"TRCSEQEVR2", 0b10, 0b001, 0b0000, 0b0010, 0b100>; 1104def : RWSysReg<"TRCSEQRSTEVR", 0b10, 0b001, 0b0000, 0b0110, 0b100>; 1105def : RWSysReg<"TRCSEQSTR", 0b10, 0b001, 0b0000, 0b0111, 0b100>; 1106def : RWSysReg<"TRCEXTINSELR", 0b10, 0b001, 0b0000, 0b1000, 0b100>; 1107def : RWSysReg<"TRCCNTRLDVR0", 0b10, 0b001, 0b0000, 0b0000, 0b101>; 1108def : RWSysReg<"TRCCNTRLDVR1", 0b10, 0b001, 0b0000, 0b0001, 0b101>; 1109def : RWSysReg<"TRCCNTRLDVR2", 0b10, 0b001, 0b0000, 0b0010, 0b101>; 1110def : RWSysReg<"TRCCNTRLDVR3", 0b10, 0b001, 0b0000, 0b0011, 0b101>; 1111def : RWSysReg<"TRCCNTCTLR0", 0b10, 0b001, 0b0000, 0b0100, 0b101>; 1112def : RWSysReg<"TRCCNTCTLR1", 0b10, 0b001, 0b0000, 0b0101, 0b101>; 1113def : RWSysReg<"TRCCNTCTLR2", 0b10, 0b001, 0b0000, 0b0110, 0b101>; 1114def : RWSysReg<"TRCCNTCTLR3", 0b10, 0b001, 0b0000, 0b0111, 0b101>; 1115def : RWSysReg<"TRCCNTVR0", 0b10, 0b001, 0b0000, 0b1000, 0b101>; 1116def : RWSysReg<"TRCCNTVR1", 0b10, 0b001, 0b0000, 0b1001, 0b101>; 1117def : RWSysReg<"TRCCNTVR2", 0b10, 0b001, 0b0000, 0b1010, 0b101>; 1118def : RWSysReg<"TRCCNTVR3", 0b10, 0b001, 0b0000, 0b1011, 0b101>; 1119def : RWSysReg<"TRCIMSPEC0", 0b10, 0b001, 0b0000, 0b0000, 0b111>; 1120def : RWSysReg<"TRCIMSPEC1", 0b10, 0b001, 0b0000, 0b0001, 0b111>; 1121def : RWSysReg<"TRCIMSPEC2", 0b10, 0b001, 0b0000, 0b0010, 0b111>; 1122def : RWSysReg<"TRCIMSPEC3", 0b10, 0b001, 0b0000, 0b0011, 0b111>; 1123def : RWSysReg<"TRCIMSPEC4", 0b10, 0b001, 0b0000, 0b0100, 0b111>; 1124def : RWSysReg<"TRCIMSPEC5", 0b10, 0b001, 0b0000, 0b0101, 0b111>; 1125def : RWSysReg<"TRCIMSPEC6", 0b10, 0b001, 0b0000, 0b0110, 0b111>; 1126def : RWSysReg<"TRCIMSPEC7", 0b10, 0b001, 0b0000, 0b0111, 0b111>; 1127def : RWSysReg<"TRCRSCTLR2", 0b10, 0b001, 0b0001, 0b0010, 0b000>; 1128def : RWSysReg<"TRCRSCTLR3", 0b10, 0b001, 0b0001, 0b0011, 0b000>; 1129def : RWSysReg<"TRCRSCTLR4", 0b10, 0b001, 0b0001, 0b0100, 0b000>; 1130def : RWSysReg<"TRCRSCTLR5", 0b10, 0b001, 0b0001, 0b0101, 0b000>; 1131def : RWSysReg<"TRCRSCTLR6", 0b10, 0b001, 0b0001, 0b0110, 0b000>; 1132def : RWSysReg<"TRCRSCTLR7", 0b10, 0b001, 0b0001, 0b0111, 0b000>; 1133def : RWSysReg<"TRCRSCTLR8", 0b10, 0b001, 0b0001, 0b1000, 0b000>; 1134def : RWSysReg<"TRCRSCTLR9", 0b10, 0b001, 0b0001, 0b1001, 0b000>; 1135def : RWSysReg<"TRCRSCTLR10", 0b10, 0b001, 0b0001, 0b1010, 0b000>; 1136def : RWSysReg<"TRCRSCTLR11", 0b10, 0b001, 0b0001, 0b1011, 0b000>; 1137def : RWSysReg<"TRCRSCTLR12", 0b10, 0b001, 0b0001, 0b1100, 0b000>; 1138def : RWSysReg<"TRCRSCTLR13", 0b10, 0b001, 0b0001, 0b1101, 0b000>; 1139def : RWSysReg<"TRCRSCTLR14", 0b10, 0b001, 0b0001, 0b1110, 0b000>; 1140def : RWSysReg<"TRCRSCTLR15", 0b10, 0b001, 0b0001, 0b1111, 0b000>; 1141def : RWSysReg<"TRCRSCTLR16", 0b10, 0b001, 0b0001, 0b0000, 0b001>; 1142def : RWSysReg<"TRCRSCTLR17", 0b10, 0b001, 0b0001, 0b0001, 0b001>; 1143def : RWSysReg<"TRCRSCTLR18", 0b10, 0b001, 0b0001, 0b0010, 0b001>; 1144def : RWSysReg<"TRCRSCTLR19", 0b10, 0b001, 0b0001, 0b0011, 0b001>; 1145def : RWSysReg<"TRCRSCTLR20", 0b10, 0b001, 0b0001, 0b0100, 0b001>; 1146def : RWSysReg<"TRCRSCTLR21", 0b10, 0b001, 0b0001, 0b0101, 0b001>; 1147def : RWSysReg<"TRCRSCTLR22", 0b10, 0b001, 0b0001, 0b0110, 0b001>; 1148def : RWSysReg<"TRCRSCTLR23", 0b10, 0b001, 0b0001, 0b0111, 0b001>; 1149def : RWSysReg<"TRCRSCTLR24", 0b10, 0b001, 0b0001, 0b1000, 0b001>; 1150def : RWSysReg<"TRCRSCTLR25", 0b10, 0b001, 0b0001, 0b1001, 0b001>; 1151def : RWSysReg<"TRCRSCTLR26", 0b10, 0b001, 0b0001, 0b1010, 0b001>; 1152def : RWSysReg<"TRCRSCTLR27", 0b10, 0b001, 0b0001, 0b1011, 0b001>; 1153def : RWSysReg<"TRCRSCTLR28", 0b10, 0b001, 0b0001, 0b1100, 0b001>; 1154def : RWSysReg<"TRCRSCTLR29", 0b10, 0b001, 0b0001, 0b1101, 0b001>; 1155def : RWSysReg<"TRCRSCTLR30", 0b10, 0b001, 0b0001, 0b1110, 0b001>; 1156def : RWSysReg<"TRCRSCTLR31", 0b10, 0b001, 0b0001, 0b1111, 0b001>; 1157def : RWSysReg<"TRCSSCCR0", 0b10, 0b001, 0b0001, 0b0000, 0b010>; 1158def : RWSysReg<"TRCSSCCR1", 0b10, 0b001, 0b0001, 0b0001, 0b010>; 1159def : RWSysReg<"TRCSSCCR2", 0b10, 0b001, 0b0001, 0b0010, 0b010>; 1160def : RWSysReg<"TRCSSCCR3", 0b10, 0b001, 0b0001, 0b0011, 0b010>; 1161def : RWSysReg<"TRCSSCCR4", 0b10, 0b001, 0b0001, 0b0100, 0b010>; 1162def : RWSysReg<"TRCSSCCR5", 0b10, 0b001, 0b0001, 0b0101, 0b010>; 1163def : RWSysReg<"TRCSSCCR6", 0b10, 0b001, 0b0001, 0b0110, 0b010>; 1164def : RWSysReg<"TRCSSCCR7", 0b10, 0b001, 0b0001, 0b0111, 0b010>; 1165def : RWSysReg<"TRCSSCSR0", 0b10, 0b001, 0b0001, 0b1000, 0b010>; 1166def : RWSysReg<"TRCSSCSR1", 0b10, 0b001, 0b0001, 0b1001, 0b010>; 1167def : RWSysReg<"TRCSSCSR2", 0b10, 0b001, 0b0001, 0b1010, 0b010>; 1168def : RWSysReg<"TRCSSCSR3", 0b10, 0b001, 0b0001, 0b1011, 0b010>; 1169def : RWSysReg<"TRCSSCSR4", 0b10, 0b001, 0b0001, 0b1100, 0b010>; 1170def : RWSysReg<"TRCSSCSR5", 0b10, 0b001, 0b0001, 0b1101, 0b010>; 1171def : RWSysReg<"TRCSSCSR6", 0b10, 0b001, 0b0001, 0b1110, 0b010>; 1172def : RWSysReg<"TRCSSCSR7", 0b10, 0b001, 0b0001, 0b1111, 0b010>; 1173def : RWSysReg<"TRCSSPCICR0", 0b10, 0b001, 0b0001, 0b0000, 0b011>; 1174def : RWSysReg<"TRCSSPCICR1", 0b10, 0b001, 0b0001, 0b0001, 0b011>; 1175def : RWSysReg<"TRCSSPCICR2", 0b10, 0b001, 0b0001, 0b0010, 0b011>; 1176def : RWSysReg<"TRCSSPCICR3", 0b10, 0b001, 0b0001, 0b0011, 0b011>; 1177def : RWSysReg<"TRCSSPCICR4", 0b10, 0b001, 0b0001, 0b0100, 0b011>; 1178def : RWSysReg<"TRCSSPCICR5", 0b10, 0b001, 0b0001, 0b0101, 0b011>; 1179def : RWSysReg<"TRCSSPCICR6", 0b10, 0b001, 0b0001, 0b0110, 0b011>; 1180def : RWSysReg<"TRCSSPCICR7", 0b10, 0b001, 0b0001, 0b0111, 0b011>; 1181def : RWSysReg<"TRCPDCR", 0b10, 0b001, 0b0001, 0b0100, 0b100>; 1182def : RWSysReg<"TRCACVR0", 0b10, 0b001, 0b0010, 0b0000, 0b000>; 1183def : RWSysReg<"TRCACVR1", 0b10, 0b001, 0b0010, 0b0010, 0b000>; 1184def : RWSysReg<"TRCACVR2", 0b10, 0b001, 0b0010, 0b0100, 0b000>; 1185def : RWSysReg<"TRCACVR3", 0b10, 0b001, 0b0010, 0b0110, 0b000>; 1186def : RWSysReg<"TRCACVR4", 0b10, 0b001, 0b0010, 0b1000, 0b000>; 1187def : RWSysReg<"TRCACVR5", 0b10, 0b001, 0b0010, 0b1010, 0b000>; 1188def : RWSysReg<"TRCACVR6", 0b10, 0b001, 0b0010, 0b1100, 0b000>; 1189def : RWSysReg<"TRCACVR7", 0b10, 0b001, 0b0010, 0b1110, 0b000>; 1190def : RWSysReg<"TRCACVR8", 0b10, 0b001, 0b0010, 0b0000, 0b001>; 1191def : RWSysReg<"TRCACVR9", 0b10, 0b001, 0b0010, 0b0010, 0b001>; 1192def : RWSysReg<"TRCACVR10", 0b10, 0b001, 0b0010, 0b0100, 0b001>; 1193def : RWSysReg<"TRCACVR11", 0b10, 0b001, 0b0010, 0b0110, 0b001>; 1194def : RWSysReg<"TRCACVR12", 0b10, 0b001, 0b0010, 0b1000, 0b001>; 1195def : RWSysReg<"TRCACVR13", 0b10, 0b001, 0b0010, 0b1010, 0b001>; 1196def : RWSysReg<"TRCACVR14", 0b10, 0b001, 0b0010, 0b1100, 0b001>; 1197def : RWSysReg<"TRCACVR15", 0b10, 0b001, 0b0010, 0b1110, 0b001>; 1198def : RWSysReg<"TRCACATR0", 0b10, 0b001, 0b0010, 0b0000, 0b010>; 1199def : RWSysReg<"TRCACATR1", 0b10, 0b001, 0b0010, 0b0010, 0b010>; 1200def : RWSysReg<"TRCACATR2", 0b10, 0b001, 0b0010, 0b0100, 0b010>; 1201def : RWSysReg<"TRCACATR3", 0b10, 0b001, 0b0010, 0b0110, 0b010>; 1202def : RWSysReg<"TRCACATR4", 0b10, 0b001, 0b0010, 0b1000, 0b010>; 1203def : RWSysReg<"TRCACATR5", 0b10, 0b001, 0b0010, 0b1010, 0b010>; 1204def : RWSysReg<"TRCACATR6", 0b10, 0b001, 0b0010, 0b1100, 0b010>; 1205def : RWSysReg<"TRCACATR7", 0b10, 0b001, 0b0010, 0b1110, 0b010>; 1206def : RWSysReg<"TRCACATR8", 0b10, 0b001, 0b0010, 0b0000, 0b011>; 1207def : RWSysReg<"TRCACATR9", 0b10, 0b001, 0b0010, 0b0010, 0b011>; 1208def : RWSysReg<"TRCACATR10", 0b10, 0b001, 0b0010, 0b0100, 0b011>; 1209def : RWSysReg<"TRCACATR11", 0b10, 0b001, 0b0010, 0b0110, 0b011>; 1210def : RWSysReg<"TRCACATR12", 0b10, 0b001, 0b0010, 0b1000, 0b011>; 1211def : RWSysReg<"TRCACATR13", 0b10, 0b001, 0b0010, 0b1010, 0b011>; 1212def : RWSysReg<"TRCACATR14", 0b10, 0b001, 0b0010, 0b1100, 0b011>; 1213def : RWSysReg<"TRCACATR15", 0b10, 0b001, 0b0010, 0b1110, 0b011>; 1214def : RWSysReg<"TRCDVCVR0", 0b10, 0b001, 0b0010, 0b0000, 0b100>; 1215def : RWSysReg<"TRCDVCVR1", 0b10, 0b001, 0b0010, 0b0100, 0b100>; 1216def : RWSysReg<"TRCDVCVR2", 0b10, 0b001, 0b0010, 0b1000, 0b100>; 1217def : RWSysReg<"TRCDVCVR3", 0b10, 0b001, 0b0010, 0b1100, 0b100>; 1218def : RWSysReg<"TRCDVCVR4", 0b10, 0b001, 0b0010, 0b0000, 0b101>; 1219def : RWSysReg<"TRCDVCVR5", 0b10, 0b001, 0b0010, 0b0100, 0b101>; 1220def : RWSysReg<"TRCDVCVR6", 0b10, 0b001, 0b0010, 0b1000, 0b101>; 1221def : RWSysReg<"TRCDVCVR7", 0b10, 0b001, 0b0010, 0b1100, 0b101>; 1222def : RWSysReg<"TRCDVCMR0", 0b10, 0b001, 0b0010, 0b0000, 0b110>; 1223def : RWSysReg<"TRCDVCMR1", 0b10, 0b001, 0b0010, 0b0100, 0b110>; 1224def : RWSysReg<"TRCDVCMR2", 0b10, 0b001, 0b0010, 0b1000, 0b110>; 1225def : RWSysReg<"TRCDVCMR3", 0b10, 0b001, 0b0010, 0b1100, 0b110>; 1226def : RWSysReg<"TRCDVCMR4", 0b10, 0b001, 0b0010, 0b0000, 0b111>; 1227def : RWSysReg<"TRCDVCMR5", 0b10, 0b001, 0b0010, 0b0100, 0b111>; 1228def : RWSysReg<"TRCDVCMR6", 0b10, 0b001, 0b0010, 0b1000, 0b111>; 1229def : RWSysReg<"TRCDVCMR7", 0b10, 0b001, 0b0010, 0b1100, 0b111>; 1230def : RWSysReg<"TRCCIDCVR0", 0b10, 0b001, 0b0011, 0b0000, 0b000>; 1231def : RWSysReg<"TRCCIDCVR1", 0b10, 0b001, 0b0011, 0b0010, 0b000>; 1232def : RWSysReg<"TRCCIDCVR2", 0b10, 0b001, 0b0011, 0b0100, 0b000>; 1233def : RWSysReg<"TRCCIDCVR3", 0b10, 0b001, 0b0011, 0b0110, 0b000>; 1234def : RWSysReg<"TRCCIDCVR4", 0b10, 0b001, 0b0011, 0b1000, 0b000>; 1235def : RWSysReg<"TRCCIDCVR5", 0b10, 0b001, 0b0011, 0b1010, 0b000>; 1236def : RWSysReg<"TRCCIDCVR6", 0b10, 0b001, 0b0011, 0b1100, 0b000>; 1237def : RWSysReg<"TRCCIDCVR7", 0b10, 0b001, 0b0011, 0b1110, 0b000>; 1238def : RWSysReg<"TRCVMIDCVR0", 0b10, 0b001, 0b0011, 0b0000, 0b001>; 1239def : RWSysReg<"TRCVMIDCVR1", 0b10, 0b001, 0b0011, 0b0010, 0b001>; 1240def : RWSysReg<"TRCVMIDCVR2", 0b10, 0b001, 0b0011, 0b0100, 0b001>; 1241def : RWSysReg<"TRCVMIDCVR3", 0b10, 0b001, 0b0011, 0b0110, 0b001>; 1242def : RWSysReg<"TRCVMIDCVR4", 0b10, 0b001, 0b0011, 0b1000, 0b001>; 1243def : RWSysReg<"TRCVMIDCVR5", 0b10, 0b001, 0b0011, 0b1010, 0b001>; 1244def : RWSysReg<"TRCVMIDCVR6", 0b10, 0b001, 0b0011, 0b1100, 0b001>; 1245def : RWSysReg<"TRCVMIDCVR7", 0b10, 0b001, 0b0011, 0b1110, 0b001>; 1246def : RWSysReg<"TRCCIDCCTLR0", 0b10, 0b001, 0b0011, 0b0000, 0b010>; 1247def : RWSysReg<"TRCCIDCCTLR1", 0b10, 0b001, 0b0011, 0b0001, 0b010>; 1248def : RWSysReg<"TRCVMIDCCTLR0", 0b10, 0b001, 0b0011, 0b0010, 0b010>; 1249def : RWSysReg<"TRCVMIDCCTLR1", 0b10, 0b001, 0b0011, 0b0011, 0b010>; 1250def : RWSysReg<"TRCITCTRL", 0b10, 0b001, 0b0111, 0b0000, 0b100>; 1251def : RWSysReg<"TRCCLAIMSET", 0b10, 0b001, 0b0111, 0b1000, 0b110>; 1252def : RWSysReg<"TRCCLAIMCLR", 0b10, 0b001, 0b0111, 0b1001, 0b110>; 1253 1254// GICv3 registers 1255// Op0 Op1 CRn CRm Op2 1256def : RWSysReg<"ICC_BPR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b011>; 1257def : RWSysReg<"ICC_BPR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b011>; 1258def : RWSysReg<"ICC_PMR_EL1", 0b11, 0b000, 0b0100, 0b0110, 0b000>; 1259def : RWSysReg<"ICC_CTLR_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b100>; 1260def : RWSysReg<"ICC_CTLR_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b100>; 1261def : RWSysReg<"ICC_SRE_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b101>; 1262def : RWSysReg<"ICC_SRE_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b101>; 1263def : RWSysReg<"ICC_SRE_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b101>; 1264def : RWSysReg<"ICC_IGRPEN0_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b110>; 1265def : RWSysReg<"ICC_IGRPEN1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b111>; 1266def : RWSysReg<"ICC_IGRPEN1_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b111>; 1267def : RWSysReg<"ICC_AP0R0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b100>; 1268def : RWSysReg<"ICC_AP0R1_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b101>; 1269def : RWSysReg<"ICC_AP0R2_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b110>; 1270def : RWSysReg<"ICC_AP0R3_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b111>; 1271def : RWSysReg<"ICC_AP1R0_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b000>; 1272def : RWSysReg<"ICC_AP1R1_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b001>; 1273def : RWSysReg<"ICC_AP1R2_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b010>; 1274def : RWSysReg<"ICC_AP1R3_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b011>; 1275def : RWSysReg<"ICH_AP0R0_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b000>; 1276def : RWSysReg<"ICH_AP0R1_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b001>; 1277def : RWSysReg<"ICH_AP0R2_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b010>; 1278def : RWSysReg<"ICH_AP0R3_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b011>; 1279def : RWSysReg<"ICH_AP1R0_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b000>; 1280def : RWSysReg<"ICH_AP1R1_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b001>; 1281def : RWSysReg<"ICH_AP1R2_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b010>; 1282def : RWSysReg<"ICH_AP1R3_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b011>; 1283def : RWSysReg<"ICH_HCR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b000>; 1284def : ROSysReg<"ICH_MISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b010>; 1285def : RWSysReg<"ICH_VMCR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b111>; 1286def : RWSysReg<"ICH_LR0_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b000>; 1287def : RWSysReg<"ICH_LR1_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b001>; 1288def : RWSysReg<"ICH_LR2_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b010>; 1289def : RWSysReg<"ICH_LR3_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b011>; 1290def : RWSysReg<"ICH_LR4_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b100>; 1291def : RWSysReg<"ICH_LR5_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b101>; 1292def : RWSysReg<"ICH_LR6_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b110>; 1293def : RWSysReg<"ICH_LR7_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b111>; 1294def : RWSysReg<"ICH_LR8_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b000>; 1295def : RWSysReg<"ICH_LR9_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b001>; 1296def : RWSysReg<"ICH_LR10_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b010>; 1297def : RWSysReg<"ICH_LR11_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b011>; 1298def : RWSysReg<"ICH_LR12_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b100>; 1299def : RWSysReg<"ICH_LR13_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b101>; 1300def : RWSysReg<"ICH_LR14_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b110>; 1301def : RWSysReg<"ICH_LR15_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b111>; 1302 1303// v8r system registers 1304let Requires = [{ {AArch64::HasV8_0rOps} }] in { 1305//Virtualization System Control Register 1306// Op0 Op1 CRn CRm Op2 1307def : RWSysReg<"VSCTLR_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b000> { 1308 let AltName = "TTBR0_EL2"; 1309} 1310 1311//MPU Type Register 1312// Op0 Op1 CRn CRm Op2 1313def : RWSysReg<"MPUIR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b100>; 1314def : RWSysReg<"MPUIR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b100>; 1315 1316//Protection Region Enable Register 1317// Op0 Op1 CRn CRm Op2 1318def : RWSysReg<"PRENR_EL1", 0b11, 0b000, 0b0110, 0b0001, 0b001>; 1319def : RWSysReg<"PRENR_EL2", 0b11, 0b100, 0b0110, 0b0001, 0b001>; 1320 1321//Protection Region Selection Register 1322// Op0 Op1 CRn CRm Op2 1323def : RWSysReg<"PRSELR_EL1", 0b11, 0b000, 0b0110, 0b0010, 0b001>; 1324def : RWSysReg<"PRSELR_EL2", 0b11, 0b100, 0b0110, 0b0010, 0b001>; 1325 1326//Protection Region Base Address Register 1327// Op0 Op1 CRn CRm Op2 1328def : RWSysReg<"PRBAR_EL1", 0b11, 0b000, 0b0110, 0b1000, 0b000>; 1329def : RWSysReg<"PRBAR_EL2", 0b11, 0b100, 0b0110, 0b1000, 0b000>; 1330 1331//Protection Region Limit Address Register 1332// Op0 Op1 CRn CRm Op2 1333def : RWSysReg<"PRLAR_EL1", 0b11, 0b000, 0b0110, 0b1000, 0b001>; 1334def : RWSysReg<"PRLAR_EL2", 0b11, 0b100, 0b0110, 0b1000, 0b001>; 1335 1336foreach n = 1-15 in { 1337foreach x = 1-2 in { 1338//Direct acces to Protection Region Base Address Register for n th MPU region 1339 def : RWSysReg<!strconcat("PRBAR"#n, "_EL"#x), 1340 0b11, 0b000, 0b0110, 0b1000, 0b000>{ 1341 let Encoding{5-2} = n; 1342 let Encoding{13} = !add(x,-1); 1343 } 1344 1345 def : RWSysReg<!strconcat("PRLAR"#n, "_EL"#x), 1346 0b11, 0b000, 0b0110, 0b1000, 0b001>{ 1347 let Encoding{5-2} = n; 1348 let Encoding{13} = !add(x,-1); 1349 } 1350} //foreach x = 1-2 in 1351} //foreach n = 1-15 in 1352} //let Requires = [{ {AArch64::HasV8_0rOps} }] in 1353 1354// v8.1a "Privileged Access Never" extension-specific system registers 1355let Requires = [{ {AArch64::FeaturePAN} }] in 1356def : RWSysReg<"PAN", 0b11, 0b000, 0b0100, 0b0010, 0b011>; 1357 1358// v8.1a "Limited Ordering Regions" extension-specific system registers 1359// Op0 Op1 CRn CRm Op2 1360let Requires = [{ {AArch64::FeatureLOR} }] in { 1361def : RWSysReg<"LORSA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b000>; 1362def : RWSysReg<"LOREA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b001>; 1363def : RWSysReg<"LORN_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b010>; 1364def : RWSysReg<"LORC_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b011>; 1365} 1366 1367// v8.1a "Virtualization Host extensions" system registers 1368// Op0 Op1 CRn CRm Op2 1369let Requires = [{ {AArch64::FeatureVH} }] in { 1370def : RWSysReg<"TTBR1_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b001>; 1371def : RWSysReg<"CNTHV_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b000>; 1372def : RWSysReg<"CNTHV_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b010>; 1373def : RWSysReg<"CNTHV_CTL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b001>; 1374def : RWSysReg<"SCTLR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b000>; 1375def : RWSysReg<"CPACR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b010>; 1376def : RWSysReg<"TTBR0_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b000>; 1377def : RWSysReg<"TTBR1_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b001>; 1378def : RWSysReg<"TCR_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b010>; 1379def : RWSysReg<"AFSR0_EL12", 0b11, 0b101, 0b0101, 0b0001, 0b000>; 1380def : RWSysReg<"AFSR1_EL12", 0b11, 0b101, 0b0101, 0b0001, 0b001>; 1381def : RWSysReg<"ESR_EL12", 0b11, 0b101, 0b0101, 0b0010, 0b000>; 1382def : RWSysReg<"FAR_EL12", 0b11, 0b101, 0b0110, 0b0000, 0b000>; 1383def : RWSysReg<"MAIR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b000>; 1384def : RWSysReg<"AMAIR_EL12", 0b11, 0b101, 0b1010, 0b0011, 0b000>; 1385def : RWSysReg<"VBAR_EL12", 0b11, 0b101, 0b1100, 0b0000, 0b000>; 1386def : RWSysReg<"CONTEXTIDR_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b001>; 1387def : RWSysReg<"CNTKCTL_EL12", 0b11, 0b101, 0b1110, 0b0001, 0b000>; 1388def : RWSysReg<"CNTP_TVAL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b000>; 1389def : RWSysReg<"CNTP_CTL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b001>; 1390def : RWSysReg<"CNTP_CVAL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b010>; 1391def : RWSysReg<"CNTV_TVAL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b000>; 1392def : RWSysReg<"CNTV_CTL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b001>; 1393def : RWSysReg<"CNTV_CVAL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b010>; 1394def : RWSysReg<"SPSR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b000>; 1395def : RWSysReg<"ELR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b001>; 1396let Requires = [{ {AArch64::FeatureCONTEXTIDREL2} }] in { 1397 def : RWSysReg<"CONTEXTIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b001>; 1398} 1399} 1400// v8.2a registers 1401// Op0 Op1 CRn CRm Op2 1402let Requires = [{ {AArch64::FeaturePsUAO} }] in 1403def : RWSysReg<"UAO", 0b11, 0b000, 0b0100, 0b0010, 0b100>; 1404 1405// v8.2a "Statistical Profiling extension" registers 1406// Op0 Op1 CRn CRm Op2 1407let Requires = [{ {AArch64::FeatureSPE} }] in { 1408def : RWSysReg<"PMBLIMITR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b000>; 1409def : RWSysReg<"PMBPTR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b001>; 1410def : RWSysReg<"PMBSR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b011>; 1411def : ROSysReg<"PMBIDR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b111>; 1412def : RWSysReg<"PMSCR_EL2", 0b11, 0b100, 0b1001, 0b1001, 0b000>; 1413def : RWSysReg<"PMSCR_EL12", 0b11, 0b101, 0b1001, 0b1001, 0b000>; 1414def : RWSysReg<"PMSCR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b000>; 1415def : RWSysReg<"PMSICR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b010>; 1416def : RWSysReg<"PMSIRR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b011>; 1417def : RWSysReg<"PMSFCR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b100>; 1418def : RWSysReg<"PMSEVFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b101>; 1419def : RWSysReg<"PMSLATFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b110>; 1420def : ROSysReg<"PMSIDR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b111>; 1421} 1422 1423// v8.2a "RAS extension" registers 1424// Op0 Op1 CRn CRm Op2 1425let Requires = [{ {AArch64::FeatureRAS} }] in { 1426def : RWSysReg<"ERRSELR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b001>; 1427def : RWSysReg<"ERXCTLR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b001>; 1428def : RWSysReg<"ERXSTATUS_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b010>; 1429def : RWSysReg<"ERXADDR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b011>; 1430def : RWSysReg<"ERXMISC0_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b000>; 1431def : RWSysReg<"ERXMISC1_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b001>; 1432def : RWSysReg<"DISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b001>; 1433def : RWSysReg<"VDISR_EL2", 0b11, 0b100, 0b1100, 0b0001, 0b001>; 1434def : RWSysReg<"VSESR_EL2", 0b11, 0b100, 0b0101, 0b0010, 0b011>; 1435} 1436 1437// v8.3a "Pointer authentication extension" registers 1438// Op0 Op1 CRn CRm Op2 1439let Requires = [{ {AArch64::FeaturePAuth} }] in { 1440def : RWSysReg<"APIAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b000>; 1441def : RWSysReg<"APIAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b001>; 1442def : RWSysReg<"APIBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b010>; 1443def : RWSysReg<"APIBKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b011>; 1444def : RWSysReg<"APDAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b000>; 1445def : RWSysReg<"APDAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b001>; 1446def : RWSysReg<"APDBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b010>; 1447def : RWSysReg<"APDBKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b011>; 1448def : RWSysReg<"APGAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b000>; 1449def : RWSysReg<"APGAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b001>; 1450} 1451 1452// v8.4 "Secure Exception Level 2 extension" 1453let Requires = [{ {AArch64::FeatureSEL2} }] in { 1454// v8.4a "Virtualization secure second stage translation" registers 1455// Op0 Op1 CRn CRm Op2 1456def : RWSysReg<"VSTCR_EL2" , 0b11, 0b100, 0b0010, 0b0110, 0b010>; 1457def : RWSysReg<"VSTTBR_EL2", 0b11, 0b100, 0b0010, 0b0110, 0b000> { 1458 let Requires = [{ {AArch64::HasV8_0aOps} }]; 1459} 1460 1461// v8.4a "Virtualization timer" registers 1462// Op0 Op1 CRn CRm Op2 1463def : RWSysReg<"CNTHVS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b000>; 1464def : RWSysReg<"CNTHVS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b010>; 1465def : RWSysReg<"CNTHVS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b001>; 1466def : RWSysReg<"CNTHPS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b000>; 1467def : RWSysReg<"CNTHPS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b010>; 1468def : RWSysReg<"CNTHPS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b001>; 1469 1470// v8.4a "Virtualization debug state" registers 1471// Op0 Op1 CRn CRm Op2 1472def : RWSysReg<"SDER32_EL2", 0b11, 0b100, 0b0001, 0b0011, 0b001>; 1473} // FeatureSEL2 1474 1475// v8.4a RAS registers 1476// Op0 Op1 CRn CRm Op2 1477def : RWSysReg<"ERXPFGCTL_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b101>; 1478def : RWSysReg<"ERXPFGCDN_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b110>; 1479def : RWSysReg<"ERXMISC2_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b010>; 1480def : RWSysReg<"ERXMISC3_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b011>; 1481def : ROSysReg<"ERXPFGF_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b100>; 1482 1483// v8.4a MPAM registers 1484// Op0 Op1 CRn CRm Op2 1485let Requires = [{ {AArch64::FeatureMPAM} }] in { 1486def : RWSysReg<"MPAM0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b001>; 1487def : RWSysReg<"MPAM1_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b000>; 1488def : RWSysReg<"MPAM2_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b000>; 1489def : RWSysReg<"MPAM3_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b000>; 1490def : RWSysReg<"MPAM1_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b000>; 1491def : RWSysReg<"MPAMHCR_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b000>; 1492def : RWSysReg<"MPAMVPMV_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b001>; 1493def : RWSysReg<"MPAMVPM0_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b000>; 1494def : RWSysReg<"MPAMVPM1_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b001>; 1495def : RWSysReg<"MPAMVPM2_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b010>; 1496def : RWSysReg<"MPAMVPM3_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b011>; 1497def : RWSysReg<"MPAMVPM4_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b100>; 1498def : RWSysReg<"MPAMVPM5_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b101>; 1499def : RWSysReg<"MPAMVPM6_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b110>; 1500def : RWSysReg<"MPAMVPM7_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b111>; 1501def : ROSysReg<"MPAMIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b100>; 1502} //FeatureMPAM 1503 1504// v8.4a Activity Monitor registers 1505// Op0 Op1 CRn CRm Op2 1506let Requires = [{ {AArch64::FeatureAM} }] in { 1507def : RWSysReg<"AMCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b000>; 1508def : ROSysReg<"AMCFGR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b001>; 1509def : ROSysReg<"AMCGCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b010>; 1510def : RWSysReg<"AMUSERENR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b011>; 1511def : RWSysReg<"AMCNTENCLR0_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b100>; 1512def : RWSysReg<"AMCNTENSET0_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b101>; 1513def : RWSysReg<"AMEVCNTR00_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b000>; 1514def : RWSysReg<"AMEVCNTR01_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b001>; 1515def : RWSysReg<"AMEVCNTR02_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b010>; 1516def : RWSysReg<"AMEVCNTR03_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b011>; 1517def : ROSysReg<"AMEVTYPER00_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b000>; 1518def : ROSysReg<"AMEVTYPER01_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b001>; 1519def : ROSysReg<"AMEVTYPER02_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b010>; 1520def : ROSysReg<"AMEVTYPER03_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b011>; 1521def : RWSysReg<"AMCNTENCLR1_EL0", 0b11, 0b011, 0b1101, 0b0011, 0b000>; 1522def : RWSysReg<"AMCNTENSET1_EL0", 0b11, 0b011, 0b1101, 0b0011, 0b001>; 1523def : RWSysReg<"AMEVCNTR10_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b000>; 1524def : RWSysReg<"AMEVCNTR11_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b001>; 1525def : RWSysReg<"AMEVCNTR12_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b010>; 1526def : RWSysReg<"AMEVCNTR13_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b011>; 1527def : RWSysReg<"AMEVCNTR14_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b100>; 1528def : RWSysReg<"AMEVCNTR15_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b101>; 1529def : RWSysReg<"AMEVCNTR16_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b110>; 1530def : RWSysReg<"AMEVCNTR17_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b111>; 1531def : RWSysReg<"AMEVCNTR18_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b000>; 1532def : RWSysReg<"AMEVCNTR19_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b001>; 1533def : RWSysReg<"AMEVCNTR110_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b010>; 1534def : RWSysReg<"AMEVCNTR111_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b011>; 1535def : RWSysReg<"AMEVCNTR112_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b100>; 1536def : RWSysReg<"AMEVCNTR113_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b101>; 1537def : RWSysReg<"AMEVCNTR114_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b110>; 1538def : RWSysReg<"AMEVCNTR115_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b111>; 1539def : RWSysReg<"AMEVTYPER10_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b000>; 1540def : RWSysReg<"AMEVTYPER11_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b001>; 1541def : RWSysReg<"AMEVTYPER12_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b010>; 1542def : RWSysReg<"AMEVTYPER13_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b011>; 1543def : RWSysReg<"AMEVTYPER14_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b100>; 1544def : RWSysReg<"AMEVTYPER15_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b101>; 1545def : RWSysReg<"AMEVTYPER16_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b110>; 1546def : RWSysReg<"AMEVTYPER17_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b111>; 1547def : RWSysReg<"AMEVTYPER18_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b000>; 1548def : RWSysReg<"AMEVTYPER19_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b001>; 1549def : RWSysReg<"AMEVTYPER110_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b010>; 1550def : RWSysReg<"AMEVTYPER111_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b011>; 1551def : RWSysReg<"AMEVTYPER112_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b100>; 1552def : RWSysReg<"AMEVTYPER113_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b101>; 1553def : RWSysReg<"AMEVTYPER114_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b110>; 1554def : RWSysReg<"AMEVTYPER115_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b111>; 1555} //FeatureAM 1556 1557// v8.4a Trace Extension registers 1558// 1559// Please note that the 8.4 spec also defines these registers: 1560// TRCIDR1, ID_DFR0_EL1, ID_AA64DFR0_EL1, MDSCR_EL1, MDCR_EL2, and MDCR_EL3, 1561// but they are already defined above. 1562// 1563// Op0 Op1 CRn CRm Op2 1564let Requires = [{ {AArch64::FeatureTRACEV8_4} }] in { 1565def : RWSysReg<"TRFCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b001>; 1566def : RWSysReg<"TRFCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b001>; 1567def : RWSysReg<"TRFCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b001>; 1568} //FeatureTRACEV8_4 1569 1570// v8.4a Timing insensitivity of data processing instructions 1571// DIT: Data Independent Timing instructions 1572// Op0 Op1 CRn CRm Op2 1573let Requires = [{ {AArch64::FeatureDIT} }] in { 1574def : RWSysReg<"DIT", 0b11, 0b011, 0b0100, 0b0010, 0b101>; 1575} //FeatureDIT 1576 1577// v8.4a Enhanced Support for Nested Virtualization 1578// Op0 Op1 CRn CRm Op2 1579let Requires = [{ {AArch64::FeatureNV} }] in { 1580def : RWSysReg<"VNCR_EL2", 0b11, 0b100, 0b0010, 0b0010, 0b000>; 1581} //FeatureNV 1582 1583// SVE control registers 1584// Op0 Op1 CRn CRm Op2 1585let Requires = [{ {AArch64::FeatureSVE} }] in { 1586def : RWSysReg<"ZCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b000>; 1587def : RWSysReg<"ZCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b000>; 1588def : RWSysReg<"ZCR_EL3", 0b11, 0b110, 0b0001, 0b0010, 0b000>; 1589def : RWSysReg<"ZCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b000>; 1590} 1591 1592// V8.5a Spectre mitigation SSBS register 1593// Op0 Op1 CRn CRm Op2 1594let Requires = [{ {AArch64::FeatureSSBS} }] in 1595def : RWSysReg<"SSBS", 0b11, 0b011, 0b0100, 0b0010, 0b110>; 1596 1597// v8.5a Memory Tagging Extension 1598// Op0 Op1 CRn CRm Op2 1599let Requires = [{ {AArch64::FeatureMTE} }] in { 1600def : RWSysReg<"TCO", 0b11, 0b011, 0b0100, 0b0010, 0b111>; 1601def : RWSysReg<"GCR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b110>; 1602def : RWSysReg<"RGSR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b101>; 1603def : RWSysReg<"TFSR_EL1", 0b11, 0b000, 0b0101, 0b0110, 0b000>; 1604def : RWSysReg<"TFSR_EL2", 0b11, 0b100, 0b0101, 0b0110, 0b000>; 1605def : RWSysReg<"TFSR_EL3", 0b11, 0b110, 0b0101, 0b0110, 0b000>; 1606def : RWSysReg<"TFSR_EL12", 0b11, 0b101, 0b0101, 0b0110, 0b000>; 1607def : RWSysReg<"TFSRE0_EL1", 0b11, 0b000, 0b0101, 0b0110, 0b001>; 1608def : ROSysReg<"GMID_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b100>; 1609} // HasMTE 1610 1611// Embedded Trace Extension R/W System registers 1612let Requires = [{ {AArch64::FeatureETE} }] in { 1613// Name Op0 Op1 CRn CRm Op2 1614def : RWSysReg<"TRCRSR", 0b10, 0b001, 0b0000, 0b1010, 0b000>; 1615// TRCEXTINSELR0 has the same encoding as ETM TRCEXTINSELR 1616def : RWSysReg<"TRCEXTINSELR0", 0b10, 0b001, 0b0000, 0b1000, 0b100>; 1617def : RWSysReg<"TRCEXTINSELR1", 0b10, 0b001, 0b0000, 0b1001, 0b100>; 1618def : RWSysReg<"TRCEXTINSELR2", 0b10, 0b001, 0b0000, 0b1010, 0b100>; 1619def : RWSysReg<"TRCEXTINSELR3", 0b10, 0b001, 0b0000, 0b1011, 0b100>; 1620} // FeatureETE 1621 1622// Trace Buffer Extension System registers 1623let Requires = [{ {AArch64::FeatureTRBE} }] in { 1624// Name Op0 Op1 CRn CRm Op2 1625def : RWSysReg<"TRBLIMITR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b000>; 1626def : RWSysReg<"TRBPTR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b001>; 1627def : RWSysReg<"TRBBASER_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b010>; 1628def : RWSysReg<"TRBSR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b011>; 1629def : RWSysReg<"TRBMAR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b100>; 1630def : RWSysReg<"TRBTRG_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b110>; 1631def : ROSysReg<"TRBIDR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b111>; 1632} // FeatureTRBE 1633 1634 1635// v8.6a Activity Monitors Virtualization Support 1636let Requires = [{ {AArch64::FeatureAMVS} }] in { 1637foreach n = 0-15 in { 1638 foreach x = 0-1 in { 1639 def : RWSysReg<"AMEVCNTVOFF"#x#n#"_EL2", 1640 0b11, 0b100, 0b1101, 0b1000, 0b000>{ 1641 let Encoding{4} = x; 1642 let Encoding{3-0} = n; 1643 } 1644 } 1645} 1646} 1647 1648// v8.6a Fine Grained Virtualization Traps 1649// Op0 Op1 CRn CRm Op2 1650let Requires = [{ {AArch64::FeatureFineGrainedTraps} }] in { 1651def : RWSysReg<"HFGRTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b100>; 1652def : RWSysReg<"HFGWTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b101>; 1653def : RWSysReg<"HFGITR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b110>; 1654def : RWSysReg<"HDFGRTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b100>; 1655def : RWSysReg<"HDFGWTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b101>; 1656} 1657 1658// v8.6a Enhanced Counter Virtualization 1659// Op0 Op1 CRn CRm Op2 1660let Requires = [{ {AArch64::FeatureEnhancedCounterVirtualization} }] in { 1661def : RWSysReg<"CNTSCALE_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b100>; 1662def : RWSysReg<"CNTISCALE_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b101>; 1663def : RWSysReg<"CNTPOFF_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b110>; 1664def : RWSysReg<"CNTVFRQ_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b111>; 1665def : RWSysReg<"CNTPCTSS_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b101>; 1666def : RWSysReg<"CNTVCTSS_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b110>; 1667} 1668 1669// v8.7a LD64B/ST64B Accelerator Extension system register 1670let Requires = [{ {AArch64::FeatureLS64} }] in 1671def : RWSysReg<"ACCDATA_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b101>; 1672 1673// Branch Record Buffer system registers 1674let Requires = [{ {AArch64::FeatureBRBE} }] in { 1675def : RWSysReg<"BRBCR_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b000>; 1676def : RWSysReg<"BRBCR_EL12", 0b10, 0b101, 0b1001, 0b0000, 0b000>; 1677def : RWSysReg<"BRBCR_EL2", 0b10, 0b100, 0b1001, 0b0000, 0b000>; 1678def : RWSysReg<"BRBFCR_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b001>; 1679def : ROSysReg<"BRBIDR0_EL1", 0b10, 0b001, 0b1001, 0b0010, 0b000>; 1680def : RWSysReg<"BRBINFINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b000>; 1681def : RWSysReg<"BRBSRCINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b001>; 1682def : RWSysReg<"BRBTGTINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b010>; 1683def : RWSysReg<"BRBTS_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b010>; 1684foreach n = 0-31 in { 1685 defvar nb = !cast<bits<5>>(n); 1686 def : ROSysReg<"BRBINF"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b00}>; 1687 def : ROSysReg<"BRBSRC"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b01}>; 1688 def : ROSysReg<"BRBTGT"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b10}>; 1689} 1690} 1691 1692// Statistical Profiling Extension system register 1693let Requires = [{ {AArch64::FeatureSPE_EEF} }] in 1694def : RWSysReg<"PMSNEVFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b001>; 1695 1696// Cyclone specific system registers 1697// Op0 Op1 CRn CRm Op2 1698let Requires = [{ {AArch64::FeatureAppleA7SysReg} }] in 1699def : RWSysReg<"CPM_IOACC_CTL_EL3", 0b11, 0b111, 0b1111, 0b0010, 0b000>; 1700 1701// Scalable Matrix Extension (SME) 1702// Op0 Op1 CRn CRm Op2 1703let Requires = [{ {AArch64::FeatureSME} }] in { 1704def : RWSysReg<"SMCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b110>; 1705def : RWSysReg<"SMCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b110>; 1706def : RWSysReg<"SMCR_EL3", 0b11, 0b110, 0b0001, 0b0010, 0b110>; 1707def : RWSysReg<"SMCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b110>; 1708def : RWSysReg<"SVCR", 0b11, 0b011, 0b0100, 0b0010, 0b010>; 1709def : RWSysReg<"SMPRI_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b100>; 1710def : RWSysReg<"SMPRIMAP_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b101>; 1711def : ROSysReg<"SMIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b110>; 1712def : RWSysReg<"TPIDR2_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b101>; 1713} // HasSME 1714 1715// v8.4a MPAM and SME registers 1716// Op0 Op1 CRn CRm Op2 1717let Requires = [{ {AArch64::FeatureMPAM, AArch64::FeatureSME} }] in { 1718def : RWSysReg<"MPAMSM_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b011>; 1719} // HasMPAM, HasSME 1720