1//=- AArch64SchedCyclone.td - Cyclone Scheduling Definitions -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for AArch64 Cyclone to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14def CycloneModel : SchedMachineModel { 15 let IssueWidth = 6; // 6 micro-ops are dispatched per cycle. 16 let MicroOpBufferSize = 192; // Based on the reorder buffer. 17 let LoadLatency = 4; // Optimistic load latency. 18 let MispredictPenalty = 16; // 14-19 cycles are typical. 19 let CompleteModel = 1; 20 21 list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F, 22 PAUnsupported.F, 23 SMEUnsupported.F); 24} 25 26//===----------------------------------------------------------------------===// 27// Define each kind of processor resource and number available on Cyclone. 28 29// 4 integer pipes 30def CyUnitI : ProcResource<4> { 31 let BufferSize = 48; 32} 33 34// 2 branch units: I[0..1] 35def CyUnitB : ProcResource<2> { 36 let Super = CyUnitI; 37 let BufferSize = 24; 38} 39 40// 1 indirect-branch unit: I[0] 41def CyUnitBR : ProcResource<1> { 42 let Super = CyUnitB; 43} 44 45// 2 shifter pipes: I[2..3] 46// When an instruction consumes a CyUnitIS, it also consumes a CyUnitI 47def CyUnitIS : ProcResource<2> { 48 let Super = CyUnitI; 49 let BufferSize = 24; 50} 51 52// 1 mul pipe: I[0] 53def CyUnitIM : ProcResource<1> { 54 let Super = CyUnitBR; 55 let BufferSize = 32; 56} 57 58// 1 div pipe: I[1] 59def CyUnitID : ProcResource<1> { 60 let Super = CyUnitB; 61 let BufferSize = 16; 62} 63 64// 1 integer division unit. This is driven by the ID pipe, but only 65// consumes the pipe for one cycle at issue and another cycle at writeback. 66def CyUnitIntDiv : ProcResource<1>; 67 68// 2 ld/st pipes. 69def CyUnitLS : ProcResource<2> { 70 let BufferSize = 28; 71} 72 73// 3 fp/vector pipes. 74def CyUnitV : ProcResource<3> { 75 let BufferSize = 48; 76} 77// 2 fp/vector arithmetic and multiply pipes: V[0-1] 78def CyUnitVM : ProcResource<2> { 79 let Super = CyUnitV; 80 let BufferSize = 32; 81} 82// 1 fp/vector division/sqrt pipe: V[2] 83def CyUnitVD : ProcResource<1> { 84 let Super = CyUnitV; 85 let BufferSize = 16; 86} 87// 1 fp compare pipe: V[0] 88def CyUnitVC : ProcResource<1> { 89 let Super = CyUnitVM; 90 let BufferSize = 16; 91} 92 93// 2 fp division/square-root units. These are driven by the VD pipe, 94// but only consume the pipe for one cycle at issue and a cycle at writeback. 95def CyUnitFloatDiv : ProcResource<2>; 96 97//===----------------------------------------------------------------------===// 98// Define scheduler read/write resources and latency on Cyclone. 99// This mirrors sections 7.7-7.9 of the Tuning Guide v1.0.1. 100 101let SchedModel = CycloneModel in { 102 103//--- 104// 7.8.1. Moves 105//--- 106 107// A single nop micro-op (uX). 108def WriteX : SchedWriteRes<[]> { let Latency = 0; } 109 110// Move zero is a register rename (to machine register zero). 111// The move is replaced by a single nop micro-op. 112// MOVZ Rd, #0 113// AND Rd, Rzr, #imm 114def WriteZPred : SchedPredicate<[{TII->isGPRZero(*MI)}]>; 115def WriteImmZ : SchedWriteVariant<[ 116 SchedVar<WriteZPred, [WriteX]>, 117 SchedVar<NoSchedPred, [WriteImm]>]>; 118def : InstRW<[WriteImmZ], (instrs MOVZWi,MOVZXi,ANDWri,ANDXri)>; 119 120// Move GPR is a register rename and single nop micro-op. 121// ORR Xd, XZR, Xm 122// ADD Xd, Xn, #0 123def WriteIMovPred : SchedPredicate<[{TII->isGPRCopy(*MI)}]>; 124def WriteVMovPred : SchedPredicate<[{TII->isFPRCopy(*MI)}]>; 125def WriteMov : SchedWriteVariant<[ 126 SchedVar<WriteIMovPred, [WriteX]>, 127 SchedVar<WriteVMovPred, [WriteX]>, 128 SchedVar<NoSchedPred, [WriteI]>]>; 129def : InstRW<[WriteMov], (instrs COPY,ORRXrr,ADDXrr)>; 130 131// Move non-zero immediate is an integer ALU op. 132// MOVN,MOVZ,MOVK 133def : WriteRes<WriteImm, [CyUnitI]>; 134 135//--- 136// 7.8.2-7.8.5. Arithmetic and Logical, Comparison, Conditional, 137// Shifts and Bitfield Operations 138//--- 139 140// ADR,ADRP 141// ADD(S)ri,SUB(S)ri,AND(S)ri,EORri,ORRri 142// ADD(S)rr,SUB(S)rr,AND(S)rr,BIC(S)rr,EONrr,EORrr,ORNrr,ORRrr 143// ADC(S),SBC(S) 144// Aliases: CMN, CMP, TST 145// 146// Conditional operations. 147// CCMNi,CCMPi,CCMNr,CCMPr, 148// CSEL,CSINC,CSINV,CSNEG 149// 150// Bit counting and reversal operations. 151// CLS,CLZ,RBIT,REV,REV16,REV32 152def : WriteRes<WriteI, [CyUnitI]>; 153 154// ADD with shifted register operand is a single micro-op that 155// consumes a shift pipeline for two cycles. 156// ADD(S)rs,SUB(S)rs,AND(S)rs,BIC(S)rs,EONrs,EORrs,ORNrs,ORRrs 157// EXAMPLE: ADDrs Xn, Xm LSL #imm 158def : WriteRes<WriteISReg, [CyUnitIS]> { 159 let Latency = 2; 160 let ResourceCycles = [2]; 161} 162 163// ADD with extended register operand is the same as shifted reg operand. 164// ADD(S)re,SUB(S)re 165// EXAMPLE: ADDXre Xn, Xm, UXTB #1 166def : WriteRes<WriteIEReg, [CyUnitIS]> { 167 let Latency = 2; 168 let ResourceCycles = [2]; 169} 170 171// Variable shift and bitfield operations. 172// ASRV,LSLV,LSRV,RORV,BFM,SBFM,UBFM 173def : WriteRes<WriteIS, [CyUnitIS]>; 174 175// EXTR Shifts a pair of registers and requires two micro-ops. 176// The second micro-op is delayed, as modeled by ReadExtrHi. 177// EXTR Xn, Xm, #imm 178def : WriteRes<WriteExtr, [CyUnitIS, CyUnitIS]> { 179 let Latency = 2; 180 let NumMicroOps = 2; 181} 182 183// EXTR's first register read is delayed by one cycle, effectively 184// shortening its writer's latency. 185// EXTR Xn, Xm, #imm 186def : ReadAdvance<ReadExtrHi, 1>; 187 188//--- 189// 7.8.6. Multiplies 190//--- 191 192// MUL/MNEG are aliases for MADD/MSUB. 193// MADDW,MSUBW,SMADDL,SMSUBL,UMADDL,UMSUBL 194def : WriteRes<WriteIM32, [CyUnitIM]> { 195 let Latency = 4; 196} 197// MADDX,MSUBX,SMULH,UMULH 198def : WriteRes<WriteIM64, [CyUnitIM]> { 199 let Latency = 5; 200} 201 202//--- 203// 7.8.7. Divide 204//--- 205 206// 32-bit divide takes 7-13 cycles. 10 cycles covers a 20-bit quotient. 207// The ID pipe is consumed for 2 cycles: issue and writeback. 208// SDIVW,UDIVW 209def : WriteRes<WriteID32, [CyUnitID, CyUnitIntDiv]> { 210 let Latency = 10; 211 let ResourceCycles = [2, 10]; 212} 213// 64-bit divide takes 7-21 cycles. 13 cycles covers a 32-bit quotient. 214// The ID pipe is consumed for 2 cycles: issue and writeback. 215// SDIVX,UDIVX 216def : WriteRes<WriteID64, [CyUnitID, CyUnitIntDiv]> { 217 let Latency = 13; 218 let ResourceCycles = [2, 13]; 219} 220 221//--- 222// 7.8.8,7.8.10. Load/Store, single element 223//--- 224 225// Integer loads take 4 cycles and use one LS unit for one cycle. 226def : WriteRes<WriteLD, [CyUnitLS]> { 227 let Latency = 4; 228} 229 230// Store-load forwarding is 4 cycles. 231// 232// Note: The store-exclusive sequence incorporates this 233// latency. However, general heuristics should not model the 234// dependence between a store and subsequent may-alias load because 235// hardware speculation works. 236def : WriteRes<WriteST, [CyUnitLS]> { 237 let Latency = 4; 238} 239 240// Load from base address plus an optionally scaled register offset. 241// Rt latency is latency WriteIS + WriteLD. 242// EXAMPLE: LDR Xn, Xm [, lsl 3] 243def CyWriteLDIdx : SchedWriteVariant<[ 244 SchedVar<ScaledIdxPred, [WriteIS, WriteLD]>, // Load from scaled register. 245 SchedVar<NoSchedPred, [WriteLD]>]>; // Load from register offset. 246def : SchedAlias<WriteLDIdx, CyWriteLDIdx>; // Map AArch64->Cyclone type. 247 248// EXAMPLE: STR Xn, Xm [, lsl 3] 249def CyWriteSTIdx : SchedWriteVariant<[ 250 SchedVar<ScaledIdxPred, [WriteIS, WriteST]>, // Store to scaled register. 251 SchedVar<NoSchedPred, [WriteST]>]>; // Store to register offset. 252def : SchedAlias<WriteSTIdx, CyWriteSTIdx>; // Map AArch64->Cyclone type. 253 254// Read the (unshifted) base register Xn in the second micro-op one cycle later. 255// EXAMPLE: LDR Xn, Xm [, lsl 3] 256def ReadBaseRS : SchedReadAdvance<1>; 257def CyReadAdrBase : SchedReadVariant<[ 258 SchedVar<ScaledIdxPred, [ReadBaseRS]>, // Read base reg after shifting offset. 259 SchedVar<NoSchedPred, [ReadDefault]>]>; // Read base reg with no shift. 260def : SchedAlias<ReadAdrBase, CyReadAdrBase>; // Map AArch64->Cyclone type. 261def : ReadAdvance<ReadST, 0>; 262 263//--- 264// 7.8.9,7.8.11. Load/Store, paired 265//--- 266 267// Address pre/post increment is a simple ALU op with one cycle latency. 268def : WriteRes<WriteAdr, [CyUnitI]>; 269 270// LDP high register write is fused with the load, but a nop micro-op remains. 271def : WriteRes<WriteLDHi, []> { 272 let Latency = 4; 273} 274 275// STP is a vector op and store, except for QQ, which is just two stores. 276def : SchedAlias<WriteSTP, WriteVSTShuffle>; 277def : InstRW<[WriteST, WriteST], (instrs STPQi)>; 278 279//--- 280// 7.8.13. Branches 281//--- 282 283// Branches take a single micro-op. 284// The misprediction penalty is defined as a SchedMachineModel property. 285def : WriteRes<WriteBr, [CyUnitB]> {let Latency = 0;} 286def : WriteRes<WriteBrReg, [CyUnitBR]> {let Latency = 0;} 287 288//--- 289// 7.8.14. Never-issued Instructions, Barrier and Hint Operations 290//--- 291 292// NOP,SEV,SEVL,WFE,WFI,YIELD 293def : WriteRes<WriteHint, []> {let Latency = 0;} 294// ISB 295def : InstRW<[WriteI], (instrs ISB)>; 296// SLREX,DMB,DSB 297def : WriteRes<WriteBarrier, [CyUnitLS]>; 298 299// System instructions get an invalid latency because the latency of 300// other operations across them is meaningless. 301def : WriteRes<WriteSys, []> {let Latency = -1;} 302 303//===----------------------------------------------------------------------===// 304// 7.9 Vector Unit Instructions 305 306// Simple vector operations take 2 cycles. 307def : WriteRes<WriteVd, [CyUnitV]> {let Latency = 2;} 308def : WriteRes<WriteVq, [CyUnitV]> {let Latency = 2;} 309 310// Define some longer latency vector op types for Cyclone. 311def CyWriteV3 : SchedWriteRes<[CyUnitV]> {let Latency = 3;} 312def CyWriteV4 : SchedWriteRes<[CyUnitV]> {let Latency = 4;} 313def CyWriteV5 : SchedWriteRes<[CyUnitV]> {let Latency = 5;} 314def CyWriteV6 : SchedWriteRes<[CyUnitV]> {let Latency = 6;} 315 316// Simple floating-point operations take 2 cycles. 317def : WriteRes<WriteF, [CyUnitV]> {let Latency = 2;} 318 319//--- 320// 7.9.1 Vector Moves 321//--- 322 323// TODO: Add Cyclone-specific zero-cycle zeros. LLVM currently 324// generates expensive int-float conversion instead: 325// FMOVDi Dd, #0.0 326// FMOVv2f64ns Vd.2d, #0.0 327 328// FMOVSi,FMOVDi 329def : WriteRes<WriteFImm, [CyUnitV]> {let Latency = 2;} 330 331// MOVI,MVNI are WriteV 332// FMOVv2f32ns,FMOVv2f64ns,FMOVv4f32ns are WriteV 333 334// Move FPR is a register rename and single nop micro-op. 335// ORR.16b Vd,Vn,Vn 336// COPY is handled above in the WriteMov Variant. 337def WriteVMov : SchedWriteVariant<[ 338 SchedVar<WriteVMovPred, [WriteX]>, 339 SchedVar<NoSchedPred, [WriteVq]>]>; 340def : InstRW<[WriteVMov], (instrs ORRv16i8)>; 341 342// FMOVSr,FMOVDr are WriteF. 343 344// MOV V,V is a WriteV. 345 346// CPY D,V[x] is a WriteV 347 348// INS V[x],V[y] is a WriteV. 349 350// FMOVWSr,FMOVXDr,FMOVXDHighr 351def : WriteRes<WriteFCopy, [CyUnitLS]> { 352 let Latency = 5; 353} 354 355// FMOVSWr,FMOVDXr 356def : InstRW<[WriteLD], (instrs FMOVSWr,FMOVDXr,FMOVDXHighr)>; 357 358// INS V[x],R 359def CyWriteCopyToFPR : WriteSequence<[WriteVLD, WriteVq]>; 360def : InstRW<[CyWriteCopyToFPR], (instregex "INSv")>; 361 362// SMOV,UMOV R,V[x] 363def CyWriteCopyToGPR : WriteSequence<[WriteLD, WriteI]>; 364def : InstRW<[CyWriteCopyToGPR], (instregex "SMOVv","UMOVv")>; 365 366// DUP V,R 367def : InstRW<[CyWriteCopyToFPR], (instregex "DUPv")>; 368 369// DUP V,V[x] is a WriteV. 370 371//--- 372// 7.9.2 Integer Arithmetic, Logical, and Comparisons 373//--- 374 375// BIC,ORR V,#imm are WriteV 376 377def : InstRW<[CyWriteV3], (instregex "ABSv")>; 378 379// MVN,NEG,NOT are WriteV 380 381def : InstRW<[CyWriteV3], (instregex "SQABSv","SQNEGv")>; 382 383// ADDP is a WriteV. 384def CyWriteVADDLP : SchedWriteRes<[CyUnitV]> {let Latency = 2;} 385def : InstRW<[CyWriteVADDLP], (instregex "SADDLPv","UADDLPv")>; 386 387def : InstRW<[CyWriteV3], 388 (instregex "ADDVv","SMAXVv","UMAXVv","SMINVv","UMINVv")>; 389 390def : InstRW<[CyWriteV3], (instregex "SADDLV","UADDLV")>; 391 392// ADD,SUB are WriteV 393 394// Forward declare. 395def CyWriteVABD : SchedWriteRes<[CyUnitV]> {let Latency = 3;} 396 397// Add/Diff and accumulate uses the vector multiply unit. 398def CyWriteVAccum : SchedWriteRes<[CyUnitVM]> {let Latency = 3;} 399def CyReadVAccum : SchedReadAdvance<1, 400 [CyWriteVAccum, CyWriteVADDLP, CyWriteVABD]>; 401 402def : InstRW<[CyWriteVAccum, CyReadVAccum], 403 (instregex "SADALP","UADALP")>; 404 405def : InstRW<[CyWriteVAccum, CyReadVAccum], 406 (instregex "SABAv","UABAv","SABALv","UABALv")>; 407 408def : InstRW<[CyWriteV3], (instregex "SQADDv","SQSUBv","UQADDv","UQSUBv")>; 409 410def : InstRW<[CyWriteV3], (instregex "SUQADDv","USQADDv")>; 411 412def : InstRW<[CyWriteV4], (instregex "ADDHNv","RADDHNv", "RSUBHNv", "SUBHNv")>; 413 414// WriteV includes: 415// AND,BIC,CMTST,EOR,ORN,ORR 416// ADDP 417// SHADD,SHSUB,SRHADD,UHADD,UHSUB,URHADD 418// SADDL,SSUBL,UADDL,USUBL 419// SADDW,SSUBW,UADDW,USUBW 420 421def : InstRW<[CyWriteV3], (instregex "CMEQv","CMGEv","CMGTv", 422 "CMLEv","CMLTv", 423 "CMHIv","CMHSv")>; 424 425def : InstRW<[CyWriteV3], (instregex "SMAXv","SMINv","UMAXv","UMINv", 426 "SMAXPv","SMINPv","UMAXPv","UMINPv")>; 427 428def : InstRW<[CyWriteVABD], (instregex "SABDv","UABDv", 429 "SABDLv","UABDLv")>; 430 431//--- 432// 7.9.3 Floating Point Arithmetic and Comparisons 433//--- 434 435// FABS,FNEG are WriteF 436 437def : InstRW<[CyWriteV4], (instrs FADDPv2i32p)>; 438def : InstRW<[CyWriteV5], (instrs FADDPv2i64p)>; 439 440def : InstRW<[CyWriteV3], (instregex "FMAXPv2i","FMAXNMPv2i", 441 "FMINPv2i","FMINNMPv2i")>; 442 443def : InstRW<[CyWriteV4], (instregex "FMAXVv","FMAXNMVv","FMINVv","FMINNMVv")>; 444 445def : InstRW<[CyWriteV4], (instrs FADDSrr,FADDv2f32,FADDv4f32, 446 FSUBSrr,FSUBv2f32,FSUBv4f32, 447 FADDPv2f32,FADDPv4f32, 448 FABD32,FABDv2f32,FABDv4f32)>; 449def : InstRW<[CyWriteV5], (instrs FADDDrr,FADDv2f64, 450 FSUBDrr,FSUBv2f64, 451 FADDPv2f64, 452 FABD64,FABDv2f64)>; 453 454def : InstRW<[CyWriteV3], (instregex "FCMEQ","FCMGT","FCMLE","FCMLT")>; 455 456def : InstRW<[CyWriteV3], (instregex "FACGE","FACGT", 457 "FMAXS","FMAXD","FMAXv", 458 "FMINS","FMIND","FMINv", 459 "FMAXNMS","FMAXNMD","FMAXNMv", 460 "FMINNMS","FMINNMD","FMINNMv", 461 "FMAXPv2f","FMAXPv4f", 462 "FMINPv2f","FMINPv4f", 463 "FMAXNMPv2f","FMAXNMPv4f", 464 "FMINNMPv2f","FMINNMPv4f")>; 465 466// FCMP,FCMPE,FCCMP,FCCMPE 467def : WriteRes<WriteFCmp, [CyUnitVC]> {let Latency = 4;} 468 469// FCSEL is a WriteF. 470 471//--- 472// 7.9.4 Shifts and Bitfield Operations 473//--- 474 475// SHL is a WriteV 476 477def CyWriteVSHR : SchedWriteRes<[CyUnitV]> {let Latency = 2;} 478def : InstRW<[CyWriteVSHR], (instregex "SSHRv","USHRv")>; 479 480def CyWriteVSRSHR : SchedWriteRes<[CyUnitV]> {let Latency = 3;} 481def : InstRW<[CyWriteVSRSHR], (instregex "SRSHRv","URSHRv")>; 482 483// Shift and accumulate uses the vector multiply unit. 484def CyWriteVShiftAcc : SchedWriteRes<[CyUnitVM]> {let Latency = 3;} 485def CyReadVShiftAcc : SchedReadAdvance<1, 486 [CyWriteVShiftAcc, CyWriteVSHR, CyWriteVSRSHR]>; 487def : InstRW<[CyWriteVShiftAcc, CyReadVShiftAcc], 488 (instregex "SRSRAv","SSRAv","URSRAv","USRAv")>; 489 490// SSHL,USHL are WriteV. 491 492def : InstRW<[CyWriteV3], (instregex "SRSHLv","URSHLv")>; 493 494// SQSHL,SQSHLU,UQSHL are WriteV. 495 496def : InstRW<[CyWriteV3], (instregex "SQRSHLv","UQRSHLv")>; 497 498// WriteV includes: 499// SHLL,SSHLL,USHLL 500// SLI,SRI 501// BIF,BIT,BSL,BSP 502// EXT 503// CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN 504// XTN2 505 506def : InstRW<[CyWriteV4], 507 (instregex "RSHRNv","SHRNv", 508 "SQRSHRNv","SQRSHRUNv","SQSHRNv","SQSHRUNv", 509 "UQRSHRNv","UQSHRNv","SQXTNv","SQXTUNv","UQXTNv")>; 510 511//--- 512// 7.9.5 Multiplication 513//--- 514 515def CyWriteVMul : SchedWriteRes<[CyUnitVM]> { let Latency = 4;} 516def : InstRW<[CyWriteVMul], (instregex "MULv","SMULLv","UMULLv", 517 "SQDMULLv","SQDMULHv","SQRDMULHv")>; 518 519// FMUL,FMULX,FNMUL default to WriteFMul. 520def : WriteRes<WriteFMul, [CyUnitVM]> { let Latency = 4;} 521 522def CyWriteV64Mul : SchedWriteRes<[CyUnitVM]> { let Latency = 5;} 523def : InstRW<[CyWriteV64Mul], (instrs FMULDrr,FMULv2f64,FMULv2i64_indexed, 524 FNMULDrr,FMULX64,FMULXv2f64,FMULXv2i64_indexed)>; 525 526def CyReadVMulAcc : SchedReadAdvance<1, [CyWriteVMul, CyWriteV64Mul]>; 527def : InstRW<[CyWriteVMul, CyReadVMulAcc], 528 (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL", 529 "SQDMLAL","SQDMLSL")>; 530 531def CyWriteSMul : SchedWriteRes<[CyUnitVM]> { let Latency = 8;} 532def CyWriteDMul : SchedWriteRes<[CyUnitVM]> { let Latency = 10;} 533def CyReadSMul : SchedReadAdvance<4, [CyWriteSMul]>; 534def CyReadDMul : SchedReadAdvance<5, [CyWriteDMul]>; 535 536def : InstRW<[CyWriteSMul, CyReadSMul], 537 (instrs FMADDSrrr,FMSUBSrrr,FNMADDSrrr,FNMSUBSrrr, 538 FMLAv2f32,FMLAv4f32, 539 FMLAv1i32_indexed,FMLAv1i64_indexed,FMLAv2i32_indexed)>; 540def : InstRW<[CyWriteDMul, CyReadDMul], 541 (instrs FMADDDrrr,FMSUBDrrr,FNMADDDrrr,FNMSUBDrrr, 542 FMLAv2f64,FMLAv2i64_indexed, 543 FMLSv2f64,FMLSv2i64_indexed)>; 544 545def CyWritePMUL : SchedWriteRes<[CyUnitVD]> { let Latency = 3; } 546def : InstRW<[CyWritePMUL], (instregex "PMULv", "PMULLv")>; 547 548//--- 549// 7.9.6 Divide and Square Root 550//--- 551 552// FDIV,FSQRT 553// TODO: Add 64-bit variant with 19 cycle latency. 554// TODO: Specialize FSQRT for longer latency. 555def : WriteRes<WriteFDiv, [CyUnitVD, CyUnitFloatDiv]> { 556 let Latency = 17; 557 let ResourceCycles = [2, 17]; 558} 559 560def : InstRW<[CyWriteV4], (instregex "FRECPEv","FRECPXv","URECPEv","URSQRTEv")>; 561 562def WriteFRSQRTE : SchedWriteRes<[CyUnitVM]> { let Latency = 4; } 563def : InstRW<[WriteFRSQRTE], (instregex "FRSQRTEv")>; 564 565def WriteFRECPS : SchedWriteRes<[CyUnitVM]> { let Latency = 8; } 566def WriteFRSQRTS : SchedWriteRes<[CyUnitVM]> { let Latency = 10; } 567def : InstRW<[WriteFRECPS], (instregex "FRECPSv")>; 568def : InstRW<[WriteFRSQRTS], (instregex "FRSQRTSv")>; 569 570//--- 571// 7.9.7 Integer-FP Conversions 572//--- 573 574// FCVT lengthen f16/s32 575def : InstRW<[WriteVq], (instrs FCVTSHr,FCVTDHr,FCVTDSr)>; 576 577// FCVT,FCVTN,FCVTXN 578// SCVTF,UCVTF V,V 579// FRINT(AIMNPXZ) V,V 580def : WriteRes<WriteFCvt, [CyUnitV]> {let Latency = 4;} 581 582// SCVT/UCVT S/D, Rd = VLD5+V4: 9 cycles. 583def CyWriteCvtToFPR : WriteSequence<[WriteVLD, CyWriteV4]>; 584def : InstRW<[CyWriteCopyToFPR], (instregex "FCVT[AMNPZ][SU][SU][WX][SD]r")>; 585 586// FCVT Rd, S/D = V6+LD4: 10 cycles 587def CyWriteCvtToGPR : WriteSequence<[CyWriteV6, WriteLD]>; 588def : InstRW<[CyWriteCvtToGPR], (instregex "[SU]CVTF[SU][WX][SD]r")>; 589 590// FCVTL is a WriteV 591 592//--- 593// 7.9.8-7.9.10 Cryptography, Data Transposition, Table Lookup 594//--- 595 596def CyWriteCrypto2 : SchedWriteRes<[CyUnitVD]> {let Latency = 2;} 597def : InstRW<[CyWriteCrypto2], (instrs AESIMCrr, AESMCrr, SHA1Hrr, 598 AESDrr, AESErr, SHA1SU1rr, SHA256SU0rr, 599 SHA1SU0rrr)>; 600 601def CyWriteCrypto3 : SchedWriteRes<[CyUnitVD]> {let Latency = 3;} 602def : InstRW<[CyWriteCrypto3], (instrs SHA256SU1rrr)>; 603 604def CyWriteCrypto6 : SchedWriteRes<[CyUnitVD]> {let Latency = 6;} 605def : InstRW<[CyWriteCrypto6], (instrs SHA1Crrr, SHA1Mrrr, SHA1Prrr, 606 SHA256Hrrr,SHA256H2rrr)>; 607 608// TRN,UZP,ZUP are WriteV. 609 610// TBL,TBX are WriteV. 611 612//--- 613// 7.9.11-7.9.14 Load/Store, single element and paired 614//--- 615 616// Loading into the vector unit takes 5 cycles vs 4 for integer loads. 617def : WriteRes<WriteVLD, [CyUnitLS]> { 618 let Latency = 5; 619} 620 621// Store-load forwarding is 4 cycles. 622def : WriteRes<WriteVST, [CyUnitLS]> { 623 let Latency = 4; 624} 625 626// WriteVLDPair/VSTPair sequences are expanded by the target description. 627 628//--- 629// 7.9.15 Load, element operations 630//--- 631 632// Only the first WriteVLD and WriteAdr for writeback matches def operands. 633// Subsequent WriteVLDs consume resources. Since all loaded values have the 634// same latency, this is acceptable. 635 636// Vd is read 5 cycles after issuing the vector load. 637def : ReadAdvance<ReadVLD, 5>; 638 639def : InstRW<[WriteVLD], 640 (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 641def : InstRW<[WriteVLD, WriteAdr], 642 (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST")>; 643 644// Register writes from the load's high half are fused micro-ops. 645def : InstRW<[WriteVLD], 646 (instregex "LD1Twov(8b|4h|2s|1d)$")>; 647def : InstRW<[WriteVLD, WriteAdr], 648 (instregex "LD1Twov(8b|4h|2s|1d)_POST")>; 649def : InstRW<[WriteVLD, WriteVLD], 650 (instregex "LD1Twov(16b|8h|4s|2d)$")>; 651def : InstRW<[WriteVLD, WriteAdr, WriteVLD], 652 (instregex "LD1Twov(16b|8h|4s|2d)_POST")>; 653 654def : InstRW<[WriteVLD, WriteVLD], 655 (instregex "LD1Threev(8b|4h|2s|1d)$")>; 656def : InstRW<[WriteVLD, WriteAdr, WriteVLD], 657 (instregex "LD1Threev(8b|4h|2s|1d)_POST")>; 658def : InstRW<[WriteVLD, WriteVLD, WriteVLD], 659 (instregex "LD1Threev(16b|8h|4s|2d)$")>; 660def : InstRW<[WriteVLD, WriteAdr, WriteVLD, WriteVLD], 661 (instregex "LD1Threev(16b|8h|4s|2d)_POST")>; 662 663def : InstRW<[WriteVLD, WriteVLD], 664 (instregex "LD1Fourv(8b|4h|2s|1d)$")>; 665def : InstRW<[WriteVLD, WriteAdr, WriteVLD], 666 (instregex "LD1Fourv(8b|4h|2s|1d)_POST")>; 667def : InstRW<[WriteVLD, WriteVLD, WriteVLD, WriteVLD], 668 (instregex "LD1Fourv(16b|8h|4s|2d)$")>; 669def : InstRW<[WriteVLD, WriteAdr, WriteVLD, WriteVLD, WriteVLD], 670 (instregex "LD1Fourv(16b|8h|4s|2d)_POST")>; 671 672def : InstRW<[WriteVLDShuffle, ReadVLD], 673 (instregex "LD1i(8|16|32)$")>; 674def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr], 675 (instregex "LD1i(8|16|32)_POST")>; 676 677def : InstRW<[WriteVLDShuffle, ReadVLD], (instrs LD1i64)>; 678def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr],(instrs LD1i64_POST)>; 679 680def : InstRW<[WriteVLDShuffle], 681 (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 682def : InstRW<[WriteVLDShuffle, WriteAdr], 683 (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 684 685def : InstRW<[WriteVLDShuffle, WriteVq], 686 (instregex "LD2Twov(8b|4h|2s)$")>; 687def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVq], 688 (instregex "LD2Twov(8b|4h|2s)_POST$")>; 689def : InstRW<[WriteVLDShuffle, WriteVLDShuffle], 690 (instregex "LD2Twov(16b|8h|4s|2d)$")>; 691def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle], 692 (instregex "LD2Twov(16b|8h|4s|2d)_POST")>; 693 694def : InstRW<[WriteVLDShuffle, ReadVLD, WriteVq], 695 (instregex "LD2i(8|16|32)$")>; 696def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteVq], 697 (instregex "LD2i(8|16|32)_POST")>; 698def : InstRW<[WriteVLDShuffle, ReadVLD, WriteVq], 699 (instregex "LD2i64$")>; 700def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteVq], 701 (instregex "LD2i64_POST")>; 702 703def : InstRW<[WriteVLDShuffle, WriteVq], 704 (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 705def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVq], 706 (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST")>; 707 708def : InstRW<[WriteVLDShuffle, WriteVLDShuffle, WriteVq], 709 (instregex "LD3Threev(8b|4h|2s)$")>; 710def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle, WriteVq], 711 (instregex "LD3Threev(8b|4h|2s)_POST")>; 712def : InstRW<[WriteVLDShuffle, WriteVLDShuffle, WriteVLDShuffle], 713 (instregex "LD3Threev(16b|8h|4s|2d)$")>; 714def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle, WriteVLDShuffle], 715 (instregex "LD3Threev(16b|8h|4s|2d)_POST")>; 716 717def : InstRW<[WriteVLDShuffle, ReadVLD, WriteVq, WriteVq], 718 (instregex "LD3i(8|16|32)$")>; 719def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteVq, WriteVq], 720 (instregex "LD3i(8|16|32)_POST")>; 721 722def : InstRW<[WriteVLDShuffle, ReadVLD, WriteVLDShuffle, WriteVq], 723 (instregex "LD3i64$")>; 724def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteVLDShuffle, WriteVq], 725 (instregex "LD3i64_POST")>; 726 727def : InstRW<[WriteVLDShuffle, WriteVq, WriteVq], 728 (instregex "LD3Rv(8b|4h|2s|16b|8h|4s)$")>; 729def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVq, WriteVq], 730 (instregex "LD3Rv(8b|4h|2s|16b|8h|4s)_POST")>; 731 732def : InstRW<[WriteVLDShuffle, WriteVLDShuffle, WriteVq], 733 (instrs LD3Rv1d,LD3Rv2d)>; 734def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle, WriteVq], 735 (instrs LD3Rv1d_POST,LD3Rv2d_POST)>; 736 737def : InstRW<[WriteVLDShuffle, WriteVLDShuffle, WriteVq, WriteVq], 738 (instregex "LD4Fourv(8b|4h|2s)$")>; 739def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle, WriteVq, WriteVq], 740 (instregex "LD4Fourv(8b|4h|2s)_POST")>; 741def : InstRW<[WriteVLDPairShuffle, WriteVLDPairShuffle, 742 WriteVLDPairShuffle, WriteVLDPairShuffle], 743 (instregex "LD4Fourv(16b|8h|4s|2d)$")>; 744def : InstRW<[WriteVLDPairShuffle, WriteAdr, WriteVLDPairShuffle, 745 WriteVLDPairShuffle, WriteVLDPairShuffle], 746 (instregex "LD4Fourv(16b|8h|4s|2d)_POST")>; 747 748def : InstRW<[WriteVLDShuffle, ReadVLD, WriteVq, WriteVq, WriteVq], 749 (instregex "LD4i(8|16|32)$")>; 750def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteVq, WriteVq, WriteVq], 751 (instregex "LD4i(8|16|32)_POST")>; 752 753 754def : InstRW<[WriteVLDShuffle, ReadVLD, WriteVLDShuffle, WriteVq, WriteVq], 755 (instrs LD4i64)>; 756def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteVLDShuffle, WriteVq], 757 (instrs LD4i64_POST)>; 758 759def : InstRW<[WriteVLDShuffle, WriteVq, WriteVq, WriteVq], 760 (instregex "LD4Rv(8b|4h|2s|16b|8h|4s)$")>; 761def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVq, WriteVq, WriteVq], 762 (instregex "LD4Rv(8b|4h|2s|16b|8h|4s)_POST")>; 763 764def : InstRW<[WriteVLDShuffle, WriteVLDShuffle, WriteVq, WriteVq], 765 (instrs LD4Rv1d,LD4Rv2d)>; 766def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle, WriteVq, WriteVq], 767 (instrs LD4Rv1d_POST,LD4Rv2d_POST)>; 768 769//--- 770// 7.9.16 Store, element operations 771//--- 772 773// Only the WriteAdr for writeback matches a def operands. 774// Subsequent WriteVLDs only consume resources. 775 776def : InstRW<[WriteVST], 777 (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 778def : InstRW<[WriteAdr, WriteVST], 779 (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST")>; 780 781def : InstRW<[WriteVSTShuffle], 782 (instregex "ST1Twov(8b|4h|2s|1d)$")>; 783def : InstRW<[WriteAdr, WriteVSTShuffle], 784 (instregex "ST1Twov(8b|4h|2s|1d)_POST")>; 785def : InstRW<[WriteVST, WriteVST], 786 (instregex "ST1Twov(16b|8h|4s|2d)$")>; 787def : InstRW<[WriteAdr, WriteVST, WriteVST], 788 (instregex "ST1Twov(16b|8h|4s|2d)_POST")>; 789 790def : InstRW<[WriteVSTShuffle, WriteVST], 791 (instregex "ST1Threev(8b|4h|2s|1d)$")>; 792def : InstRW<[WriteAdr, WriteVSTShuffle, WriteVST], 793 (instregex "ST1Threev(8b|4h|2s|1d)_POST")>; 794def : InstRW<[WriteVST, WriteVST, WriteVST], 795 (instregex "ST1Threev(16b|8h|4s|2d)$")>; 796def : InstRW<[WriteAdr, WriteVST, WriteVST, WriteVST], 797 (instregex "ST1Threev(16b|8h|4s|2d)_POST")>; 798 799def : InstRW<[WriteVSTShuffle, WriteVSTShuffle], 800 (instregex "ST1Fourv(8b|4h|2s|1d)$")>; 801def : InstRW<[WriteAdr, WriteVSTShuffle, WriteVSTShuffle], 802 (instregex "ST1Fourv(8b|4h|2s|1d)_POST")>; 803def : InstRW<[WriteVST, WriteVST, WriteVST, WriteVST], 804 (instregex "ST1Fourv(16b|8h|4s|2d)$")>; 805def : InstRW<[WriteAdr, WriteVST, WriteVST, WriteVST, WriteVST], 806 (instregex "ST1Fourv(16b|8h|4s|2d)_POST")>; 807 808def : InstRW<[WriteVSTShuffle], (instregex "ST1i(8|16|32)$")>; 809def : InstRW<[WriteAdr, WriteVSTShuffle], (instregex "ST1i(8|16|32)_POST")>; 810 811def : InstRW<[WriteVSTShuffle], (instrs ST1i64)>; 812def : InstRW<[WriteAdr, WriteVSTShuffle], (instrs ST1i64_POST)>; 813 814def : InstRW<[WriteVSTShuffle], 815 (instregex "ST2Twov(8b|4h|2s)$")>; 816def : InstRW<[WriteAdr, WriteVSTShuffle], 817 (instregex "ST2Twov(8b|4h|2s)_POST")>; 818def : InstRW<[WriteVSTShuffle, WriteVSTShuffle], 819 (instregex "ST2Twov(16b|8h|4s|2d)$")>; 820def : InstRW<[WriteAdr, WriteVSTShuffle, WriteVSTShuffle], 821 (instregex "ST2Twov(16b|8h|4s|2d)_POST")>; 822 823def : InstRW<[WriteVSTShuffle], (instregex "ST2i(8|16|32)$")>; 824def : InstRW<[WriteAdr, WriteVSTShuffle], (instregex "ST2i(8|16|32)_POST")>; 825def : InstRW<[WriteVSTShuffle], (instrs ST2i64)>; 826def : InstRW<[WriteAdr, WriteVSTShuffle], (instrs ST2i64_POST)>; 827 828def : InstRW<[WriteVSTShuffle, WriteVSTShuffle], 829 (instregex "ST3Threev(8b|4h|2s)$")>; 830def : InstRW<[WriteAdr, WriteVSTShuffle, WriteVSTShuffle], 831 (instregex "ST3Threev(8b|4h|2s)_POST")>; 832def : InstRW<[WriteVSTShuffle, WriteVSTShuffle, WriteVSTShuffle], 833 (instregex "ST3Threev(16b|8h|4s|2d)$")>; 834def : InstRW<[WriteAdr, WriteVSTShuffle, WriteVSTShuffle, WriteVSTShuffle], 835 (instregex "ST3Threev(16b|8h|4s|2d)_POST")>; 836 837def : InstRW<[WriteVSTShuffle], (instregex "ST3i(8|16|32)$")>; 838def : InstRW<[WriteAdr, WriteVSTShuffle], (instregex "ST3i(8|16|32)_POST")>; 839 840def :InstRW<[WriteVSTShuffle, WriteVSTShuffle], (instrs ST3i64)>; 841def :InstRW<[WriteAdr, WriteVSTShuffle, WriteVSTShuffle], (instrs ST3i64_POST)>; 842 843def : InstRW<[WriteVSTPairShuffle, WriteVSTPairShuffle], 844 (instregex "ST4Fourv(8b|4h|2s|1d)$")>; 845def : InstRW<[WriteAdr, WriteVSTPairShuffle, WriteVSTPairShuffle], 846 (instregex "ST4Fourv(8b|4h|2s|1d)_POST")>; 847def : InstRW<[WriteVSTPairShuffle, WriteVSTPairShuffle, 848 WriteVSTPairShuffle, WriteVSTPairShuffle], 849 (instregex "ST4Fourv(16b|8h|4s|2d)$")>; 850def : InstRW<[WriteAdr, WriteVSTPairShuffle, WriteVSTPairShuffle, 851 WriteVSTPairShuffle, WriteVSTPairShuffle], 852 (instregex "ST4Fourv(16b|8h|4s|2d)_POST")>; 853 854def : InstRW<[WriteVSTPairShuffle], (instregex "ST4i(8|16|32)$")>; 855def : InstRW<[WriteAdr, WriteVSTPairShuffle], (instregex "ST4i(8|16|32)_POST")>; 856 857def : InstRW<[WriteVSTShuffle, WriteVSTShuffle], (instrs ST4i64)>; 858def : InstRW<[WriteAdr, WriteVSTShuffle, WriteVSTShuffle],(instrs ST4i64_POST)>; 859 860// Atomic operations are not supported. 861def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 862 863//--- 864// Unused SchedRead types 865//--- 866 867def : ReadAdvance<ReadI, 0>; 868def : ReadAdvance<ReadISReg, 0>; 869def : ReadAdvance<ReadIEReg, 0>; 870def : ReadAdvance<ReadIM, 0>; 871def : ReadAdvance<ReadIMA, 0>; 872def : ReadAdvance<ReadID, 0>; 873 874} // SchedModel = CycloneModel 875